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REJ09B0320-0200
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32
SuperH
TM
SH7261Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer RISC engine Family / SH7260 Series R5S72611 R5S72612 R5S72613
Rev.2.00 Revision Date: Sep. 07, 2007
Rev. 2.00 Sep. 07, 2007 Page ii of xxxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 2.00 Sep. 07, 2007 Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products that have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Processing when the Power Supply Voltage is beyond the Operating Voltage Specification* When the power supply voltage exceeds the operating voltage specification, erroneous operation may occur. To prevent this, design your system so that it does not malfunction. For example, the system should be reset after the power supply voltage is changed to a value within the operating voltage specification. Note: * The voltage must be within the range up to the absolute maximum rating. The LSI may be permanently damaged if the absolute maximum rating is exceeded. 5. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. 6. Reading from/Writing to Reserved Bit of Each Register Treat the reserved bit of a register used in each module as follows except in cases where the specifications for values which are read from or written to the bit are provided in the description. The bit is always read as 0. The write value should be 0 or one, which has been read immediately before writing. Writing the value, which has been read immediately before writing, has the advantage of preventing the bit from being affected on its extended function when the function is assigned.
Rev. 2.00 Sep. 07, 2007 Page iv of xxxii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix * Product Type, Package Dimensions, etc. 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 2.00 Sep. 07, 2007 Page v of xxxii
Preface
This LSI is an RISC (Reduced Instruction Set Computer) microcomputer that includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-2A, SH2A-FPU Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 30, List of Registers.
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* Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below.
(1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF
(4) (2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and do not refer to specific data in this manual.
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* Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below.
[Bit Chart]
Bit: 15 Initial value: R/W: 0 R/W 14 0 R/W 13 12 11 10 0 R 9 1 R 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 Q 0 R/W 3 2 1 0 IFE 0 R/W
ASID2 ASID1 ASID0 0 R/W 0 R/W 0 R/W
ACMP2 ACMP1 ACMP0 0 R/W 0 R/W 0 R/W
[Table of Bits]
(1) Bit 15 14 13 to 11 10 9
(2) Bit Name - - ASID2 to ASID0 - - -
(3)
(4) Description
(5) Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1.
Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual.
(1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. The bit or field is readable. R: "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. The bit or field is writable. W: (5) Description Describes the function of the bit or field and specifies the values for writing.
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Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 1.4 1.5 SH7261 Group Features......................................................................................................... 1 Product Lineup..................................................................................................................... 10 Block Diagram ..................................................................................................................... 11 Pin Assignments................................................................................................................... 12 Pin Functions ....................................................................................................................... 15
Section 2 CPU......................................................................................................23
2.1 Register Configuration......................................................................................................... 23 2.1.1 General Registers.................................................................................................... 23 2.1.2 Control Registers .................................................................................................... 24 2.1.3 System Registers..................................................................................................... 26 2.1.4 Register Banks ........................................................................................................ 27 2.1.5 Initial Values of Registers....................................................................................... 27 Data Formats........................................................................................................................ 28 2.2.1 Data Format in Registers ........................................................................................ 28 2.2.2 Data Formats in Memory ........................................................................................ 28 2.2.3 Immediate Data Format .......................................................................................... 29 Instruction Features.............................................................................................................. 30 2.3.1 RISC-Type Instruction Set...................................................................................... 30 2.3.2 Addressing Modes .................................................................................................. 34 2.3.3 Instruction Format................................................................................................... 38 Instruction Set ...................................................................................................................... 42 2.4.1 Instruction Set by Classification ............................................................................. 42 2.4.2 Data Transfer Instructions....................................................................................... 48 2.4.3 Arithmetic Operation Instructions .......................................................................... 52 2.4.4 Logic Operation Instructions .................................................................................. 55 2.4.5 Shift Instructions..................................................................................................... 56 2.4.6 Branch Instructions ................................................................................................. 57 2.4.7 System Control Instructions.................................................................................... 58 2.4.8 Floating Point Operation Instructions ..................................................................... 60 2.4.9 FPU-Related CPU Instructions ............................................................................... 62 2.4.10 Bit Manipulation Instructions ................................................................................. 63 Processing States.................................................................................................................. 64
2.2
2.3
2.4
2.5
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Section 3 Floating-Point Unit (FPU)................................................................... 67
3.1 3.2 Features................................................................................................................................ 67 Data Formats........................................................................................................................ 67 3.2.1 Floating-Point Format............................................................................................. 67 3.2.2 Non-Numbers (NaN) .............................................................................................. 69 3.2.3 Denormalized Numbers .......................................................................................... 70 Register Descriptions........................................................................................................... 71 3.3.1 Floating-Point Registers ......................................................................................... 71 3.3.2 Floating-Point Status/Control Register (FPSCR) ................................................... 72 3.3.3 Floating-Point Communication Register (FPUL) ................................................... 73 Rounding.............................................................................................................................. 74 Floating-Point Exceptions.................................................................................................... 75 3.5.1 FPU Exception Sources .......................................................................................... 75 3.5.2 FPU Exception Handling ........................................................................................ 75
3.3
3.4 3.5
Section 4 Clock Pulse Generator (CPG) ............................................................. 77
4.1 4.2 4.3 4.4 Features................................................................................................................................ 77 Input/Output Pins................................................................................................................. 80 Clock Operating Modes ....................................................................................................... 81 Register Descriptions........................................................................................................... 87 4.4.1 Frequency Control Register (FRQCR) ................................................................... 87 4.4.2 CKIO Control Register (CKIOCR) ........................................................................ 90 Changing the Frequency ...................................................................................................... 91 4.5.1 Changing the Multiplication Rate........................................................................... 91 4.5.2 Changing the Division Ratio................................................................................... 92 Notes on Board Design ........................................................................................................ 92 4.6.1 Note on Inputting External Clock ........................................................................... 92 4.6.2 Note on Using Crystal Resonator ........................................................................... 93 4.6.3 Note on Resonator .................................................................................................. 93 4.6.4 Note on Using a PLL Oscillation Circuit................................................................ 94 4.6.5 Note on Changing the Multiplication Rate ............................................................. 94
4.5
4.6
Section 5 Exception Handling ............................................................................. 95
5.1 Overview.............................................................................................................................. 95 5.1.1 Types of Exception Handling and Priority ............................................................. 95 5.1.2 Exception Handling Operations.............................................................................. 97 5.1.3 Exception Handling Vector Table .......................................................................... 99 Resets................................................................................................................................. 101 5.2.1 Input/Output Pins.................................................................................................. 101
5.2
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5.2.2 Types of Reset ...................................................................................................... 101 5.2.3 Power-On Reset .................................................................................................... 102 5.2.4 Manual Reset ........................................................................................................ 104 5.3 Address Errors ................................................................................................................... 105 5.3.1 Address Error Sources .......................................................................................... 105 5.3.2 Address Error Exception Handling ....................................................................... 106 5.4 Bus Error............................................................................................................................ 106 5.4.1 Bus Error Generation Source ................................................................................ 106 5.4.2 Bus Error Exception Handling.............................................................................. 106 5.5 Register Bank Errors.......................................................................................................... 107 5.5.1 Register Bank Error Sources................................................................................. 107 5.5.2 Register Bank Error Exception Handling ............................................................. 107 5.6 Interrupts............................................................................................................................ 108 5.6.1 Interrupt Sources................................................................................................... 108 5.6.2 Interrupt Priority Level ......................................................................................... 109 5.6.3 Interrupt Exception Handling ............................................................................... 110 5.7 Exceptions Triggered by Instructions ................................................................................ 111 5.7.1 Types of Exceptions Triggered by Instructions .................................................... 111 5.7.2 Trap Instructions ................................................................................................... 112 5.7.3 Slot Illegal Instructions ......................................................................................... 112 5.7.4 General Illegal Instructions................................................................................... 112 5.7.5 Integer Division Instructions................................................................................. 113 5.7.6 Floating-point Operation Instruction .................................................................... 113 5.8 When Exception Sources Are Not Accepted ..................................................................... 114 5.9 Stack Status after Exception Handling Ends...................................................................... 115 5.10 Usage Notes ....................................................................................................................... 117 5.10.1 Value of Stack Pointer (SP) .................................................................................. 117 5.10.2 Value of Vector Base Register (VBR) .................................................................. 117 5.10.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 117
Section 6 Interrupt Controller (INTC) ...............................................................119
6.1 6.2 6.3 Features.............................................................................................................................. 119 Input/Output Pins ............................................................................................................... 121 Register Descriptions ......................................................................................................... 121 6.3.1 Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to IPR16) .... 123 6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 125 6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 126 6.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 127 6.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 127 6.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 129
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6.3.7 PINT Interrupt Request Register (PIRR) .............................................................. 130 6.3.8 Bank Control Register (IBCR).............................................................................. 131 6.3.9 Bank Number Register (IBNR) ............................................................................ 132 6.3.10 DMA Transfer Request Enable Register 0 (DREQER0) ...................................... 133 6.3.11 DMA Transfer Request Enable Register 1 (DREQER1) ...................................... 134 6.3.12 DMA Transfer Request Enable Register 2 (DREQER2) ...................................... 135 6.3.13 DMA Transfer Request Enable Register 3 (DREQER3) ...................................... 136 6.4 Interrupt Sources................................................................................................................ 137 6.4.1 NMI Interrupt........................................................................................................ 137 6.4.2 User Break Interrupt ............................................................................................. 137 6.4.3 H-UDI Interrupt .................................................................................................... 137 6.4.4 IRQ Interrupts....................................................................................................... 138 6.4.5 PINT Interrupts..................................................................................................... 139 6.4.6 On-Chip Peripheral Module Interrupts ................................................................. 139 6.5 Interrupt Exception Handling Vector Table and Priority................................................... 140 6.6 Operation ........................................................................................................................... 150 6.6.1 Interrupt Operation Sequence ............................................................................... 150 6.6.2 Stack after Interrupt Exception Handling ............................................................. 152 6.7 Interrupt Response Time.................................................................................................... 153 6.8 Register Banks ................................................................................................................... 158 6.8.1 Register Banks and Bank Control Registers ......................................................... 159 6.8.2 Bank Save and Restore Operations....................................................................... 159 6.8.3 Save and Restore Operations after Saving to All Banks....................................... 161 6.8.4 Register Bank Exception ...................................................................................... 162 6.8.5 Register Bank Error Exception Handling ............................................................. 162 6.9 Data Transfer with Interrupt Request Signals.................................................................... 163 6.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but not DMAC Activation .......................................................................................... 163 6.9.2 Handling Interrupt Request Signals as Sources for DMAC Activation but not CPU Interrupt ................................................................................................. 163 6.10 Usage Note......................................................................................................................... 164 6.10.1 Timing to Clear an Interrupt Source ..................................................................... 164
Section 7 User Break Controller (UBC)............................................................ 165
7.1 7.2 7.3 Features.............................................................................................................................. 165 Input/Output Pin ................................................................................................................ 167 Register Descriptions......................................................................................................... 167 7.3.1 Break Address Register (BAR)............................................................................. 168 7.3.2 Break Address Mask Register (BAMR) ............................................................... 169 7.3.3 Break Data Register (BDR) .................................................................................. 170
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7.4
7.5
7.3.4 Break Data Mask Register (BDMR)..................................................................... 171 7.3.5 Break Bus Cycle Register (BBR).......................................................................... 172 7.3.6 Break Control Register (BRCR) ........................................................................... 174 Operation ........................................................................................................................... 177 7.4.1 Flow of the User Break Operation ........................................................................ 177 7.4.2 Break on Instruction Fetch Cycle.......................................................................... 178 7.4.3 Break on Data Access Cycle................................................................................. 179 7.4.4 Value of Saved Program Counter ......................................................................... 180 7.4.5 Usage Examples.................................................................................................... 181 Usage Notes ....................................................................................................................... 184
Section 8 Cache .................................................................................................187
8.1 8.2 Features.............................................................................................................................. 187 8.1.1 Cache Structure..................................................................................................... 187 Register Descriptions ......................................................................................................... 190 8.2.1 Cache Control Register 1 (CCR1) ........................................................................ 190 8.2.2 Cache Control Register 2 (CCR2) ........................................................................ 192 Operation ........................................................................................................................... 195 8.3.1 Searching Cache ................................................................................................... 195 8.3.2 Read Access.......................................................................................................... 197 8.3.3 Prefetch Operation (Only for Operand Cache) ..................................................... 197 8.3.4 Write Operation (Only for Operand Cache).......................................................... 197 8.3.5 Write-Back Buffer (Only for Operand Cache)...................................................... 198 8.3.6 Coherency of Cache and External Memory .......................................................... 200 Memory-Mapped Cache .................................................................................................... 200 8.4.1 Address Array ....................................................................................................... 200 8.4.2 Data Array ............................................................................................................ 201 8.4.3 Usage Examples.................................................................................................... 203 8.4.4 Notes ..................................................................................................................... 204
8.3
8.4
Section 9 Bus State Controller (BSC)................................................................205
9.1 9.2 9.3 Features.............................................................................................................................. 205 Input/Output Pins ............................................................................................................... 207 Area Overview ................................................................................................................... 209 9.3.1 Address Map ......................................................................................................... 209 9.3.2 Data Bus Width and Pin Function Setting for Individual Areas ........................... 210 Register Descriptions ......................................................................................................... 211 9.4.1 CSn Control Register (CSnCNT) (n = 0 to 6)....................................................... 213 9.4.2 CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ............................. 215 9.4.3 SDRAMCm Control Register (SDCmCNT) (m = 0, 1)........................................ 217
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9.4
9.5
9.6
9.4.4 CSn Mode Register (CSMODn) (n = 0 to 6) ........................................................ 218 9.4.5 CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6) ..................................... 221 9.4.6 CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6) ..................................... 223 9.4.7 SDRAM Refresh Control Register 0 (SDRFCNT0)............................................. 226 9.4.8 SDRAM Refresh Control Register 1 (SDRFCNT1)............................................. 227 9.4.9 SDRAM Initialization Register 0 (SDIR0)........................................................... 229 9.4.10 SDRAM Initialization Register 1 (SDIR1)........................................................... 231 9.4.11 SDRAM Power-Down Control Register (SDPWDCNT) ..................................... 232 9.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT) ........................ 233 9.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)............................................ 234 9.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1) ................................................ 235 9.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)............................................... 237 9.4.16 SDRAM Status Register (SDSTR) ....................................................................... 238 9.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .................. 240 9.4.18 AC Characteristics Switching Register (ACSWR) ............................................... 241 Operation ........................................................................................................................... 242 9.5.1 CSC Interface........................................................................................................ 242 9.5.2 SDRAM Interface ................................................................................................. 252 Usage Note......................................................................................................................... 288 9.6.1 Note on Power-on Reset Exception Handling and Deep Standby Mode Cancellation .......................................................................................................... 288 9.6.2 Write Buffer.......................................................................................................... 288 9.6.3 Note on Transition to Software Standby Mode or Deep Standby Mode............... 289
Section 10 Bus Monitor..................................................................................... 291
10.1 Register Descriptions......................................................................................................... 291 10.1.1 Bus Monitor Enable Register (SYCBEEN) .......................................................... 292 10.1.2 Bus Monitor Status Register 1 (SYCBESTS1)..................................................... 293 10.1.3 Bus Monitor Status Register 2 (SYCBESTS2)..................................................... 295 10.1.4 Bus Error Control Register (SYCBESW)............................................................. 298 10.2 Bus Monitor Function........................................................................................................ 299 10.2.1 Operation when a Bus Error is Detected............................................................... 299 10.2.2 Illegal Address Access Detection Function .......................................................... 300 10.2.3 Bus Timeout Detection Function .......................................................................... 302 10.2.4 Combinations of Masters and Bus Errors ............................................................. 303 10.3 Usage Note......................................................................................................................... 304 10.3.1 Operation when the CPU is Not Notified of a Bus Error...................................... 304
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Section 11 Direct Memory Access Controller (DMAC) ...................................305
11.1 Features.............................................................................................................................. 305 11.2 Input/Output Pins ............................................................................................................... 307 11.3 Register Descriptions ......................................................................................................... 308 11.3.1 DMA Current Source Address Register (DMCSADR) ........................................ 312 11.3.2 DMA Current Destination Address Register (DMCDADR) ................................ 313 11.3.3 DMA Current Byte Count Register (DMCBCT) .................................................. 314 11.3.4 DMA Reload Source Address Register (DMRSADR) ......................................... 315 11.3.5 DMA Reload Destination Address Register (DMRDADR) ................................. 316 11.3.6 DMA Reload Byte Count Register (DMRBCT) ................................................... 317 11.3.7 DMA Mode Register (DMMOD) ......................................................................... 318 11.3.8 DMA Control Register A (DMCNTA) ................................................................. 324 11.3.9 DMA Control Register B (DMCNTB) ................................................................. 332 11.3.10 DMA Activation Control Register (DMSCNT).................................................... 338 11.3.11 DMA Interrupt Control Register (DMICNT) ....................................................... 339 11.3.12 DMA Common Interrupt Control Register (DMICNTA)..................................... 340 11.3.13 DMA Interrupt Status Register (DMISTS) ........................................................... 341 11.3.14 DMA Transfer End Detection Register (DMEDET) ............................................ 342 11.3.15 DMA Arbitration Status Register (DMASTS)...................................................... 344 11.4 Operation ........................................................................................................................... 346 11.4.1 DMA Transfer Mode ............................................................................................ 346 11.4.2 DMA Transfer Condition...................................................................................... 348 11.4.3 DMA Activation ................................................................................................... 352 11.5 Completion of DMA Transfer and Interrupts .................................................................... 353 11.5.1 Completion of DMA Transfer .............................................................................. 353 11.5.2 DMA Interrupt Requests....................................................................................... 354 11.5.3 DMA End Signal Output ...................................................................................... 356 11.6 Suspending, Restarting, and Stopping of DMA Transfer .................................................. 358 11.6.1 Suspending and Restarting DMA Transfer ........................................................... 358 11.6.2 Stopping DMA Transfer on Any Channel ............................................................ 358 11.7 DMA Requests................................................................................................................... 359 11.7.1 Sources of DMA Requests.................................................................................... 359 11.7.2 Synchronous Circuits for DMA Request Signals.................................................. 359 11.7.3 Sense Mode for DMA Requests............................................................................ 360 11.8 Determining DMA Channel Priority.................................................................................. 363 11.8.1 Channel Priority Order.......................................................................................... 363 11.8.2 Operation during Multiple DMA Requests........................................................... 363 11.8.3 Output of the DMA Acknowledge and DNA Active Signals ............................... 364 11.9 Units of Transfer and Positioning of Bytes for Transfer.................................................... 366
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11.10 11.11 11.12 11.13
Reload Function................................................................................................................. 367 Rotate Function.................................................................................................................. 369 Transfer Speed ................................................................................................................... 370 Usage Note......................................................................................................................... 371 11.13.1 Note on Making a Transition To Software Standby Mode or Deep Standby Mode ............................................................................................. 371
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 373
12.1 Features.............................................................................................................................. 373 12.2 Input/Output Pins............................................................................................................... 379 12.3 Register Descriptions......................................................................................................... 380 12.3.1 Timer Control Register (TCR).............................................................................. 386 12.3.2 Timer Mode Register (TMDR)............................................................................. 390 12.3.3 Timer I/O Control Register (TIOR)...................................................................... 393 12.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 412 12.3.5 Timer Interrupt Enable Register (TIER)............................................................... 413 12.3.6 Timer Status Register (TSR)................................................................................. 418 12.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 425 12.3.8 Timer Input Capture Control Register (TICCR)................................................... 426 12.3.9 Timer A/D Converter Start Request Control Register (TADCR) ......................... 427 12.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4)...................................................................... 430 12.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) ................................................................ 431 12.3.12 Timer Counter (TCNT)......................................................................................... 431 12.3.13 Timer General Register (TGR) ............................................................................. 432 12.3.14 Timer Start Register (TSTR) ................................................................................ 433 12.3.15 Timer Synchronous Register (TSYR)................................................................... 435 12.3.16 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 437 12.3.17 Timer Read/Write Enable Register (TRWER) ..................................................... 439 12.3.18 Timer Output Master Enable Register (TOER) .................................................... 440 12.3.19 Timer Output Control Register 1 (TOCR1).......................................................... 441 12.3.20 Timer Output Control Register 2 (TOCR2).......................................................... 444 12.3.21 Timer Output Level Buffer Register (TOLBR) .................................................... 447 12.3.22 Timer Gate Control Register (TGCR) .................................................................. 448 12.3.23 Timer Subcounter (TCNTS) ................................................................................. 450 12.3.24 Timer Dead Time Data Register (TDDR)............................................................. 451 12.3.25 Timer Cycle Data Register (TCDR) ..................................................................... 451 12.3.26 Timer Cycle Buffer Register (TCBR)................................................................... 452 12.3.27 Timer Interrupt Skipping Set Register (TITCR)................................................... 452
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12.4
12.5
12.6
12.7
12.3.28 Timer Interrupt Skipping Counter (TITCNT)....................................................... 454 12.3.29 Timer Buffer Transfer Set Register (TBTER) ...................................................... 455 12.3.30 Timer Dead Time Enable Register (TDER).......................................................... 457 12.3.31 Timer Waveform Control Register (TWCR) ........................................................ 458 12.3.32 Bus Master Interface............................................................................................. 459 Operation ........................................................................................................................... 460 12.4.1 Basic Functions..................................................................................................... 460 12.4.2 Synchronous Operation......................................................................................... 466 12.4.3 Buffer Operation ................................................................................................... 468 12.4.4 Cascaded Operation .............................................................................................. 473 12.4.5 PWM Modes ......................................................................................................... 478 12.4.6 Phase Counting Mode........................................................................................... 483 12.4.7 Reset-Synchronized PWM Mode.......................................................................... 490 12.4.8 Complementary PWM Mode................................................................................ 493 12.4.9 A/D Converter Start Request Delaying Function.................................................. 529 12.4.10 External Pulse Width Measurement...................................................................... 533 12.4.11 Dead Time Compensation..................................................................................... 534 12.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 536 Interrupt Sources................................................................................................................ 537 12.5.1 Interrupt Sources and Priorities ............................................................................ 537 12.5.2 DMAC Activation................................................................................................. 539 12.5.3 A/D Converter Activation..................................................................................... 539 Operation Timing............................................................................................................... 541 12.6.1 Input/Output Timing ............................................................................................. 541 12.6.2 Interrupt Signal Timing......................................................................................... 548 Usage Notes ....................................................................................................................... 552 12.7.1 Module Standby Mode Setting ............................................................................. 552 12.7.2 Input Clock Restrictions ....................................................................................... 552 12.7.3 Caution on Period Setting ..................................................................................... 553 12.7.4 Contention between TCNT Write and Clear Operations...................................... 554 12.7.5 Contention between TCNT Write and Increment Operations............................... 554 12.7.6 Contention between TGR Write and Compare Match .......................................... 555 12.7.7 Contention between Buffer Register Write and Compare Match ......................... 556 12.7.8 Contention between Buffer Register Write and TCNT Clear ............................... 557 12.7.9 Contention between TGR Read and Input Capture............................................... 558 12.7.10 Contention between TGR Write and Input Capture.............................................. 559 12.7.11 Contention between Buffer Register Write and Input Capture ............................. 560 12.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 560 12.7.13 Counter Value during Complementary PWM Mode Stop .................................... 562 12.7.14 Buffer Operation Setting in Complementary PWM Mode ................................... 562
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12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 563 12.7.16 Overflow Flags in Reset Synchronous PWM Mode ............................................. 564 12.7.17 Contention between Overflow/Underflow and Counter Clearing......................... 565 12.7.18 Contention between TCNT Write and Overflow/Underflow................................ 566 12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode ......................................................................... 566 12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode .......................................................................................................... 567 12.7.21 Interrupts in Module Standby Mode ..................................................................... 567 12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 567 12.8 MTU2 Output Pin Initialization......................................................................................... 568 12.8.1 Operating Modes .................................................................................................. 568 12.8.2 Reset Start Operation ............................................................................................ 568 12.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 569 12.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. .................................................................................. 570
Section 13 8-Bit Timers (TMR) ........................................................................ 601
13.1 Features.............................................................................................................................. 601 13.2 Input/Output Pins............................................................................................................... 603 13.3 Register Descriptions......................................................................................................... 603 13.3.1 Timer Counter (TCNT)......................................................................................... 604 13.3.2 Time Constant Register A (TCORA) ................................................................... 604 13.3.3 Time Constant Register B (TCORB).................................................................... 605 13.3.4 Timer Control Register (TCR).............................................................................. 605 13.3.5 Timer Counter Control Register (TCCR) ............................................................. 607 13.3.6 Timer Control/Status Register (TCSR)................................................................. 609 13.4 Operation ........................................................................................................................... 613 13.4.1 Pulse Output ......................................................................................................... 613 13.4.2 Reset Input............................................................................................................ 614 13.5 Operation Timing............................................................................................................... 615 13.5.1 TCNT Count Timing ............................................................................................ 615 13.5.2 Timing of CMFA and CMFB Setting at Compare Match .................................... 616 13.5.3 Timing of Timer Output at Compare Match......................................................... 616 13.5.4 Timing of Counter Clear by Compare Match ....................................................... 617 13.5.5 Timing of TCNT External Reset........................................................................... 617 13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 618 13.6 Operation with Cascaded Connection................................................................................ 618 13.6.1 16-Bit Counter Mode ............................................................................................ 618 13.6.2 Compare Match Count Mode ............................................................................... 619
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13.7 Interrupt Sources................................................................................................................ 619 13.7.1 Interrupt Sources................................................................................................... 619 13.7.2 A/D Converter Activation..................................................................................... 620 13.8 Usage Notes ....................................................................................................................... 620 13.8.1 Notes on Setting Cycle.......................................................................................... 620 13.8.2 Conflict between TCNT Write and Clear ............................................................. 620 13.8.3 Conflict between TCNT Write and Increment...................................................... 621 13.8.4 Conflict between TCOR Write and Compare Match ............................................ 621 13.8.5 Conflict between Compare Matches A and B....................................................... 622 13.8.6 Switching of Internal Clocks and TCNT Operation.............................................. 622 13.8.7 Mode Setting with Cascaded Connection ............................................................. 624 13.8.8 Module Standby Setting........................................................................................ 624 13.8.9 Interrupts in Module Standby Mode ..................................................................... 624
Section 14 Watchdog Timer (WDT)..................................................................625
14.1 Features.............................................................................................................................. 625 14.2 Input/Output Pin................................................................................................................. 626 14.3 Register Descriptions ......................................................................................................... 627 14.3.1 Watchdog Timer Counter (WTCNT).................................................................... 627 14.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 628 14.3.3 Watchdog Reset Control/Status Register (WRCSR) ............................................ 630 14.3.4 Notes on Register Access...................................................................................... 631 14.4 WDT Usage ....................................................................................................................... 633 14.4.1 Canceling Software Standby Mode....................................................................... 633 14.4.2 Changing the Frequency ....................................................................................... 633 14.4.3 Using Watchdog Timer Mode .............................................................................. 634 14.4.4 Using Interval Timer Mode .................................................................................. 635 14.5 Usage Notes ....................................................................................................................... 636 14.5.1 Timer Variation..................................................................................................... 636 14.5.2 Prohibition against Setting H'FF to WTCNT........................................................ 636 14.5.3 System Reset by WDTOVF Signal....................................................................... 636 14.5.4 Manual Reset in Watchdog Timer Mode .............................................................. 637
Section 15 Realtime Clock (RTC) .....................................................................639
15.1 Features.............................................................................................................................. 639 15.2 Input/Output Pin................................................................................................................. 641 15.3 Register Descriptions ......................................................................................................... 641 15.3.1 64-Hz Counter (R64CNT) .................................................................................... 642 15.3.2 Second Counter (RSECCNT) ............................................................................... 643 15.3.3 Minute Counter (RMINCNT) ............................................................................... 644
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15.3.4 Hour Counter (RHRCNT) .................................................................................... 645 15.3.5 Day of Week Counter (RWKCNT) ...................................................................... 646 15.3.6 Date Counter (RDAYCNT) .................................................................................. 647 15.3.7 Month Counter (RMONCNT) .............................................................................. 648 15.3.8 Year Counter (RYRCNT)..................................................................................... 649 15.3.9 Second Alarm Register (RSECAR) ...................................................................... 650 15.3.10 Minute Alarm Register (RMINAR)...................................................................... 651 15.3.11 Hour Alarm Register (RHRAR) ........................................................................... 652 15.3.12 Day of Week Alarm Register (RWKAR) ............................................................. 653 15.3.13 Date Alarm Register (RDAYAR)......................................................................... 654 15.3.14 Month Alarm Register (RMONAR) ..................................................................... 655 15.3.15 Year Alarm Register (RYRAR)............................................................................ 656 15.3.16 RTC Control Register 1 (RCR1)........................................................................... 657 15.3.17 RTC Control Register 2 (RCR2)........................................................................... 659 15.3.18 RTC Control Register 3 (RCR3)........................................................................... 661 15.4 Operation ........................................................................................................................... 662 15.4.1 Initial Settings of Registers after Power-On ......................................................... 662 15.4.2 Setting Time ......................................................................................................... 662 15.4.3 Reading Time........................................................................................................ 663 15.4.4 Alarm Function..................................................................................................... 664 15.5 Usage Notes ....................................................................................................................... 665 15.5.1 Register Writing during RTC Count..................................................................... 665 15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts................................................ 665 15.5.3 Transition to Standby Mode after Setting Register............................................... 666 15.5.4 Crystal Oscillator Circuit for RTC........................................................................ 666 15.5.5 Procedure for Setting the 30-Second Adjustment Function.................................. 667
Section 16 Serial Communication Interface with FIFO (SCIF)........................ 669
16.1 Features.............................................................................................................................. 669 16.2 Input/Output Pins............................................................................................................... 671 16.3 Register Descriptions......................................................................................................... 671 16.3.1 Receive Shift Register (SCRSR) .......................................................................... 675 16.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 675 16.3.3 Transmit Shift Register (SCTSR) ......................................................................... 676 16.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 676 16.3.5 Serial Mode Register (SCSMR)............................................................................ 677 16.3.6 Serial Control Register (SCSCR).......................................................................... 680 16.3.7 Serial Status Register (SCFSR) ............................................................................ 684 16.3.8 Bit Rate Register (SCBRR) .................................................................................. 692 16.3.9 FIFO Control Register (SCFCR) .......................................................................... 700
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16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 702 16.3.11 Serial Port Register (SCSPTR) ............................................................................. 703 16.3.12 Line Status Register (SCLSR) .............................................................................. 705 16.4 Operation ........................................................................................................................... 706 16.4.1 Overview............................................................................................................... 706 16.4.2 Operation in Asynchronous Mode ........................................................................ 708 16.4.3 Operation in Clocked Synchronous Mode ............................................................ 717 16.5 SCIF Interrupts .................................................................................................................. 725 16.6 Usage Notes ....................................................................................................................... 726 16.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 726 16.6.2 SCFRDR Reading and RDF Flag ......................................................................... 726 16.6.3 Restriction on DMAC Usage ................................................................................ 727 16.6.4 Break Detection and Processing ........................................................................... 727 16.6.5 Sending a Break Signal......................................................................................... 727 16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 728
Section 17 I2C Bus Interface 3 (IIC3) ................................................................729
17.1 Features.............................................................................................................................. 729 17.2 Input/Output Pins ............................................................................................................... 731 17.3 Register Descriptions ......................................................................................................... 732 17.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 733 17.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 736 17.3.3 I2C Bus Mode Register (ICMR)............................................................................ 738 17.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 740 17.3.5 I2C Bus Status Register (ICSR)............................................................................. 742 17.3.6 Slave Address Register (SAR).............................................................................. 745 17.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 746 17.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 746 17.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 746 17.3.10 NF2CYC Register (NF2CYC) .............................................................................. 747 17.4 Operation ........................................................................................................................... 748 17.4.1 I2C Bus Format...................................................................................................... 748 17.4.2 Master Transmit Operation ................................................................................... 749 17.4.3 Master Receive Operation..................................................................................... 751 17.4.4 Slave Transmit Operation ..................................................................................... 753 17.4.5 Slave Receive Operation....................................................................................... 756 17.4.6 Clocked Synchronous Serial Format..................................................................... 757 17.4.7 Noise Filter ........................................................................................................... 761 17.4.8 Example of Use..................................................................................................... 762 17.5 Interrupt Requests .............................................................................................................. 766
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17.6 Bit Synchronous Circuit..................................................................................................... 767 17.7 Usage Note......................................................................................................................... 770 17.7.1 Issuance of Stop Condition and Start Condition (Retransmission)....................... 770 17.7.2 Settings for Multi-Master Operation..................................................................... 770 17.7.3 Reading ICDRR in Master Receive Mode............................................................ 770
Section 18 Serial Sound Interface (SSI)............................................................ 771
18.1 Features.............................................................................................................................. 771 18.2 Input/Output Pins............................................................................................................... 773 18.3 Register Description .......................................................................................................... 774 18.3.1 Control Register (SSICR) ..................................................................................... 775 18.3.2 Status Register (SSISR) ........................................................................................ 781 18.3.3 Transmit Data Register (SSITDR)........................................................................ 786 18.3.4 Receive Data Register (SSIRDR) ......................................................................... 786 18.4 Operation Description........................................................................................................ 787 18.4.1 Bus Format ........................................................................................................... 787 18.4.2 Non-Compressed Modes....................................................................................... 788 18.4.3 Operation Modes .................................................................................................. 798 18.4.4 Transmit Operation............................................................................................... 799 18.4.5 Receive Operation ................................................................................................ 802 18.4.6 Temporary Stop and Restart Procedures in Transmit Mode ................................. 805 18.4.7 Serial Bit Clock Control ....................................................................................... 806 18.5 Usage Notes ....................................................................................................................... 806 18.5.1 Limitations from Overflow during Receive DMA Operation............................... 806 18.5.2 Note on Using Oversample Clock ........................................................................ 807 18.5.3 Restriction on Stopping Clock Supply.................................................................. 807
Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]...................................................................................... 809
19.1 Summary............................................................................................................................ 809 19.1.1 Overview .............................................................................................................. 809 19.1.2 Scope .................................................................................................................... 809 19.1.3 Audience............................................................................................................... 809 19.1.4 References ............................................................................................................ 810 19.1.5 Features................................................................................................................. 810 19.2 Architecture ....................................................................................................................... 811 19.2.1 Block Diagram...................................................................................................... 811 19.2.2 Functions of Each Block....................................................................................... 812 19.2.3 Input/Output Pins.................................................................................................. 813 19.2.4 Memory Map ........................................................................................................ 814
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19.3 Mailbox.............................................................................................................................. 815 19.3.1 Mailbox Structure ................................................................................................. 815 19.3.2 Message Control Field .......................................................................................... 817 19.3.3 Local Acceptance Filter Mask (LAFM)................................................................ 821 19.3.4 Message Data Fields ............................................................................................. 822 19.4 RCAN-ET Control Registers ............................................................................................. 823 19.4.1 Master Control Register (MCR) ........................................................................... 823 19.4.2 General Status Register (GSR) ............................................................................. 829 19.4.3 Bit Configuration Register (BCR0, BCR1) .......................................................... 832 19.4.4 Interrupt Request Register (IRR) .......................................................................... 837 19.4.5 Interrupt Mask Register (IMR) ............................................................................. 843 19.4.6 Transmit Error Counter (TEC) and Receive Error Counter (REC)....................... 844 19.5 RCAN-ET Mailbox Registers............................................................................................ 845 19.5.1 Transmit Pending Register (TXPR0, TXPR1)...................................................... 846 19.5.2 Transmit Cancel Register 0 (TXCR0) .................................................................. 849 19.5.3 Transmit Acknowledge Register 0 (TXACK0) .................................................... 850 19.5.4 Abort Acknowledge Register 0 (ABACK0) ......................................................... 851 19.5.5 Data Frame Receive Pending Register 0 (RXPR0)............................................... 852 19.5.6 Remote Frame Receive Pending Register 0 (RFPR0) .......................................... 853 19.5.7 Mailbox Interrupt Mask Register 0 (MBIMR0).................................................... 854 19.5.8 Unread Message Status Register 0 (UMSR0)....................................................... 855 19.6 Application Note................................................................................................................ 856 19.6.1 Configuration of RCAN-ET ................................................................................. 856 19.6.2 Test Mode Settings ............................................................................................... 861 19.6.3 Message Transmission Sequence.......................................................................... 863 19.6.4 Message Receive Sequence .................................................................................. 865 19.6.5 Reconfiguration of Mailbox.................................................................................. 867 19.7 Interrupt Sources................................................................................................................ 869 19.8 CAN Bus Interface............................................................................................................. 871 19.9 Usage Notes ....................................................................................................................... 872 19.9.1 Module Standby Mode.......................................................................................... 872 19.9.2 Reset ..................................................................................................................... 872 19.9.3 CAN Sleep Mode.................................................................................................. 872 19.9.4 Register Access..................................................................................................... 872 19.9.5 Interrupts............................................................................................................... 873
Section 20 IEBus Controller (IEB) [R5S72612] [R5S72613] ......................875
20.1 Features.............................................................................................................................. 875 20.1.1 IEBus Communications Protocol.......................................................................... 876 20.1.2 Communications Protocol..................................................................................... 880
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20.2 20.3
20.4
20.5
20.6
20.1.3 Transfer Data (Data Field Contents)..................................................................... 888 20.1.4 Bit Format............................................................................................................. 891 20.1.5 Configuration........................................................................................................ 892 Input/Output Pins............................................................................................................... 894 Register Descriptions......................................................................................................... 894 20.3.1 IEBus Control Register (IECTR).......................................................................... 896 20.3.2 IEBus Command Register (IECMR) .................................................................... 897 20.3.3 IEBus Master Control Register (IEMCR)............................................................. 899 20.3.4 IEBus Master Unit Address Register 1 (IEAR1) .................................................. 901 20.3.5 IEBus Master Unit Address Register 2 (IEAR2) .................................................. 902 20.3.6 IEBus Slave Address Setting Register 1 (IESA1)................................................. 903 20.3.7 IEBus Slave Address Setting Register 2 (IESA2)................................................. 903 20.3.8 IEBus Transmit Message Length Register (IETBFL) .......................................... 904 20.3.9 IEBus Reception Master Address Register 1 (IEMA1) ........................................ 905 20.3.10 IEBus Reception Master Address Register 2 (IEMA2) ........................................ 906 20.3.11 IEBus Receive Control Field Register (IERCTL) ................................................ 907 20.3.12 IEBus Receive Message Length Register (IERBFL)............................................ 908 20.3.13 IEBus Lock Address Register 1 (IELA1) ............................................................. 908 20.3.14 IEBus Lock Address Register 2 (IELA2) ............................................................. 909 20.3.15 IEBus General Flag Register (IEFLG) ................................................................. 910 20.3.16 IEBus Transmit Status Register (IETSR) ............................................................. 913 20.3.17 IEBus Transmit Interrupt Enable Register (IEIET) .............................................. 917 20.3.18 IEBus Receive Status Register (IERSR)............................................................... 919 20.3.19 IEBus Receive Interrupt Enable Register (IEIER)................................................ 923 20.3.20 IEBus Clock Selection Register (IECKSR) .......................................................... 924 20.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128)......................... 926 20.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128) .......................... 927 Data Format ....................................................................................................................... 928 20.4.1 Transmission Format ............................................................................................ 928 20.4.2 Reception Format.................................................................................................. 929 Software Control Flows ..................................................................................................... 930 20.5.1 Initial Setting ........................................................................................................ 930 20.5.2 Master Transmission............................................................................................. 931 20.5.3 Slave Reception .................................................................................................... 932 20.5.4 Master Reception .................................................................................................. 933 20.5.5 Slave Transmission............................................................................................... 934 Operation Timing............................................................................................................... 935 20.6.1 Master Transmit Operation................................................................................... 935 20.6.2 Slave Receive Operation....................................................................................... 936 20.6.3 Master Receive Operation .................................................................................... 937
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20.6.4 Slave Transmit Operation ..................................................................................... 938 20.7 Interrupt Sources................................................................................................................ 939 20.8 Usage Notes ....................................................................................................................... 941 20.8.1 Notes when the Communications have not been Completed within the Maximum Number of Transmit Bytes .................................................................. 941
Section 21 CD-ROM Decoder (ROM-DEC).....................................................943
21.1 Features.............................................................................................................................. 943 21.1.1 Formats Supported by ROM-DEC........................................................................ 944 21.2 Block Diagrams ................................................................................................................. 945 21.3 Register Descriptions ......................................................................................................... 949 21.3.1 ROM-DEC Enable Control Register (CROMEN) ................................................ 952 21.3.2 Sync Code-Based Synchronization Control Register (CROMSY0) ..................... 953 21.3.3 Decoding Mode Control Register (CROMCTL0) ................................................ 954 21.3.4 EDC/ECC Check Control Register (CROMCTL1) .............................................. 956 21.3.5 Automatic Decoding Stop Control Register (CROMCTL3)................................. 957 21.3.6 Decoding Option Setting Control Register (CROMCTL4) .................................. 958 21.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5) .............. 959 21.3.8 Sync Code Status Register (CROMST0) .............................................................. 960 21.3.9 Post-ECC Header Error Status Register (CROMST1).......................................... 961 21.3.10 Post-ECC Subheader Error Status Register (CROMST3) .................................... 962 21.3.11 Header/Subheader Validity Check Status Register (CROMST4)......................... 963 21.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5) ......................................................................................................... 964 21.3.13 ECC/EDC Error Status Register (CROMST6) ..................................................... 965 21.3.14 Buffer Status Register (CBUFST0) ...................................................................... 966 21.3.15 Decoding Stoppage Source Status Register (CBUFST1) ..................................... 967 21.3.16 Buffer Overflow Status Register (CBUFST2) ...................................................... 968 21.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00) ......................... 968 21.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01)......................... 969 21.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02)............................................................................................................. 969 21.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03)............................. 969 21.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00) .......................................................................................................... 970 21.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01) .......................................................................................................... 970 21.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02) .......................................................................................................... 971
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21.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03) .......................................................................................................... 971 21.3.25 Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04) .......................................................................................................... 972 21.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05) .......................................................................................................... 972 21.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06) .......................................................................................................... 973 21.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07) .......................................................................................................... 973 21.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20) ....................... 974 21.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21) ....................... 974 21.3.31 Post-ECC Correction Header: Frames (1/75 Seconds) Data Register (HEAD22) ............................................................................................................ 975 21.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23) ........................... 975 21.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20) .......................................................................................................... 976 21.3.34 Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21) .......................................................................................................... 976 21.3.35 Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22) .......................................................................................................... 977 21.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23) .......................................................................................................... 977 21.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24) .......................................................................................................... 978 21.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25) .......................................................................................................... 978 21.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26) .......................................................................................................... 979 21.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27) .......................................................................................................... 979 21.3.41 Automatic Buffering Setting Control Register (CBUFCTL0).............................. 980 21.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1)........................................................................................................ 981 21.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2)........................................................................................................ 982 21.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3)........................................................................................................ 982 21.3.45 ISY Interrupt Source Mask Control Register (CROMST0M) .............................. 983 21.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST)............................... 984
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21.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) ........................................ 985 21.3.48 SSI Data Control Register (SSI) ........................................................................... 985 21.3.49 Interrupt Flag Register (INTHOLD)..................................................................... 988 21.3.50 Interrupt Source Mask Control Register (INHINT).............................................. 989 21.3.51 Buffer Control Register (RINGBUFCTL) ............................................................ 990 21.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN0) ............................ 991 21.3.53 CD-ROM Decoder Stream Data Input Register (STRMDIN1) ............................ 991 21.3.54 CD-ROM Decoder Stream Data Input Register (STRMDIN2) ............................ 992 21.3.55 CD-ROM Decoder Stream Data Input Register (STRMDIN3) ............................ 992 21.3.56 CD-ROM Decoder Stream Data Output Register (STRMDOUT0)...................... 993 21.3.57 CD-ROM Decoder Stream Data Output Register (STRMDOUT1)...................... 993 21.4 Operation ........................................................................................................................... 994 21.4.1 Endian Conversion for Data in the Input Stream .................................................. 994 21.4.2 Sync Code Maintenance Function ........................................................................ 995 21.4.3 Error Correction.................................................................................................. 1000 21.4.4 Automatic Decoding Stop Function.................................................................... 1001 21.4.5 Buffering Format ................................................................................................ 1002 21.4.6 Target-Sector Buffering Function....................................................................... 1004 21.5 Interrupt Sources.............................................................................................................. 1006 21.5.1 Interrupt and DMA Transfer Request Signals .................................................... 1006 21.5.2 Timing of Status Registers Updates.................................................................... 1008 21.6 Usage Notes ..................................................................................................................... 1008 21.6.1 Stopping and Resuming Buffering Alone During Decoding .............................. 1008 21.6.2 When CROMST0 Status Register Bits are Set ................................................... 1008 21.6.3 Link Blocks......................................................................................................... 1008 21.6.4 Reading from the STRMDOUT0 and STRMDOUT1 Registers ........................ 1009 21.6.5 Stopping and Resuming CD-DSP Operation ...................................................... 1010
Section 22 A/D Converter (ADC)....................................................................1011
22.1 Features............................................................................................................................ 1011 22.2 Input/Output Pins ............................................................................................................. 1013 22.3 Register Configuration..................................................................................................... 1014 22.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................ 1014 22.3.2 A/D Control/Status Register (ADCSR) .............................................................. 1016 22.4 Operation ......................................................................................................................... 1020 22.4.1 Single Mode........................................................................................................ 1020 22.4.2 Multi Mode ......................................................................................................... 1023 22.4.3 Scan Mode .......................................................................................................... 1025 22.4.4 A/D Converter Activation by External Trigger, MTU2, or TMR....................... 1028 22.4.5 Input Sampling and A/D Conversion Time ........................................................ 1028
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22.4.6 External Trigger Input Timing............................................................................ 1030 22.5 Interrupt Sources and DMAC Transfer Request .............................................................. 1031 22.6 Definitions of A/D Conversion Accuracy........................................................................ 1031 22.7 Usage Notes ..................................................................................................................... 1033 22.7.1 Module Standby Mode Setting ........................................................................... 1033 22.7.2 Setting Analog Input Voltage ............................................................................. 1033 22.7.3 Notes on Board Design ....................................................................................... 1033 22.7.4 Processing of Analog Input Pins......................................................................... 1034 22.7.5 Permissible Signal Source Impedance ................................................................ 1035 22.7.6 Influences on Absolute Precision........................................................................ 1036 22.7.7 Usage Note when Shifting to Single Mode during A/D Conversion .................. 1036
Section 23 D/A Converter (DAC) ................................................................... 1037
23.1 Features............................................................................................................................ 1037 23.2 Input/Output Pins............................................................................................................. 1038 23.3 Register Descriptions....................................................................................................... 1038 23.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)........................................... 1039 23.3.2 D/A Control Register (DACR) ........................................................................... 1039 23.4 Operation ......................................................................................................................... 1041 23.5 Usage Notes ..................................................................................................................... 1042 23.5.1 Module Standby Mode Setting ........................................................................... 1042 23.5.2 D/A Output Hold Function in Software Standby Mode...................................... 1042 23.5.3 D/A Conversion and D/A Output in Deep Standby Mode.................................. 1042 23.5.4 Setting Analog Input Voltage ............................................................................. 1042
Section 24 I/O Ports......................................................................................... 1043
24.1 Port A............................................................................................................................... 1043 24.1.1 Register Configuration........................................................................................ 1044 24.1.2 Port A Data Registers H and L (PADRH and PADRL)...................................... 1044 24.1.3 Port A Port Registers H and L (PAPRH and PAPRL)........................................ 1046 24.2 Port B ............................................................................................................................... 1047 24.2.1 Register Configuration........................................................................................ 1048 24.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ...................................... 1048 24.2.3 Port B Port Registers H and L (PBPRH and PBPRL) ........................................ 1050 24.3 Port C ............................................................................................................................... 1051 24.3.1 Register Configuration........................................................................................ 1051 24.3.2 Port C Data Registers H and L (PCDRH and PCDRL) ...................................... 1052 24.3.3 Port C Port Registers H and L (PCPRH and PCPRL) ........................................ 1053 24.4 Port D............................................................................................................................... 1054 24.4.1 Register Configuration........................................................................................ 1054
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24.4.2 Port D Data Register (PDDR)............................................................................. 1055 24.4.3 Port D Port Registers H and L (PDPRH and PDPRL)........................................ 1056 24.5 Port E ............................................................................................................................... 1057 24.5.1 Register Configuration........................................................................................ 1057 24.5.2 Port E Port Register (PEPR) ............................................................................... 1057 24.6 Port F ............................................................................................................................... 1058 24.6.1 Register Configuration........................................................................................ 1058 24.6.2 Port F Data Register (PFDR) .............................................................................. 1059 24.6.3 Port F Port Register (PFPR)................................................................................ 1060
Section 25 Pin Function Controller (PFC).......................................................1061
25.1 Register Descriptions ....................................................................................................... 1069 25.1.1 Port A I/O Registers H and L (PAIORH and PAIORL) ..................................... 1071 25.1.2 Port A Control Registers 1 to 8 (PACR1 to PACR8) ......................................... 1072 25.1.3 Port B I/O Registers H and L (PBIORH and PBIORL)...................................... 1082 25.1.4 Port B Control Registers 1 to 8 (PBCR1 to PBCR8) .......................................... 1083 25.1.5 Port C I/O Registers H and L (PCIORH and PCIORL)...................................... 1096 25.1.6 Port C Control Registers 1 to 7 (PCCR1 to PCCR7) .......................................... 1097 25.1.7 Port D I/O Register (PDIOR).............................................................................. 1107 25.1.8 Port D Control Registers 1 to 5 (PDCR1 to PDCR5) ......................................... 1108 25.1.9 Port E Control Registers 1 and 2 (PECR1 and PECR2) ..................................... 1115 25.1.10 Port F I/O Register (PFIOR) ............................................................................... 1118 25.1.11 Port F Control Registers 1 and 2 (PFCR1 and PFCR2) ...................................... 1119 25.2 Usage Note....................................................................................................................... 1122
Section 26 On-Chip RAM ...............................................................................1123
26.1 Features............................................................................................................................ 1123 26.2 Usage Notes ..................................................................................................................... 1124 26.2.1 Page Conflict ...................................................................................................... 1124 26.2.2 RAME and RAMWE Bits .................................................................................. 1124
Section 27 Power-Down Modes ......................................................................1125
27.1 Features............................................................................................................................ 1125 27.1.1 Power-Down Modes ........................................................................................... 1125 27.2 Register Descriptions ....................................................................................................... 1127 27.2.1 Standby Control Register (STBCR).................................................................... 1128 27.2.2 Standby Control Register 2 (STBCR2)............................................................... 1129 27.2.3 Standby Control Register 3 (STBCR3)............................................................... 1131 27.2.4 Standby Control Register 4 (STBCR4)............................................................... 1132 27.2.5 Standby Control Register 5 (STBCR5)............................................................... 1134
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27.2.6 System Control Register 1 (SYSCR1) ................................................................ 1136 27.2.7 System Control Register 2 (SYSCR2) ................................................................ 1137 27.2.8 RAM Retaining Area Specifying Register (RAMKP)........................................ 1138 27.2.9 Deep Standby Oscillation Settling Clock Select Register (DSCNT) .................. 1139 27.2.10 Deep Standby Cancel Source Flag Register (DSFR).......................................... 1140 27.3 Operation ......................................................................................................................... 1142 27.3.1 Sleep Mode ......................................................................................................... 1142 27.3.2 Software Standby Mode...................................................................................... 1143 27.3.3 Software Standby Mode Application Example................................................... 1145 27.3.4 Deep Standby Mode ........................................................................................... 1146 27.3.5 Module Standby Function................................................................................... 1151 27.4 Usage Note....................................................................................................................... 1151 27.4.1 Note on Setting Registers ................................................................................... 1151 27.4.2 Note on Canceling Standby Mode when an External Clock is being Input ........ 1151
Section 28 User Debugging Interface (H-UDI)............................................... 1153
28.1 Features............................................................................................................................ 1153 28.2 Input/Output Pins............................................................................................................. 1154 28.3 Register Descriptions....................................................................................................... 1155 28.3.1 Bypass Register (SDBPR) .................................................................................. 1155 28.3.2 Instruction Register (SDIR) ................................................................................ 1156 28.4 Operation ......................................................................................................................... 1157 28.4.1 TAP Controller ................................................................................................... 1157 28.4.2 Reset Types......................................................................................................... 1158 28.4.3 UDTDO Output Timing...................................................................................... 1158 28.4.4 H-UDI Reset ....................................................................................................... 1159 28.4.5 H-UDI Interrupt .................................................................................................. 1159 28.5 Usage Notes ..................................................................................................................... 1160
Section 29 Advanced User Debugger II (AUD-II).......................................... 1161
29.1 Features............................................................................................................................ 1161 29.2 Input/Output Pins............................................................................................................. 1161 29.3 RAM Monitor Mode........................................................................................................ 1163 29.3.1 Communication Protocol .................................................................................... 1163 29.3.2 Operation ............................................................................................................ 1164 29.3.3 Usage Notes (RAM Monitor Mode) ................................................................... 1166
Section 30 List of Registers............................................................................. 1167
30.1 Register Addresses (Address Order)................................................................................ 1168 30.2 Register Bits..................................................................................................................... 1189
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30.3 Register States in Each Operating Mode ......................................................................... 1229
Section 31 Electrical Characteristics ...............................................................1249
31.1 Absolute Maximum Ratings ............................................................................................ 1249 31.2 DC Characteristics ........................................................................................................... 1250 31.3 AC Characteristics ........................................................................................................... 1258 31.3.1 Clock Timing ...................................................................................................... 1258 31.3.2 Control Signal Timing ........................................................................................ 1262 31.3.3 Bus Timing ......................................................................................................... 1264 31.3.4 DMAC Module Timing ...................................................................................... 1275 31.3.5 UBC Trigger Timing .......................................................................................... 1276 31.3.6 MTU2 Module Timing ....................................................................................... 1277 31.3.7 8-Bit Timer Timing............................................................................................. 1278 31.3.8 Watchdog Timer Timing..................................................................................... 1279 31.3.9 SCIF Module Timing.......................................................................................... 1280 31.3.10 IIC3 Module Timing........................................................................................... 1281 31.3.11 SSI Module Timing ............................................................................................ 1282 31.3.12 RCAN-ET Module Timing [R5S72611] [R5S72613] ........................................ 1284 31.3.13 A/D Trigger Input Timing .................................................................................. 1285 31.3.14 I/O Port Timing................................................................................................... 1285 31.3.15 H-UDI-Related Pin Timing................................................................................. 1286 31.3.16 AUD-II Timing ................................................................................................... 1288 31.3.17 AC Characteristics Measurement Conditions ..................................................... 1289 31.4 A/D Converter Characteristics ......................................................................................... 1290 31.5 D/A Converter Characteristics ......................................................................................... 1291 31.6 Usage Note....................................................................................................................... 1292
Appendix
A. B.
.......................................................................................................1293
Pin States.......................................................................................................................... 1293 Package Dimensions ........................................................................................................ 1298
Main Revisions and Additions in this Edition ...................................................1299 Index .......................................................................................................1305
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Section 1 Overview
Section 1 Overview
1.1 SH7261 Group Features
This LSI is a single-chip RISC (Reduced Instruction Set Computer) microprocessor that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU incorporated in this LSI is the SH-2A CPU, which features upward compatibility on the object code level with the SH-1, SH-2, and SH-2E microcomputers. The CPU has a RISC-type instruction set and employs a superscalar architecture and the Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture independent of the bus for the direct memory access controller (DMAC) enhances data processing power. This CPU realizes low-cost, high-performance, and high-functioning systems for applications such as high-speed realtime control, which has been next to impossible with the conventional microcomputers. This LSI has a floating-point unit and a cache. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as, 32-Kbyte RAM for high-speed operation, a controller area network (RCAN-ET)*1, IEBusTM*2 controller (IEB)*3, CD-ROM decoder (ROM-DEC), a serial sound interface (SSI), a serial communication interface with FIFO (SCIF), I2C bus interface 3 (IIC3), a multi-function timer pulse unit 2 (MTU2), an 8-bit timer (TMR), a realtime clock (RTC), an A/D converter, a D/A converter, an interrupt controller (INTC), I/O ports, and advanced user debugger II (AUD-II). This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. The features of this LSI are listed in table 1.1. Notes: 1. R5S72611 and R5S72613 support this function. 2. The IEBusTM (Inter Equipment BusTM) is a trademark of NEC Electronics Corporation. 3. R5S72612 and R5S72613 support this function.
Rev. 2.00 Sep. 07, 2007 Page 1 of 1312 REJ09B0320-0200
Section 1 Overview
Table 1.1
Item CPU
SH7261 Group Features
Features * * * * Renesas Technology original SuperH architecture Compatible with SH-1 and SH-2 at object code level 32-bit internal data bus Support of an abundant register-set Sixteen 32-bit general registers Four 32-bit control registers Four 32-bit system registers Register bank for high-speed response to interrupts * RISC-type instruction set (upward compatible with SH series) Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability Load/store architecture Delayed branch instructions Instruction set based on C language * * * * * * Superscalar architecture to execute two instructions at one time including FPU Instruction execution time: Up to two instructions/cycle Address space: 4 Gbytes Internal multiplier Five-stage pipeline Harvard architecture
Rev. 2.00 Sep. 07, 2007 Page 2 of 1312 REJ09B0320-0200
Section 1 Overview
Item Floating-point Unit (FPU)
Features * * * * * * Floating-point co-processor included Supports single-precision (32-bit) and double-precision (64-bit) Supports data type and exceptions that conforms to IEEE754 standard Two rounding modes: Round to nearest and round to zero Denormalization modes: Flush to zero Floating-point registers Sixteen 32-bit floating-point registers (single-precision x 16 words or double-precision x 8 words) Two 32-bit floating-point system registers * * * * Supports FMAC (multiplication and accumulation) instructions Supports FDIV (division) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution time Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-precision), eight cycles (double-precision) Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six cycles (double-precision) Note: FMAC only supports single-precision * 5-stage pipeline Instruction cache: 8 Kbytes Operand cache: 8 Kbytes 128-entry, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache Write-back, write-through and LRU replacement algorithm Cache locking function available (only for operand cache); ways 2 and 3 can be locked
Cache
* * * * *
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Section 1 Overview
Item Interrupt controller (INTC)
Features * * * * Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to PINT0) On-chip peripheral interrupts: Priority level set for each module 16 priority levels available Register bank enabling fast register saving and restoring in interrupt handling CSC Seven-channel chip select controller (CSC) External devices with their bus sizes of 32, 16, or 8 bits can be connected Cycle wait function Up to 31 cycles (up to 7 cycles for page access cycle) The following features settable for wait controlling Timings of asserting and negating chip select signals Timings of asserting and negating read/write signals Timings of starting and stopping data output One-write strobe and byte write strobe modes are available as write access modes Page read and page write modes are available as page access modes * SDRAMC Two-channel external SDRAM interfaces Auto refresh using the internal programmable refresh counter or self refresh mode selectable The following features settable Row-column latency, column latency, row-active period, writerecovery period, row precharge period, auto refresh request interval, initial precharge cycle count, and initial auto refresh request interval Random column burst access available (one SDRAM burst length) Initialization sequencer issues precharge and auto refresh commands
Bus state controller (BSC)
*
Bus monitor
*
Bus monitor function When an illegal address access or a bus timeout is detected, a bus error interrupt is generated.
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Section 1 Overview
Item
Features Eight channels; external request available for four of them Can be activated by software, on-chip modules, or external devices Software; 1, internal source; 33, external source;4 * * Up to 64 Mbytes can be transferred Maximum transfer data size 8, 16, or 32 bits for single-data transfer 1, 2, 4, 8, 16, 32, 64, or 128 sets of data for single operand transfer (a transfer continues until the byte count reaches 0) * Transfer method Cycle-stealing transfer (dual address transfer) Three clock cycles per one set of data (best) Bus released between read and write cycles Pipeline transfer (dual address transfer) One clock cycle per one set of data (best) * * * Addressing method Increment, decrement, or fixed Three clock cycles per one set of data (best) Transfer modes Single operand transfer, continuous operand transfer, and non-stop transfer * * * * An interrupt is requested when the byte count reaches 0 Reloading function Source address, destination address, and byte count DMAC suspend, resume, and stop function DMAC forcible terminate function Clock mode: Input clock can be selected from external input (EXTAL or CKIO) or crystal resonator Input clock can be multiplied by 16 (max.) by the internal PLL circuit Three types of clocks generated CPU clock: Maximum 120 MHz Bus clock: Maximum 60 MHz Peripheral clock: Maximum 40 MHz
Direct memory access * controller (DMAC) *
Clock pulse generator (CPG)
* * *
Watchdog timer (WDT)
* *
On-chip one-channel watchdog timer A counter overflow can reset this LSI
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Section 1 Overview
Item Power-down modes
Features * Four power-down modes provided to reduce the current consumption in this LSI Sleep mode Software standby mode Deep standby mode Module standby mode
Multi-function timer pulse unit 2 (MTU2)
* * * *
Maximum 16 lines of pulse inputs/outputs and 3 lines of pulse inputs based on six channels of 16-bit timers 21 output compare and input capture registers Input capture function Pulse output modes One shot, toggle, PWM, complementary PWM, and resetsynchronized PWM modes
* *
Synchronization of multiple counters Complementary PWM output mode Non-overlapping waveforms output for 3-phase inverter control Automatic dead time setting 0% to 100% PWM duty cycle specifiable A/D converter start request delaying function Interrupt skipping at crest or trough
*
Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty value
* 8-bit timer (TMR) * * * * Realtime clock (RTC) * *
Phase counting mode Two-phase encoder pulse counting available Two-channel 8-bit timer Six internal clocks (P/2, P/8, P/32, P/64, P/1024, or P/8192) or external clock specifiable Timer outputs controllable using two compare match signals Two channels can be cascade-connected Internal clock, calendar function, alarm function Interrupts can be generated at intervals of 1/256 s by the 32.768-kHz on-chip crystal oscillator
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Section 1 Overview
Item Serial communication interface with FIFO (SCIF)
Features * * * * * Eight channels Clock synchronous or asynchronous mode selectable Simultaneous transmission and reception (full-duplex communication) supported Dedicated baud rate generator Separate 16-byte FIFO registers for transmission and reception Three channels Master mode and slave mode supported Two-channel bidirectional serial transfer Support of various serial audio formats Support of master and slave functions Generation of programmable word clock and bit clock Multichannel formats Support of 8, 16, 18, 20, 22, 24 and 32-bit data formats Two channels Supports CAN specification 2.0B Data and remote frame in standard format (11-bit ID) Data and remote frame in extended format (18-bit ID) * * * * 16 independent message buffers using IDs in standard (11-bit) or extended (18-bit) format 15 Mailboxes for transmission or reception One receive-only Mailbox Message reception filtering by IDs: Standard message ID Extended message ID * * * * Local reception filter for all Mailboxes (standard and extended IDs) can be specified Power consumption can be reduced in sleep mode CAN data transfer rate of up to 1 Mbit/s available Transmit message queue having an internal priority sorting mechanism which handles priority-inversion issue of realtime applications Data buffer access without hand-shaking
I2C bus interface 3 (IIC3)
* *
Serial sound interface * (SSI) * * * * * Controller area network (RCAN-ET) [R5S72611] [R5S72613] * *
*
Rev. 2.00 Sep. 07, 2007 Page 7 of 1312 REJ09B0320-0200
Section 1 Overview
Item IEBus Controller (IEB) [R5S72612] [R5S72613]
TM
Features * IEBus protocol control (layer 2) supported Half-duplex asynchronous communications Multi-master system Broadcast communications function Selectable mode (three types) with different transfer speeds * On-chip buffers for data transmission and reception that enables up to 128 bytes of consecutive transmit/reception (maximum number of transfer bytes in mode 2) Operating frequency 6 MHz, 6.29 MHz (IEB uses clocks of P or AUDIO_X1/AUDIO_X2.) 12 MHz, 12.58 MHz (IEB uses 1/2 divided clocks of P or AUDIO_X1/AUDIO_X2.) 18 MHz, 18.87 MHz (IEB uses 1/3 divided clocks of P or AUDIO_X1/AUDIO_X2.) 24 MHz, 25.16 MHz (IEB uses 1/4 divided clocks of P or AUDIO_X1/AUDIO_X2.) 30 MHz, 31.45 MHz (IEB uses 1/5 divided clocks of P or AUDIO_X1/AUDIO_X2.) 36 MHz, 37.74 MHz (IEB uses 1/6 divided clocks of P or AUDIO_X1/AUDIO_X2.)
*
Rev. 2.00 Sep. 07, 2007 Page 8 of 1312 REJ09B0320-0200
Section 1 Overview
Item CD-ROM decoder (ROM-DEC)
Features * * Support of five formats: mode 0, mode 1, mode 2, mode 2 form 1, and mode 2 form 2 Sync codes detection and protection Protection: When a sync code is not detected, it is automatically inserted * * Descrambling ECC P, Q, PQ, and QP correction PQ or QP correction can be repeated up to three times * * * * EDC Performed before and after ECC Mode and form are automatically detected Link sectors are automatically detected Buffering data control Buffering CD-ROM data including SYNC code in specified format, after the data is descrambled, corrected by ECC and checked by EDC.
I/O ports A/D converter (ADC)
* * * * *
109 I/Os and 14 inputs Input or output can be selected for each bit 10-bit resolution Eight input channels A/D conversion request by the external trigger or timer trigger 8-bit resolution Two output channels Two break channels Addresses, data values, type of access, and data size can all be set as break conditions E10A emulator support JTAG-standard pin assignment Eight I/O pins Functions to read/write modules connected to internal/external buses (except cache and H-UDI) in RAM monitor mode 32-Kbyte memory PVcc, VccR, and PLLVcc: 3.0 to 3.6 V LQFP2424-176Cu (0.5 pitch)
D/A converter (DAC) User break controller (UBC) User debugging interface (H-UDI) Advanced user debugger II (AUD-II) On-chip RAM Power supply voltage Packages
* * * * * * * * * * *
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Section 1 Overview
1.2
Table 1.2
Product Lineup
Product Lineup
RCAN-ET IEB Operating Temperature
Abbreviation Product Code R5S72611
R5S72611RB120FP Supported R5S72611RP100FP R5S72611RP80FP
Not supported -20 to +70C (Regular specifications) -40 to +85C (Wide-range specifications) -40 to +85C (Wide-range specifications) -20 to +70C (Regular specifications) -40 to +85C (Wide-range specifications) -40 to +85C (Wide-range specifications) Supported -20 to +70C (Regular specifications) -40 to +85C (Wide-range specifications) -40 to +85C (Wide-range specifications)
R5S72612
R5S72612RB120FP Not supported Supported R5S72612RP100FP R5S72612RP80FP
R5S72613
R5S72613RB120FP Supported R5S72613RP100FP R5S72613RP80FP
Rev. 2.00 Sep. 07, 2007 Page 10 of 1312 REJ09B0320-0200
Section 1 Overview
1.3
Block Diagram
The block diagram of this LSI is shown in figure 1.1.
SH-2A CPU core
Floating-point unit (FPU) CPU instruction fetch bus (F bus) CPU memory access bus (M bus) CPU bus (C bus)
Port
Cache controller
Internal bus (I bus) Bus bridge Internal CPU bus Internal DMA write bus Internal DMA read bus External bus I/O External bus width mode input
Port
Bus state controller (BSC)
On-chip peripheral module bus 1 controller
On-chip peripheral module bus 2 controller
On-chip peripheral module bus 1
Port
Bus monitor
Direct memory access controller (DMAC)
DREQ input On-chip DACK output peripheral module bus 3 DACT output controller DTEND output
On-chip peripheral module bus 3 On-chip peripheral module bus 2
Pin function controller (PFC)
I/O port
Clock pulse generator (CPG)
Watchdog timer (WDT)
Interrupt controller (INTC)
Multi-function timer pulse unit 2 (MTU2) Port Timer pulse I/O
Port
Instruction cache Operand cache memory (8 kbytes) memory (8 kbytes)
On-chip RAM (32 kbytes)
User break controller (UBC)
UBCTRG output
Advanced user debugger-II (AUD-II)
AUDRST input AUDSYNC input AUDCK input AUDMD input AUDATA I/O
CD-ROM decoder (ROM-DEC)
8-bit timer (TMR)
Realtime clock (RTC)
Port General I/O
Port
Port
Port RES input MRES input NMI input IRQ input PINT input
Port
Port RTC_X1 input RTC_X2 output
WDTOVF output EXTAL input XTAL output CKIO I/O Clock mode input
Compare match output External counter clock input External counter reset input
*2
User debugging interface (H-UDI) Power-down mode control D/A converter (DAC) A/D converter (ADC) IEBusTM controller (IEB)
*1
Controller area network (RCAN-ET) Serial sound interface (SSI) I2C bus interface 3 (IIC3) Serial communication interface with FIFO (SCIF) Port Serial I/O
Port JTAG I/O
Port Analog output
Port Analog input ADTRG input
Port IEB bus I/O
Port
Port
Port I2C bus I/O
Notes: 1. R5S72611 and R5S72613 support this unit. 2. R5S72612 and R5S72613 support this unit.
CAN bus I/O Serial I/O Audio clock input
Figure 1.1 Block Diagram
Rev. 2.00 Sep. 07, 2007 Page 11 of 1312 REJ09B0320-0200
Section 1 Overview
1.4
Pin Assignments
ASEBRK/ASEBRKAK UDTCK UDTDI UDTDO UDTMS PVCC UDTRST PVSS AUDIO_X1 AUDIO_X2 PVSS PD0/AUDIO_CLK PD1/SSIDATA0 PD2/SSISCK0 PD3/SSIWS0 PD4/TxD4/SSIDATA1 PD5/RxD4/SSISCK1 PD6/SCK4/SSIWS1 PD7/TIOC0A/TxD0/DACT1 PD8/TIOC0B/RxD0/DTEND1 PD9/TIOC0C/SCK0 PD10/TMO1/TIOC0D/TxD1 PD11/TMRI1/RxD1 PD12/TMCI1/SCK1 PD13/DREQ1 PD14/DACK1 PD15/SDA2 PD16/SCL2 PF7/AUDATA3 PVSS PF6/AUDATA2 PVCC PF5/AUDATA1 PF4/AUDATA0 PF3/AUDSYNC PF2/TCLKD/SCK7/AUDCK PF1/RxD7/AUDMD PF0/TxD7/AUDRST AVSS PE7/IRQ7/AN7/DA1 PE6/IRQ6/AN6/DA0 PE5/IRQ5/AN5 PE4/IRQ4/AN4 PE3/PINT7/AN3
ASEMD MD1 MD0 WDTOVF PVSS PB0/D0 PVCC PB1/D1 PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 PB8/D8 PB9/D9 PB10/D10 PB11/D11 PB12/D12 PB13/D13 PB14/D14 PB15/D15 PVSS PB16/D16/IRQ0/TIOC3A PVCC PB17/D17/IRQ1/TIOC3B PB18/D18/IRQ2/TIOC3C PB19/D19/IRQ3/TIOC3D PB20/D20/IRQ4/TIOC4A/TxD2 PB21/D21/IRQ5/TIOC4B/RxD2 PB22/D22/IRQ6/TIOC4C/SCK2 PB23/D23/IRQ7/TIOC4D PB24/D24/PINT0/TIC5U/TxD6 PB25/D25/PINT1/TIC5V/RxD6 PVCC PB26/D26/PINT2/TIC5W/SCK6 PVSS PB27/D27/PINT3 PB28/D28/PINT4/TMO0/TxD3 PB29/D29/PINT5/TMRI0/RxD3 PB30/D30/PINT6/TMCI0/SCK3 PB31/D31/PINT7 VCCR MRES
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
LQFP2424-176Cu (FP-176EV) Top view
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
PE2/PINT6/AN2 PE1/PINT5/AN1 PE0/PINT4/AN0 AVREF AVCC PC0/CS0 PC1/CS1 PC2/CS2/SDCS1/ADTRG PC3/CS3/UBCTRG PC4/CS4/TIOC1A/TxD5 PC5/CS5/TIOC1B/RxD5 PC6/CS6/TCLKA/SCK5 PVCC PC7/SDCS0 PVSS PC8/RD PC9/WR0 PC10/WR1 PC11/WR2/TIOC2A/DACT2 PC12/WR3/TIOC2B/DTEND2 PC13/WAIT PC14/SDCKE PC15/SDRAS PC16/SDCAS PC17/SDWE PC18/BC0/DQM0 PC19/BC1/DQM1 PC20/BC2/DQM2/TCLKB PC21/BC3/DQM3/TCLKC/DACK2 PC22/IRQ0/SCL0/DREQ2 PC23/IRQ1/SDA0 PC24/IRQ2/SCL1 PC25/IRQ3/SDA1 PVSS PA31/CRx1/DTEND0 PVCC PA30/CTx1/DACT0 PA29/CRx0/DACK0 PA28/CTx0/DREQ0 PA27/A27/PINT3/DTEND3 PA26/A26/PINT2/DACT3 PA25/A25/PINT1/DACK3 PA24/A24/PINT0/DREQ3 VSS
Rev. 2.00 Sep. 07, 2007 Page 12 of 1312 REJ09B0320-0200
VSSR RES PLLVCC NMI PLLVSS RTC_X1 RTC_X2 PVSS XTAL EXTAL PVSS CKIO/SDCLK PVCC MD_CLK0 MD_CLK1 PVSS PA0/A0 PVCC PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PA8/A8 PA9/A9 PA10/A10 PA11/A11 PA12/A12 PA13/A13 PA14/A14 PA15/A15 PA16/A16 PA17/A17 PA18/A18 PA19/A19 PVSS PA20/A20 PVCC PA21/A21 PA22/A22 PA23/A23 VCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 1.2 Pin Assignments of R5S72611
Section 1 Overview
ASEMD MD1 MD0 WDTOVF PVSS PB0/D0 PVCC PB1/D1 PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 PB8/D8 PB9/D9 PB10/D10 PB11/D11 PB12/D12 PB13/D13 PB14/D14 PB15/D15 PVSS PB16/D16/IRQ0/TIOC3A PVCC PB17/D17/IRQ1/TIOC3B PB18/D18/IRQ2/TIOC3C PB19/D19/IRQ3/TIOC3D PB20/D20/IRQ4/TIOC4A/TxD2 PB21/D21/IRQ5/TIOC4B/RxD2 PB22/D22/IRQ6/TIOC4C/SCK2 PB23/D23/IRQ7/TIOC4D PB24/D24/PINT0/TIC5U/TxD6 PB25/D25/PINT1/TIC5V/RxD6 PVCC PB26/D26/PINT2/TIC5W/SCK6 PVSS PB27/D27/PINT3 PB28/D28/PINT4/TMO0/TxD3 PB29/D29/PINT5/TMRI0/RxD3 PB30/D30/PINT6/TMCI0/SCK3 PB31/D31/PINT7 VCCR MRES
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
ASEBRK/ASEBRKAK UDTCK UDTDI UDTDO UDTMS PVCC UDTRST PVSS AUDIO_X1 AUDIO_X2 PVSS PD0/AUDIO_CLK PD1/SSIDATA0 PD2/SSISCK0 PD3/SSIWS0 PD4/TxD4/SSIDATA1 PD5/RxD4/SSISCK1 PD6/SCK4/SSIWS1 PD7/TIOC0A/TxD0/DACT1 PD8/TIOC0B/RxD0/DTEND1 PD9/TIOC0C/SCK0 PD10/TMO1/TIOC0D/TxD1 PD11/TMRI1/RxD1 PD12/TMCI1/SCK1 PD13/IETxD/DREQ1 PD14/IERxD/DACK1 PD15/SDA2 PD16/SCL2 PF7/AUDATA3 PVSS PF6/AUDATA2 PVCC PF5/AUDATA1 PF4/AUDATA0 PF3/AUDSYNC PF2/TCLKD/SCK7/AUDCK PF1/RxD7/AUDMD PF0/TxD7/AUDRST AVSS PE7/IRQ7/AN7/DA1 PE6/IRQ6/AN6/DA0 PE5/IRQ5/AN5 PE4/IRQ4/AN4 PE3/PINT7/AN3
LQFP2424-176Cu (FP-176EV) Top view
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
PE2/PINT6/AN2 PE1/PINT5/AN1 PE0/PINT4/AN0 AVREF AVCC PC0/CS0 PC1/CS1 PC2/CS2/SDCS1/ADTRG PC3/CS3/UBCTRG PC4/CS4/TIOC1A/TxD5 PC5/CS5/TIOC1B/RxD5 PC6/CS6/TCLKA/SCK5 PVCC PC7/SDCS0 PVSS PC8/RD PC9/WR0 PC10/WR1 PC11/WR2/TIOC2A/DACT2 PC12/WR3/TIOC2B/DTEND2 PC13/WAIT PC14/SDCKE PC15/SDRAS PC16/SDCAS PC17/SDWE PC18/BC0/DQM0 PC19/BC1/DQM1 PC20/BC2/DQM2/TCLKB PC21/BC3/DQM3/TCLKC/DACK2 PC22/IRQ0/SCL0/DREQ2 PC23/IRQ1/SDA0 PC24/IRQ2/SCL1 PC25/IRQ3/SDA1 PVSS PA31/DTEND0 PVCC PA30/DACT0 PA29/DACK0 PA28/DREQ0 PA27/A27/PINT3/DTEND3 PA26/A26/PINT2/DACT3 PA25/A25/PINT1/DACK3 PA24/A24/PINT0/DREQ3 VSS
VSSR RES PLLVCC NMI PLLVSS RTC_X1 RTC_X2 PVSS XTAL EXTAL PVSS CKIO/SDCLK PVCC MD_CLK0 MD_CLK1 PVSS PA0/A0 PVCC PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PA8/A8 PA9/A9 PA10/A10 PA11/A11 PA12/A12 PA13/A13 PA14/A14 PA15/A15 PA16/A16 PA17/A17 PA18/A18 PA19/A19 PVSS PA20/A20 PVCC PA21/A21 PA22/A22 PA23/A23 VCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 1.3 Pin Assignments of R5S72612
Rev. 2.00 Sep. 07, 2007 Page 13 of 1312 REJ09B0320-0200
Section 1 Overview
ASEMD MD1 MD0 WDTOVF PVSS PB0/D0 PVCC PB1/D1 PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 PB8/D8 PB9/D9 PB10/D10 PB11/D11 PB12/D12 PB13/D13 PB14/D14 PB15/D15 PVSS PB16/D16/IRQ0/TIOC3A PVCC PB17/D17/IRQ1/TIOC3B PB18/D18/IRQ2/TIOC3C PB19/D19/IRQ3/TIOC3D PB20/D20/IRQ4/TIOC4A/TxD2 PB21/D21/IRQ5/TIOC4B/RxD2 PB22/D22/IRQ6/TIOC4C/SCK2 PB23/D23/IRQ7/TIOC4D PB24/D24/PINT0/TIC5U/TxD6 PB25/D25/PINT1/TIC5V/RxD6 PVCC PB26/D26/PINT2/TIC5W/SCK6 PVSS PB27/D27/PINT3 PB28/D28/PINT4/TMO0/TxD3 PB29/D29/PINT5/TMRI0/RxD3 PB30/D30/PINT6/TMCI0/SCK3 PB31/D31/PINT7 VCCR MRES
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
ASEBRK/ASEBRKAK UDTCK UDTDI UDTDO UDTMS PVCC UDTRST PVSS AUDIO_X1 AUDIO_X2 PVSS PD0/AUDIO_CLK PD1/SSIDATA0 PD2/SSISCK0 PD3/SSIWS0 PD4/TxD4/SSIDATA1 PD5/RxD4/SSISCK1 PD6/SCK4/SSIWS1 PD7/TIOC0A/TxD0/DACT1 PD8/TIOC0B/RxD0/DTEND1 PD9/TIOC0C/SCK0 PD10/TMO1/TIOC0D/TxD1 PD11/TMRI1/RxD1 PD12/TMCI1/SCK1 PD13/IETxD/DREQ1 PD14/IERxD/DACK1 PD15/SDA2 PD16/SCL2 PF7/AUDATA3 PVSS PF6/AUDATA2 PVCC PF5/AUDATA1 PF4/AUDATA0 PF3/AUDSYNC PF2/TCLKD/SCK7/AUDCK PF1/RxD7/AUDMD PF0/TxD7/AUDRST AVSS PE7/IRQ7/AN7/DA1 PE6/IRQ6/AN6/DA0 PE5/IRQ5/AN5 PE4/IRQ4/AN4 PE3/PINT7/AN3
LQFP2424-176Cu (FP-176EV) Top view
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
PE2/PINT6/AN2 PE1/PINT5/AN1 PE0/PINT4/AN0 AVREF AVCC PC0/CS0 PC1/CS1 PC2/CS2/SDCS1/ADTRG PC3/CS3/UBCTRG PC4/CS4/TIOC1A/TxD5 PC5/CS5/TIOC1B/RxD5 PC6/CS6/TCLKA/SCK5 PVCC PC7/SDCS0 PVSS PC8/RD PC9/WR0 PC10/WR1 PC11/WR2/TIOC2A/DACT2 PC12/WR3/TIOC2B/DTEND2 PC13/WAIT PC14/SDCKE PC15/SDRAS PC16/SDCAS PC17/SDWE PC18/BC0/DQM0 PC19/BC1/DQM1 PC20/BC2/DQM2/TCLKB PC21/BC3/DQM3/TCLKC/DACK2 PC22/IRQ0/SCL0/DREQ2 PC23/IRQ1/SDA0 PC24/IRQ2/SCL1 PC25/IRQ3/SDA1 PVSS PA31/CRx1/DTEND0 PVCC PA30/CTx1/DACT0 PA29/CRx0/DACK0 PA28/CTx0/DREQ0 PA27/A27/PINT3/DTEND3 PA26/A26/PINT2/DACT3 PA25/A25/PINT1/DACK3 PA24/A24/PINT0/DREQ3 VSS
Rev. 2.00 Sep. 07, 2007 Page 14 of 1312 REJ09B0320-0200
VSSR RES PLLVCC NMI PLLVSS RTC_X1 RTC_X2 PVSS XTAL EXTAL PVSS CKIO/SDCLK PVCC MD_CLK0 MD_CLK1 PVSS PA0/A0 PVCC PA1/A1 PA2/A2 PA3/A3 PA4/A4 PA5/A5 PA6/A6 PA7/A7 PA8/A8 PA9/A9 PA10/A10 PA11/A11 PA12/A12 PA13/A13 PA14/A14 PA15/A15 PA16/A16 PA17/A17 PA18/A18 PA19/A19 PVSS PA20/A20 PVCC PA21/A21 PA22/A22 PA23/A23 VCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 1.4 Pin Assignments of R5S72613
Section 1 Overview
1.5
Pin Functions
Table 1.3 lists the pin functions. Table 1.3 Pin Functions
Symbol VCCR I/O I Name Function
Classification Power supply
Power supply for Power supply pin for the internal internal stepstep-down circuit. This pin must be down circuit connected to the system power supply. This LSI does not operate correctly if this pin is left open. Ground for internal stepdown circuit Ground pin for the internal stepdown circuit. This pin must be connected to the system power supply (0 V). This LSI does not operate correctly if this pin is left open. Pin for connecting an external capacitor for the internal step-down circuit. This pin should be connected to the VSS via the external capacitor (place closer to this pin). Ground pin for the internal stepdown circuit used for stabilize internal step-down power supply. This pin should be connected to the VCL via the external capacitor (place closer to this pin)
VSSR
I
VCL
I
Capacitor connected pin for internal stepdown circuit Ground for internal stepdown circuit
VSS
I
PVCC
I
Power supply for Power supply pins for I/O pins. All I/O circuits the PVCC pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground for I/O circuits Ground pins for I/O pins. All the PVSS pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open.
PVSS
I
Rev. 2.00 Sep. 07, 2007 Page 15 of 1312 REJ09B0320-0200
Section 1 Overview
Classification Power supply
Symbol PLLVCC
I/O I
Name
Function
Power supply for Power supply for the on-chip PLL PLL oscillator. This LSI does not operate correctly if this pin is left open. Ground for PLL Ground pin for the on-chip PLL oscillator. This LSI does not operate correctly if this pin is left open.
PLLVSS
I
Clock
EXTAL XTAL CKIO
I O I/O
Crystal resonator/ Pin connected to a crystal resonator. external clock An external clock signal may also be input to the EXTAL pin. System clock I/O Input pin for an external clock or output pin for supplying the system clock to external devices Mode set Pins to set the operating mode. Do not change signal levels on these pins during operation. Pins to set the clock operating mode. Do not change signal levels on these pins during operation.
Operating mode control
MD1, MD0
I
MD_CLK1, MD_CLK0 ASEMD
I
Clock mode set
I
Debugging mode This pin is valid when the E10A-USB emulator is in use. Otherwise, fix the signal level on this pin high. Power-on reset Manual reset Watchdog timer overflow Break mode acknowledge Break request This LSI enters the power-on reset state when this signal goes low. This LSI enters the manual reset state when this signal goes low. An overflow signal from the WDT is output on this pin. Indicates that the E10A-USB emulator has entered its break mode. E10A-USB emulator break input pin
System control
RES MRES WDTOVF ASEBRKAK
I I O O
ASEBRK*
I
Rev. 2.00 Sep. 07, 2007 Page 16 of 1312 REJ09B0320-0200
Section 1 Overview
Classification Interrupts
Symbol NMI IRQ7 to IRQ0
I/O I I
Name Non-maskable interrupt
Function Non-maskable interrupt request pin. Fix it high when not in use.
Interrupt requests Maskable interrupt request pins. 7 to 0 Level-input or edge-input detection can be selected. When the edgeinput detection is selected, the rising edge, falling edge, or both edges can also be selected. Interrupt requests Maskable interrupt request pins. 7 to 0 Only level-input detection can be selected. Address bus Data bus Addresses are output on these pins. Bidirectional data bus
PINT7 to PINT0 I
Address bus Data bus Bus control
A27 to A0 D31 to D0 CS6 to CS0 RD WAIT
O I/O O O I
Chip select 6 to 0 Chip-select signals for external memory or devices Read Wait Indicates that data is read from an external device. Input pin for inserting a wait cycle into the bus cycles during access to the external space Indicates a write access to bits 7 to 0 of data of external memory or device. (For an access in units of 8, 16, or 32 bits) Indicates a write access to bits 15 to 8 of data of external memory or device. (For an access in units of 16 or 32 bits) Indicates a write access to bits 23 to 16 of data of external memory or device. (For an access in units of 32 bits) Indicates a write access to bits 31 to 24 of data of external memory or device. (For an access in units of 32 bits)
WR0
O
Byte select
WR1
O
Byte select
WR2
O
Byte select
WR3
O
Byte select
Rev. 2.00 Sep. 07, 2007 Page 17 of 1312 REJ09B0320-0200
Section 1 Overview
Classification Bus control
Symbol BC0
I/O O
Name Byte select
Function Selects bits 7 to 0 of data of external memory or device. (For an access in units of 8, 16, or 32 bits) Selects bits 15 to 8 of data of external memory or device. (For an access in units of 16 or 32 bits) Selects bits 23 to 16 of data of external memory or device. (For an access in units of 32 bits) Selects bits 31 to 24 of data of external memory or device. (For an access in units of 32 bits) Selects bits D7 to D0 when SDRAM is connected. (For an access in units of 8, 16, or 32 bits) Selects bits D15 to D8 when SDRAM is connected. (For an access in units of 16 or 32 bits) Selects bits D23 to D16 when SDRAM is connected. (For an access in units of 32 bits) Selects bits D31 to D24 when SDRAM is connected. (For an access in units of 32 bits) Pins connected to the CS pins of SDRAM Pin connected to the RAS pin of SDRAM Pin connected to the CAS pin of SDRAM Pin connected to the WE pin of SDRAM Pin connected to the CKE pin of SDRAM Pin connected to the CLK pin of SDRAM
BC1
O
Byte select
BC2
O
Byte select
BC3
O
Byte select
DQM0
O
Byte select
DQM1
O
Byte select
DQM2
O
Byte select
DQM3
O
Byte select
SDCS1, SDCS0 SDRAS SDCAS SDWE SDCKE SDCLK
O O O O O O
Chip select RAS CAS WE CK enable Clock output
Rev. 2.00 Sep. 07, 2007 Page 18 of 1312 REJ09B0320-0200
Section 1 Overview
Classification
Symbol
I/O I O
Name DMA-transfer request DMA-transfer request acknowledge DMA-transfer request active
Function Input pins to receive external requests for DMA transfer Output pins for signals indicating acknowledge of external requests from external devices Output pins for signals indicating DMA active in response to external requests from external devices
Direct memory DREQ3 to access controller DREQ0 (DMAC) DACK3 to DACK0 DACT3 to DACT0 DTEND3 to DTEND0 Multi-function TCLKA, timer pulse unit 2 TCLKB, (MTU2) TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B
O
O I
DMA-transfer end Output pins for DMA transfer end output MTU2 timer clock External clock input pins for the timer input
I/O
MTU2 input capture/output compare (channel 0) MTU2 input capture/output compare (channel 1) MTU2 input capture/output compare (channel 2) MTU2 input capture/output compare (channel 3) MTU2 input capture/output compare (channel 4) MTU2 input capture (channel 5)
The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. The TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. The TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. The TGRA_4 and TGRB_4 input capture input/output compare output/PWM output pins. The TGRU_5, TGRV_5, and TGRW_5 input capture input/dead time compensation input pins.
I/O
TIOC2A, TIOC2B
I/O
TIOC3A, TIOC3B, TIOC3C, TIOC3D TIOC4A, TIOC4B, TIOC4C, TIOC4D TIOC5U, TIOC5V, TIOC5W
I/O
I/O
I
Rev. 2.00 Sep. 07, 2007 Page 19 of 1312 REJ09B0320-0200
Section 1 Overview
Classification
Symbol
I/O O
Name Timer output
Function Pins for waveform outputs by output compare
8-bit timer (TMR) TMO0, TMO1
TMCI0, TMCI1, I TMRI0, TMRI1 Realtime clock (RTC) Serial communication interface with FIFO (SCIF)
2
Timer clock/timer Input pins for an external clock or an reset input external reset for the timer Crystal resonator Pin connected to 32.768-kHz crystal for RTC resonator Transmit data Receive data Serial clock Serial clock pin Serial data pin SSI data I/O SSI clock I/O Data output pins Data input pins Clock input/output pins Serial clock input/output pin Serial data input/output pin I/O pins for serial data I/O pins for serial clocks
RTC_X1 RTC_X2 TxD7 to TxD0 RxD7 to RxD0 SCK7 to SCK0
I O O I I/O I/O I/O I/O I/O I/O I
I C bus SCL2 to SCL0 interface 3 (IIC3) SDA2 to SDA0 Serial sound interface (SSI) SSIDATA0, SSIDATA1 SSISCK0, SSISCK1 SSIWS0, SSIWS1 AUDIO_CLK
SSI clock LR I/O I/O pins for word selection External clock for Input pin of external clock for SSI SSI audio audio (32/44.1/48 kHz x 256/384/512). A clock input to the divider is selected from an oscillation clock input on this pin or pins AUDIO_X1 and AUDIO_X2. Crystal resonator Pins connected to a crystal resonator for SSI audio for SSI audio. An external clock can be input on pin AUDIO_X1 (32/44.1/48 kHz x 256/384/512). A clock input to the divider is selected from an oscillation clock input on these pins or the AUDIO_CLK pin.
AUDIO_X1 AUDIO_X2
I O
Rev. 2.00 Sep. 07, 2007 Page 20 of 1312 REJ09B0320-0200
Section 1 Overview
Classification Controller area network (RCAN-ET) [R5S72611] [R5S72613]
Symbol CTx0, CTx1 CRx0, CRx1
I/O O I
Name
Function
CAN bus transmit Output pin for transmit data on the data CAN bus CAN bus receive Output pin for receive data on the data CAN bus IEB receive data Input pin for receive data on IEB IEB transmit data Output pin for transmit data on IEB
IEBusTM controller IERxD (IEB) IETxD [R5S72612] [R5S72613] A/D converter AN7 to AN0 ADTRG D/A converter Analog power supply DA1, DA0 AVcc AVref AVss I/O ports PA31 to PA0 PB31 to PB0 PC25 to PC22 PC21 to PC0 PD16 to PD15 PD14 to PD0 PE7 to PE0 PF7 to PF0 User debugging interface (H-UDI) UDTCK* UDTMS* UDTDI* UDTDO UDTRST*
I O
I I O I I I I/O I/O I I/O I I/O I I/O I I I O I
Analog input pins Analog input pins A/D conversion trigger input Analog output pins Analog power supply External trigger input pin for starting A/D conversion Analog output pins Power supply pins for the A/D converter and D/A converter
Analog reference Reference voltage input pin for the power supply A/D converter and D/A converter Analog ground General port General port General port General port General port General port General port General port Test clock Test data input Test data output Test reset Ground pins for the A/D converter and D/A converter 32-bit general I/O port pins 32-bit general I/O port pins 4-bit general input port pins 22-bit general I/O port pins 2-bit general input port pins 15-bit general I/O port pins 8-bit general input port pins 8-bit general I/O port pins Test-clock input pin Serial input pin for instructions and data Serial output pin for instructions and data Initialization-signal input pin
Test mode select Test-mode select signal input pin
Rev. 2.00 Sep. 07, 2007 Page 21 of 1312 REJ09B0320-0200
Section 1 Overview
Classification Advanced user debugger II (AUD-II)
Symbol AUDATA3 to AUDATA0 AUDCK AUDSYNC AUDMD AUDRST
I/O I/O
Name AUD data
Function Input pins for monitor addresses/data I/O pins External clock input pin Input pin for an signal identifying the data start position Pin to select the AUD mode Input pins for an AUD reset Trigger output pin for UBC condition match
I I I I O
AUD clock AUD sync signal AUD mode AUD reset User break trigger output
User break controller (UBC) Note: *
UBCTRG
The pin with the pull-up function.
Rev. 2.00 Sep. 07, 2007 Page 22 of 1312 REJ09B0320-0200
Section 2 CPU
Section 2 CPU
2.1 Register Configuration
The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers
Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and restoring the status register (SR) and program counter (PC) in exception handling is accomplished by referencing the stack using R15.
31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0
Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing.
Figure 2.1 General Registers
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Section 2 CPU
2.1.2
Control Registers
The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area.
31 14 13
BO CS
9876543210
MQ I[3:0] ST
Status register (SR)
31
GBR
0 Global base register (GBR) 0
VBR
31
Vector base register (VBR) 0
31
TBR
Jump table base register (TBR)
Figure 2.2 Control Registers (1) Status Register (SR)
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 BO 0 R/W 29 -- 0 R 13 CS 0 R/W 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 M -- R/W 24 -- 0 R 8 Q -- R/W 1 R/W 23 -- 0 R 7 22 -- 0 R 6 I[3:0] 1 R/W 1 R/W 1 R/W 21 -- 0 R 5 20 -- 0 R 4 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 S -- R/W 16 -- 0 R 0 T -- R/W
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Section 2 CPU
Bit 31 to 15
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
14 13
BO CS
0 0
R/W R/W
BO Bit Indicates that a register bank has overflowed. CS Bit Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-limit value or fallen below the saturation lower-limit value.
12 to 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9 8 7 to 4 3, 2
M Q I[3:0] --
-- -- 1111 All 0
R/W R/W R/W R
M Bit Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Reserved These bits are always read as 0. The write value should always be 0.
1 0
S T
-- --
R/W R/W
S Bit Specifies a saturation operation for a MAC instruction. T Bit True/false condition or carry/borrow bit
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Section 2 CPU
(2)
Global Base Register (GBR)
GBR is referenced as the base address in a GBR-referencing MOV instruction. (3) Vector Base Register (VBR)
VBR is referenced as the branch destination base address in the event of an exception or an interrupt. (4) Jump Table Base Register (TBR)
TBR is referenced as the start address of a function table located in memory in a JSR/N@@(disp8,TBR) table-referencing subroutine call instruction. 2.1.3 System Registers
The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or multiply and accumulate operations. PR stores the return address from a subroutine procedure. PC indicates the program address being executed and controls the flow of the processing.
31 MACH MACL 31 PR 0 0
Multiply and accumulate register high (MACH) and multiply and accumulate register low (MACL): Store the results of multiply or multiply and accumulate operations.
Procedure register (PR): Stores the return address from a subroutine procedure.
31 PC
0
Program counter (PC): Indicates the four bytes ahead of the current instruction.
Figure 2.3 System Registers (1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate Register Low (MACL)
MACH and MACL are used as the addition value in a MAC instruction, and store the result of a MAC or MUL instruction.
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Section 2 CPU
(2)
Procedure Register (PR)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC)
PC indicates the address of the instruction being executed. 2.1.4 Register Banks
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 6.8, Register Banks. 2.1.5 Initial Values of Registers
Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers
Register R0 to R14 R15 (SP) Control registers SR Initial Value Undefined Value of the stack pointer in the vector address table Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table
Classification General registers
GBR, TBR VBR System registers MACH, MACL, PR PC
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Section 2 CPU
2.2
2.2.1
Data Formats
Data Format in Registers
Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register.
31 Longword 0
Figure 2.4 Data Format in Registers 2.2.2 Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in sign-extended or zero-extended form. A word operand should be accessed at a word boundary (an even address of multiple of two bytes: address 2n), and a longword operand at a longword boundary (an even address of multiple of four bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any address. Only big-endian byte order can be selected for the data format. Data formats in memory are shown in figure 2.5.
Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword 23 Byte Address m + 3
Address m + 2 15 Byte Word 7 Byte 0
Figure 2.5 Data Formats in Memory
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Section 2 CPU
2.2.3
Immediate Data Format
Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction. The MOVI20 instruction stores immediate data in the destination register in sign-extended form. The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it in the destination register in sign-extended form. Word or longword immediate data is not located in the instruction code, but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. See examples given in section 2.3.1 (10), Immediate Data.
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Section 2 CPU
2.3
2.3.1
Instruction Features
RISC-Type Instruction Set
Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions
Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions
The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease of use. (3) One Instruction per State
Each basic instruction can be executed in one cycle using the pipeline system. (4) Data Length
Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data in memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It is also handled as longword data. Table 2.2
SH-2A CPU MOV.W ADD
Sign Extension of Word Data
Description @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD instruction. H'1234 Example of Other CPU ADD.W #H'1234,R0
.DATA.W
Note: @(disp, PC) accesses the immediate data.
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Section 2 CPU
(5)
Load-Store Architecture
Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. (6) Delayed Branch Instructions
With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. This reduces disturbance of the pipeline control when a branch is taken. In a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution such as register updating excluding the actual branch operation, is performed in the order of delayed branch instruction delay slot instruction. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.3
SH-2A CPU BRA ADD TRGET R1,R0
Delayed Branch Instructions
Description Executes the ADD before branching to TRGET. Example of Other CPU ADD.W BRA R1,R0 TRGET
(7)
Unconditional Branch Instructions with No Delay Slot
The SH-2A additionally features unconditional branch instructions in which a delay slot instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code size. (8) Multiply/Multiply-and-Accumulate Operations
16-bit x 16-bit 32-bit multiply operations are executed in one to two cycles. 16-bit x 16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit x 32-bit 64-bit multiply and 32-bit x 32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four cycles.
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Section 2 CPU
(9)
T Bit
The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Table 2.4
SH-2A CPU CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET
T Bit
Description T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. Example of Other CPU CMP.W BGE BLT SUB.W BEQ R1,R0 TRGET0 TRGET1 #1,R0 TRGET
(10) Immediate Data Byte immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for 21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a register. Table 2.5 Immediate Data Accessing
SH-2A CPU MOV MOVI20 MOVI20 MOVI20S OR 32-bit immediate MOV.L .DATA.L #H'12,R0 #H'1234,R0 #H'12345,R0 #H'12345,R0 #H'67,R0 @(disp,PC),R0 ................. H'12345678 Note: @(disp, PC) accesses the immediate data. MOV.L #H'12345678,R0 Example of Other CPU MOV.B MOV.W MOV.L MOV.L #H'12,R0 #H'1234,R0 #H'12345,R0 #H'1234567,R0
Classification 8-bit immediate 16-bit immediate 20-bit immediate 28-bit immediate
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Section 2 CPU
(11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in register indirect addressing mode. With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also possible to transfer immediate data located in the instruction code to a register and to reference the data in register indirect addressing mode. However, when referencing data using an absolute address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register. Table 2.6 Absolute Address Accessing
SH-2A CPU MOVI20 MOV.B 21 to 28 bits MOVI20S OR MOV.B 29 bits or more MOV.L MOV.B .DATA.L #H'12345,R1 @R1,R0 #H'12345,R1 #H'67,R1 @R1,R0 @(disp,PC),R1 @R1,R0 .................. H'12345678 MOV.B @H'12345678,R0 MOV.B @H'1234567,R0 Example of Other CPU MOV.B @H'12345,R0
Classification Up to 20 bits
(12) 16-Bit/32-Bit Displacement When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indexed indirect register addressing mode. Table 2.7 Displacement Accessing
SH-2A CPU MOV.W MOV.W .DATA.W @(disp,PC),R0 @(R0,R1),R2 .................. H'1234 Example of Other CPU MOV.W @(H'1234,R1),R2
Classification 16-bit displacement
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Section 2 CPU
2.3.2
Addressing Modes
Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses
Effective Address Calculation The effective address is register Rn. (The operand is the contents of register Rn.) Equation --
Addressing Mode Instruction Format Register direct Register indirect Rn
@Rn
The effective address is the contents of register Rn Rn.
Rn Rn
Register indirect @Rn+ with post-increment
The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation.
Rn Rn + 1/2/4 1/2/4 + Rn
Rn (After instruction execution) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn
Register indirect @-Rn with pre-decrement
The effective address is the value obtained by Byte: subtracting a constant from Rn. 1 is subtracted Rn - 1 Rn for a byte operation, 2 for a word operation, and Word: 4 for a longword operation. Rn - 2 Rn
Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4
Longword: Rn - 4 Rn (Instruction is executed with Rn after this calculation)
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Section 2 CPU
Addressing Mode Instruction Format Register indirect with displacement @(disp:4,Rn)
Effective Address Calculation The effective address is the sum of Rn and a 4-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation.
Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4
Equation Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4
Register indirect with displacement
@(disp:12,Rn)
The effective address is the sum of Rn and a 12-bit displacement (disp). The value of disp is zero-extended.
Rn + disp (zero-extended) Rn + disp
Byte: Rn + disp Word: Rn + disp Longword: Rn + disp
Indexed register indirect
@(R0,Rn)
The effective address is the sum of Rn and R0.
Rn + R0 Rn + R0
Rn + R0
GBR indirect with displacement
@(disp:8,GBR)
The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation.
GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4
Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4
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Section 2 CPU
Addressing Mode Instruction Format Indexed GBR indirect @(R0,GBR)
Effective Address Calculation The effective address is the sum of GBR value and R0.
GBR + R0 GBR + R0
Equation GBR + R0
TBR duplicate indirect with displacement
@@ (disp:8,TBR)
The effective address is the sum of TBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and is multiplied by 4.
TBR disp (zero-extended) + TBR + disp x 4
Contents of address (TBR + disp x 4)
x
(TBR 4 + disp x 4)
PC indirect with displacement
@(disp:8,PC)
The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked.
PC & H'FFFFFFFC disp (zero-extended) x 2/4 (for longword) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4
Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4
+
PC relative
disp:8
The effective address is the sum of PC value and the value that is obtained by doubling the sign-extended 8-bit displacement (disp).
PC disp (sign-extended) x 2 + PC + disp x 2
PC + disp x 2
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Section 2 CPU
Addressing Mode Instruction Format PC relative disp:12
Effective Address Calculation The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp).
PC disp (sign-extended) x 2 + PC + disp x 2
Equation PC + disp x 2
Rn
The effective address is the sum of PC value and Rn.
PC + Rn PC + Rn
PC + Rn
Immediate
#imm:20
The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended.
31 19 0 Signextended imm (20 bits)
--
The 20-bit immediate data (imm) for the MOVI20S -- instruction is shifted by eight bits to the left, the upper bits are sign-extended, and the lower bits are padded with zero.
31 27 8 0 imm (20 bits) 00000000
Sign-extended
#imm:8
The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended.
--
#imm:8
The 8-bit immediate data (imm) for the MOV, ADD, -- and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. The 3-bit immediate data (imm) for the BAND, BOR, BXOR, BST, BLD, BSET, and BCLR instructions indicates the target bit location. -- --
#imm:8
#imm:3
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Section 2 CPU
2.3.3
Instruction Format
The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: * * * * * xxxx: mmmm: nnnn: iiii: dddd: Instruction code Source register Destination register Immediate data Displacement Instruction Formats
Source Operand --
0 xxxx xxxx xxxx xxxx
Table 2.9
Instruction Formats 0 format
15
Destination Operand --
Example NOP
n format
15 xxxx 0 nnnn xxxx xxxx
-- Control register or system register
nnnn: Register direct nnnn: Register direct
MOVT STS DIVU
Rn MACH,Rn R0,Rn
R0 (Register direct) nnnn: Register direct Control register or system register mmmm: Register direct R15 (Register indirect with postincrement) nnnn: Register indirect with predecrement R15 (Register indirect with predecrement) nnnn: Register direct
STC.L SR,@-Rn
MOVMU.L Rm,@-R15 MOVMU.L @R15+,Rn MOV.L R0,@Rn+
R0 (Register direct) nnnn: (Register indirect with postincrement)
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Section 2 CPU
Instruction Formats m format
15 xxxx mmmm xxxx xxxx 0
Source Operand mmmm: Register direct mmmm: Register indirect with postincrement mmmm: Register indirect mmmm: Register indirect with predecrement
Destination Operand Control register or system register Control register or system register --
Example LDC Rm,SR
LDC.L @Rm+,SR
JMP
@Rm
R0 (Register direct) MOV.L @-Rm,R0
mmmm: PC relative -- using Rm nm format
15 xxxx nnnn mmmm xxxx 0
BRAF ADD
Rm Rm,Rn
mmmm: Register direct mmmm: Register direct
nnnn: Register direct nnnn: Register indirect
MOV.L Rm,@Rn MAC.W @Rm+,@Rn+
mmmm: Register MACH, MACL indirect with postincrement (multiplyand-accumulate) nnnn*: Register indirect with postincrement (multiplyand-accumulate) mmmm: Register indirect with postincrement mmmm: Register direct mmmm: Register direct md format
15 xxxx xxxx mmmm dddd 0
nnnn: Register direct nnnn: Register indirect with predecrement nnnn: Indexed register indirect
MOV.L
@Rm+,Rn
MOV.L
Rm,@-Rn
MOV.L Rm,@(R0,Rn)
mmmmdddd: Register indirect with displacement
R0 (Register direct) MOV.B @(disp,Rm),R0 MOV.B R0,@(disp,Rn)
nd4 format
15 xxxx xxxx nnnn dddd 0
R0 (Register direct) nnnndddd: Register indirect with displacement
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Section 2 CPU
Instruction Formats nmd format
15 xxxx nnnn mmmm dddd 0
Source Operand mmmm: Register direct mmmmdddd: Register indirect with displacement
Destination Operand
Example
nnnndddd: Register MOV.L indirect with Rm,@(disp,Rn) displacement nnnn: Register direct MOV.L @(disp,Rm),Rn
nmd12 format
32 xxxx 15 xxxx 16 nnnn mmmm xxxx 0 dddd dddd dddd
mmmm: Register direct mmmmdddd: Register indirect with displacement dddddddd: GBR indirect with displacement
nnnndddd: Register MOV.L indirect with Rm,@(disp12,Rn) displacement nnnn: Register direct MOV.L @(disp12,Rm),Rn
d format
15 xxxx xxxx dddd dddd 0
R0 (Register direct) MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR)
R0 (Register direct) dddddddd: GBR indirect with displacement dddddddd: PC relative with displacement dddddddd: TBR duplicate indirect with displacement dddddddd: PC relative d12 format
15 xxxx dddd dddd dddd 0
R0 (Register direct) MOVA @(disp,PC),R0 -- JSR/N @@(disp8,TBR) BF BRA label label
--
dddddddddddd: PC -- relative dddddddd: PC relative with displacement iiiiiiii: Immediate nnnn: Register direct Indexed GBR indirect
(label = disp + PC) MOV.L @(disp,PC),Rn AND.B #imm,@(R0,GBR) #imm,R0 #imm
nd8 format
15 xxxx nnnn dddd dddd 0
i format
15 xxxx xxxx iiii 0 iiii
iiiiiiii: Immediate iiiiiiii: Immediate
R0 (Register direct) AND -- TRAPA
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Section 2 CPU
Instruction Formats ni format
15 xxxx nnnn iiii iiii 0
Source Operand iiiiiiii: Immediate
Destination Operand nnnn: Register direct --
Example ADD #imm,Rn
ni3 format
15 xxxx xxxx nnnn x iii 0
nnnn: Register direct iii: Immediate --
BLD
#imm3,Rn
nnnn: Register direct iii: Immediate nnnn: Register direct
BST
#imm3,Rn
ni20 format
32 xxxx 15 iiii 16 nnnn iiii xxxx 0 iiii iiii iiii
iiiiiiiiiiiiiiiiiiii: Immediate
MOVI20 #imm20, Rn
nid format
32 xxxx 15 xiii 16 xxxx nnnn xxxx 0 dddd dddd dddd
nnnndddddddddddd -- : Register indirect with displacement iii: Immediate --
BLD.B #imm3,@(disp12,Rn)
nnnndddddddddddd BST.B #imm3,@(disp12,Rn) : Register indirect with displacement iii: Immediate
Note:
*
In multiply-and-accumulate instructions, nnnn is the source register.
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Section 2 CPU
2.4
2.4.1
Instruction Set
Instruction Set by Classification
Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions
Classification Types Operation Code Function No. of Instructions
Data transfer
13
MOV
Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Reverse stack transfer
62
MOVA MOVI20 MOVI20S MOVML MOVMU MOVRT MOVT MOVU NOTT PREF SWAP XTRCT
Effective address transfer 20-bit immediate data transfer 20-bit immediate data transfer 8-bit left-shit R0-Rn register save/restore Rn-R14 and PR register save/restore T bit inversion and transfer to Rn T bit transfer Unsigned data transfer T bit inversion Prefetch to operand cache Swap of upper and lower bytes Extraction of the middle of registers connected
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Section 2 CPU
Classification
Types
Operation Code
Function
No. of Instructions
Arithmetic operations
26
ADD ADDC ADDV
Binary addition Binary addition with carry Binary addition with overflow check
40
CMP/cond Comparison CLIPS CLIPU DIVS DIVU DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULR MULS MULU NEG NEGC SUB SUBC SUBV Signed saturation value comparison Unsigned saturation value comparison Signed division (32 / 32) Unsigned division (32 / 32) One-step division Initialization of signed one-step division Initialization of unsigned one-step division Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-precision multiply-and-accumulate operation Double-precision multiply operation Signed multiplication with result storage in Rn Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow
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Section 2 CPU
Classification
Types
Operation Code
Function
No. of Instructions
Logic operations
6
AND NOT OR TAS TST XOR
Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit Dynamic arithmetic shift One-bit arithmetic left shift One-bit arithmetic right shift Dynamic logical shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift
14
Shift
12
ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn
16
Branch
10
BF BT BRA BRAF BSR BSRF JMP JSR RTS RTV/N
Conditional branch, conditional delayed branch 15 (branch when T = 0) Conditional branch, conditional delayed branch (branch when T = 1) Unconditional delayed branch Unconditional delayed branch Delayed branch to subroutine procedure Delayed branch to subroutine procedure Unconditional delayed branch Branch to subroutine procedure Delayed branch to subroutine procedure Return from subroutine procedure Delayed return from subroutine procedure Return from subroutine procedure with Rm R0 transfer
Rev. 2.00 Sep. 07, 2007 Page 44 of 1312 REJ09B0320-0200
Section 2 CPU
Classification
Types
Operation Code
Function
No. of Instructions
System control 14
CLRT CLRMAC LDBANK LDC LDS NOP
T bit clear MAC register clear Register restoration from specified register bank entry Load to control register Load to system register No operation
36
RESBANK Register restoration from register bank RTE SETT SLEEP STBANK STC STS TRAPA Floating-point instructions 19 FABS FADD FCMP FCNVDS FCNVSD FDIV FLDI0 FLDI1 FLDS FLOAT FMAC FMOV FMUL FNEG Return from exception handling T bit set Transition to power-down mode Register save to specified register bank entry Store control register data Store system register data Trap exception handling Floating-point absolute value Floating-point addition Floating-point comparison Conversion from double-precision to singleprecision Conversion from single-precision to doubleprecision Floating-point division Floating-point load immediate 0 Floating-point load immediate 1 Floating-point load into system register FPUL Conversion from integer to floating-point Floating-point multiply and accumulate operation Floating-point data transfer Floating-point multiplication Floating-point sign inversion 48
Rev. 2.00 Sep. 07, 2007 Page 45 of 1312 REJ09B0320-0200
Section 2 CPU
Classification
Types
Operation Code
Function
No. of Instructions
Floating-point instructions
19
FSCHG FSQRT FSTS FSUB FTRC
SZ bit inversion Floating-point square root Floating-point store from system register FPUL Floating-point subtraction Floating-point conversion with rounding to integer Load into floating-point system register Store from floating-point system register Bit AND Bit clear Bit load Bit OR Bit set Bit store Bit exclusive OR
48
FPU-related CPU instructions Bit manipulation
2
LDS STS
8
10
BAND BCLR BLD BOR BSET BST BXOR
14
BANDNOT Bit NOT AND BORNOT BLDNOT Total: 112 Bit NOT OR Bit NOT load 253
Rev. 2.00 Sep. 07, 2007 Page 46 of 1312 REJ09B0320-0200
Section 2 CPU
The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification.
Instruction
Indicated by mnemonic.
Instruction Code
Indicated in MSB LSB order.
Operation
Indicates summary of operation.
Execution States
Value when no wait states are inserted.*1
T Bit
Value of T bit after instruction is executed. Explanation of Symbols --: No change
Explanation of Symbols Rm: Rn: Source register Destination register
Explanation of Symbols mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: dddd: Immediate data Displacement
Explanation of Symbols , : (xx): Transfer direction Memory operand
imm: Immediate data disp: Displacement*2
M/Q/T: Flag bits in SR &: |: ^: ~: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit
<>n: n-bit right shift
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory register) is the same as the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by x1, x2, or x4. For details, refer to the SH-2A, SH2A-FPU Software Manual.
Rev. 2.00 Sep. 07, 2007 Page 47 of 1312 REJ09B0320-0200
Section 2 CPU
2.4.2
Data Transfer Instructions
Table 2.11 Data Transfer Instructions
Execution Cycles 1 1 Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes SH-2A Yes Yes
Instruction MOV MOV.W #imm,Rn @(disp,PC),Rn
Instruction Code
Operation
1110nnnniiiiiiii imm sign extension Rn 1001nnnndddddddd (disp x 2 + PC) sign extension Rn 1101nnnndddddddd (disp x 4 + PC) Rn 0110nnnnmmmm0011 Rm Rn 0010nnnnmmmm0000 Rm (Rn) 0010nnnnmmmm0001 Rm (Rn) 0010nnnnmmmm0010 Rm (Rn) 0110nnnnmmmm0000 (Rm) sign extension Rn 0110nnnnmmmm0001 (Rm) sign extension Rn 0110nnnnmmmm0010 (Rm) Rn 0010nnnnmmmm0100 Rn-1 Rn, Rm (Rn) 0010nnnnmmmm0101 Rn-2 Rn, Rm (Rn) 0010nnnnmmmm0110 Rn-4 Rn, Rm (Rn) Rm + 1 Rm
MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B
@(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn
1 1 1 1 1 1 1 1 1 1 1
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
0110nnnnmmmm0100 (Rm) sign extension Rn, 1 0110nnnnmmmm0101 (Rm) sign extension Rn, 1 Rm + 2 Rm 0110nnnnmmmm0110 (Rm) Rn, Rm + 4 Rm 10000000nnnndddd R0 (disp + Rn) 10000001nnnndddd R0 (disp x 2 + Rn) 0001nnnnmmmmdddd Rm (disp x 4 + Rn) 10000100mmmmdddd (disp + Rm) sign extension R0 10000101mmmmdddd (disp x 2 + Rm) sign extension R0 0101nnnnmmmmdddd (disp x 4 + Rm) Rn 0000nnnnmmmm0100 Rm (R0 + Rn) 0000nnnnmmmm0101 Rm (R0 + Rn)
MOV.W
@Rm+,Rn
Yes
Yes
Yes
MOV.L MOV.B MOV.W MOV.L MOV.B
@Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0
1 1 1 1 1
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
MOV.W
@(disp,Rm),R0
1
Yes
Yes
Yes
MOV.L MOV.B MOV.W
@(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn)
1 1 1
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 48 of 1312 REJ09B0320-0200
Section 2 CPU
Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes SH-2A Yes Yes
Instruction MOV.L MOV.B Rm,@(R0,Rn) @(R0,Rm),Rn
Instruction Code
Operation
Execution Cycles 1 1
0000nnnnmmmm0110 Rm (R0 + Rn) 0000nnnnmmmm1100 (R0 + Rm) sign extension Rn 0000nnnnmmmm1101 (R0 + Rm) sign extension Rn 0000nnnnmmmm1110 (R0 + Rm) Rn 11000000dddddddd R0 (disp + GBR) 11000001dddddddd R0 (disp x 2 + GBR) 11000010dddddddd R0 (disp x 4 + GBR) 11000100dddddddd (disp + GBR) sign extension R0 11000101dddddddd (disp x 2 + GBR) sign extension R0 11000110dddddddd (disp x 4 + GBR) R0 0100nnnn10001011 R0 (Rn), Rn + 1 Rn 0100nnnn10011011 R0 (Rn), Rn + 2 Rn 0100nnnn10101011 R0 Rn), Rn + 4 Rn 0100mmmm11001011 Rm-1 Rm, (Rm) sign extension R0 0100mmmm11011011 Rm-2 Rm, (Rm) sign extension R0 0100mmmm11101011 Rm-4 Rm, (Rm) R0
MOV.W
@(R0,Rm),Rn
1
Yes
Yes
Yes
MOV.L MOV.B MOV.W MOV.L MOV.B
@(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0
1 1 1 1 1
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
MOV.W
@(disp,GBR),R0
1
Yes
Yes
Yes
MOV.L MOV.B MOV.W MOV.L MOV.B
@(disp,GBR),R0 R0,@Rn+ R0,@Rn+ R0,@Rn+ @-Rm,R0
1 1 1 1 1
Yes
Yes
Yes Yes Yes Yes Yes
MOV.W
@-Rm,R0
1
Yes
MOV.L MOV.B
@-Rm,R0
1 1
Yes Yes
Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm (disp + Rn) 0000dddddddddddd
MOV.W
Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm (disp x 2 + Rn) 0001dddddddddddd
1
Yes
MOV.L
Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm (disp x 4 + Rn) 0010dddddddddddd
1
Yes
MOV.B
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) 0100dddddddddddd sign extension Rn
1
Yes
MOV.W
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp x 2 + Rm) 0101dddddddddddd sign extension Rn
1
Yes
MOV.L
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp x 4 + Rm) Rn 0110dddddddddddd
1
Yes
Rev. 2.00 Sep. 07, 2007 Page 49 of 1312 REJ09B0320-0200
Section 2 CPU
Compatibility SH2, T Bit SH2E SH4 Yes Yes SH-2A Yes Yes
Instruction MOVA MOVI20 @(disp,PC),R0 #imm20,Rn
Instruction Code
Operation
Execution Cycles 1 1
11000111dddddddd disp x 4 + PC R0 0000nnnniiii0000 imm sign extension Rn iiiiiiiiiiiiiiii
MOVI20S #imm20,Rn
0000nnnniiii0001 imm << 8 sign extension iiiiiiiiiiiiiiii Rn
1
Yes
MOVML.L Rm,@-R15
0100mmmm11110001 R15-4 R15, Rm (R15) R15-4 R15, Rm-1 (R15) : R15-4 R15, R0 (R15) Note: When Rm = R15, read Rm as PR 0100nnnn11110101 (R15) R0, R15 + 4 R15 (R15) R1, R15 + 4 R15 : (R15) Rn Note: When Rn = R15, read Rm as PR 0100mmmm11110000 R15-4 R15, PR (R15) R15-4 R15, R14 (R15) : R15-4 R15, Rm (R15) Note: When Rm = R15, read Rm as PR 0100nnnn11110100 (R15) Rn, R15 + 4 R15 (R15) Rn + 1, R15 + 4 R15 : (R15) R14, R15 + 4 R15 (R15) PR Note: When Rn = R15, read Rm as PR 0000nnnn00111001 ~T Rn 0000nnnn00101001 T Rn 1000dddddddddddd zero extension Rn
1 to 16
Yes
MOVML.L @R15+,Rn
1 to 16
Yes
MOVMU.L Rm,@-R15
1 to 16
Yes
MOVMU.L @R15+,Rn
1 to 16
Yes
MOVRT MOVT MOVU.B
Rn Rn
1 1 1
Yes Yes
Yes Yes Yes
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm)
MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp x 2 + Rm) 1001dddddddddddd zero extension Rn
1
Yes
Rev. 2.00 Sep. 07, 2007 Page 50 of 1312 REJ09B0320-0200
Section 2 CPU
Compatibility SH2, T Bit SH2E SH4 Operation result PREF SWAP.B @Rn Rm,Rn 0000nnnn10000011 (Rn) operand cache 0110nnnnmmmm1000 Rm swap lower 2 bytes Rn SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm swap upper and lower words Rn XTRCT Rm,Rn 0010nnnnmmmm1101 Middle 32 bits of Rm:Rn Rn 1 Yes Yes Yes 1 Yes Yes Yes 1 1 Yes Yes Yes Yes Yes SH-2A Yes
Instruction NOTT
Instruction Code
Operation
Execution Cycles 1
0000000001101000 ~T T
Rev. 2.00 Sep. 07, 2007 Page 51 of 1312 REJ09B0320-0200
Section 2 CPU
2.4.3
Arithmetic Operation Instructions
Table 2.12 Arithmetic Operation Instructions
Execution Cycles 1 1 Compatibility T Bit Carry Overflow CMP/EQ #imm,R0 10001000iiiiiiii When R0 = imm, 1 T Otherwise, 0 T When Rn = Rm, 1 T Otherwise, 0 T When Rn Rm (unsigned), 1T Otherwise, 0 T CMP/GE Rm,Rn 0011nnnnmmmm0011 When Rn Rm (signed), 1T Otherwise, 0 T CMP/HI Rm,Rn 0011nnnnmmmm0110 When Rn > Rm (unsigned), 1T Otherwise, 0 T CMP/GT Rm,Rn 0011nnnnmmmm0111 When Rn > Rm (signed), 1T Otherwise, 0 T CMP/PL Rn 0100nnnn00010101 When Rn > 0, 1 T Otherwise, 0 T When Rn 0, 1 T Otherwise, 0 T 1 1 1 1 1 Comparison result CMP/EQ Rm,Rn 0011nnnnmmmm0000 1 Comparison result CMP/HS Rm,Rn 0011nnnnmmmm0010 1 Comparison result Comparison result Comparison result Comparison result Comparison result CMP/PZ Rn 0100nnnn00010001 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 When any bytes are equal, 1T Otherwise, 0 T 1 Comparison result Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SH2, SH2E SH4 Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes
Instruction ADD ADD ADDC ADDV Rm,Rn #imm,Rn Rm,Rn Rm,Rn
Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111
Operation Rn + Rm Rn Rn + imm Rn
Rn + Rm + T Rn, carry T 1 Rn + Rm Rn, overflow T 1
Rev. 2.00 Sep. 07, 2007 Page 52 of 1312 REJ09B0320-0200
Section 2 CPU
Compatibility T Bit SH2, SH2E SH4 SH-2A Yes
Instruction CLIPS.B Rn
Instruction Code 0100nnnn10010001
Operation When Rn > (H'0000007F), (H'0000007F) Rn, 1 CS when Rn < (H'FFFFFF80), (H'FFFFFF80) Rn, 1 CS
Execution Cycles 1
CLIPS.W
Rn
0100nnnn10010101
When Rn > (H'00007FFF), (H'00007FFF) Rn, 1 CS When Rn < (H'FFFF8000), (H'FFFF8000) Rn, 1 CS
1
Yes
CLIPU.B
Rn
0100nnnn10000001
When Rn > (H'000000FF), (H'000000FF) Rn, 1 CS
1

Yes
CLIPU.W Rn
0100nnnn10000101
When Rn > (H'0000FFFF), (H'0000FFFF) Rn, 1 CS 1-step division (Rn / Rm)
1
Yes
DIV1
Rm,Rn
0011nnnnmmmm0100
1
Calcu- Yes lation result
Yes
Yes
DIV0S
Rm,Rn
0010nnnnmmmm0111
MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Signed operation of Rn / R0 Rn 32 / 32 32 bits
1
Calcu- Yes lation result
Yes
Yes
DIV0U DIVS R0,Rn
0000000000011001 0100nnnn10010100
1 36
0
Yes
Yes
Yes Yes
DIVU
R0,Rn
0100nnnn10000100
Unsigned operation of Rn / R0 34 Rn 32 / 32 32 bits Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn When Rn is 0, 1 T When Rn is not 0, 0 T
Yes
DMULS.L Rm,Rn
0011nnnnmmmm1101
2
Yes
Yes
Yes
DMULU.L Rm,Rn
0011nnnnmmmm0101
2
Yes
Yes
Yes
DT
Rn
0100nnnn00010000
1
Comparison result
Yes
Yes
Yes
EXTS.B
Rm,Rn
0110nnnnmmmm1110
Byte in Rm is sign-extended Rn
1
Yes
Yes
Yes
EXTS.W
Rm,Rn
0110nnnnmmmm1111
Word in Rm is sign-extended Rn
1
Yes
Yes
Yes
EXTU.B
Rm,Rn
0110nnnnmmmm1100
Byte in Rm is zero-extended Rn
1
Yes
Yes
Yes
Rev. 2.00 Sep. 07, 2007 Page 53 of 1312 REJ09B0320-0200
Section 2 CPU
Compatibility T Bit SH2, SH2E SH4 Yes Yes SH-2A Yes
Instruction EXTU.W Rm,Rn
Instruction Code 0110nnnnmmmm1101
Operation Word in Rm is zero-extended Rn
Execution Cycles 1
MAC.L
@Rm+,@Rn+
0000nnnnmmmm1111
Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 + 64 64 bits Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bits Rn x Rm MACL 32 x 32 32 bits R0 x Rn Rn 32 x 32 32 bits Signed operation of Rn x Rm MACL 16 x 16 32 bits Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 0-Rm Rn 0-Rm-T Rn, borrow T Rn-Rm Rn Rn-Rm-T Rn, borrow T Rn-Rm Rn, underflow T
4
Yes
Yes
Yes
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
3
Yes
Yes
Yes
MUL.L
Rm,Rn
0000nnnnmmmm0111
2
Yes
Yes
Yes
MULR
R0,Rn
0100nnnn10000000
2
Yes
MULS.W
Rm,Rn
0010nnnnmmmm1111
1
Yes
Yes
Yes
MULU.W
Rm,Rn
0010nnnnmmmm1110
1
Yes
Yes
Yes
NEG NEGC SUB SUBC SUBV
Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011
1 1 1 1 1
Yes
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
Borrow Yes Yes
Borrow Yes Overflow Yes
Rev. 2.00 Sep. 07, 2007 Page 54 of 1312 REJ09B0320-0200
Section 2 CPU
2.4.4
Logic Operation Instructions
Table 2.13 Logic Operation Instructions
Execution Cycles 1 1 3 Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes
Instruction AND AND AND.B Rm,Rn #imm,R0 #imm,@(R0,GBR)
Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii
Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) When (Rn) is 0, 1 T Otherwise, 0 T, 1 MSB of(Rn)
NOT OR OR OR.B
Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR)
0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii
1 1 1 3
Yes Yes Yes Yes
Yes Yes Yes Yes
Yes Yes Yes Yes
TAS.B
@Rn
0100nnnn00011011
3
Test result
Yes
Yes
Yes
TST
Rm,Rn
0010nnnnmmmm1000
Rn & Rm When the result is 0, 1 T Otherwise, 0 T
1
Test result
Yes
Yes
Yes
TST
#imm,R0
11001000iiiiiiii
R0 & imm When the result is 0, 1 T Otherwise, 0 T
1
Test result
Yes
Yes
Yes
TST.B
#imm,@(R0,GBR)
11001100iiiiiiii
(R0 + GBR) & imm When the result is 0, 1 T Otherwise, 0 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR)
3
Test result
Yes
Yes
Yes
XOR XOR XOR.B
Rm,Rn #imm,R0 #imm,@(R0,GBR)
0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
1 1 3

Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 55 of 1312 REJ09B0320-0200
Section 2 CPU
2.4.5
Shift Instructions
Table 2.14 Shift Instructions
Execution Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Operation T Rn MSB LSB Rn T T Rn T T Rn T When Rm 0, Rn << Rm Rn When Rm < 0, Rn >> |Rm| [MSB Rn] SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 T Rn 0 MSB Rn T When Rm 0, Rn << Rm Rn When Rm < 0, Rn >> |Rm| [0 Rn] SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn 1 1 1 1 1 1 1 1 MSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 1 1 MSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 1 1 1 Compatibility SH2, T Bit SH2E SH4 MSB LSB MSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 56 of 1312 REJ09B0320-0200
Section 2 CPU
2.4.6
Branch Instructions
Table 2.15 Branch Instructions
Execution Cycles 3/1* Compatibility SH2, T Bit SH2E SH4 Yes Yes SH-2A Yes
Instruction BF label
Instruction Code 10001011dddddddd
Operation When T = 0, disp x 2 + PC PC, When T = 1, nop
BF/S
label
10001111dddddddd
Delayed branch When T = 0, disp x 2 + PC PC, When T = 1, nop When T = 1, disp x 2 + PC PC, When T = 0, nop
2/1*
Yes
Yes
Yes
BT
label
10001001dddddddd
3/1*
Yes
Yes
Yes
BT/S
label
10001101dddddddd
Delayed branch When T = 1, disp x 2 + PC PC, When T = 0, nop
2/1*
Yes
Yes
Yes
BRA
label
1010dddddddddddd
Delayed branch, disp x 2 + PC PC
2

Yes
Yes
Yes
BRAF
Rm
0000mmmm00100011
Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC
2
Yes
Yes
Yes
BSR
label
1011dddddddddddd
2
Yes
Yes
Yes
BSRF
Rm
0000mmmm00000011
2
Yes
Yes
Yes
JMP JSR
@Rm @Rm
0100mmmm00101011 0100mmmm00001011
2 2
Yes Yes
Yes Yes
Yes Yes
JSR/N JSR/N
@Rm
0100mmmm01001011
PC-2 PR, Rm PC PC-2 PR, (disp x 4 + TBR) PC Delayed branch, PR PC PR PC Rm R0, PR PC
3 5

Yes Yes
@@(disp8,TBR) 10000011dddddddd
RTS RTS/N RTV/N Rm
0000000000001011 0000000001101011 0000mmmm01111011
2 3 3
Yes
Yes
Yes Yes Yes
Note:
*
One cycle when the program does not branch.
Rev. 2.00 Sep. 07, 2007 Page 57 of 1312 REJ09B0320-0200
Section 2 CPU
2.4.7
System Control Instructions
Table 2.16 System Control Instructions
Execution Instruction CLRT CLRMAC LDBANK @Rm,R0 Instruction Code 0000000000001000 0000000000101000 0100mmmm11100101 Operation 0T 0 MACH,MACL R0 LDC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RESBANK Rm,SR Rm,TBR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR 0100mmmm00001110 0100mmmm01001010 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000001011011 Rm SR Rm TBR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR 3 1 1 1 5 1 1 1 1 1 LSB LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 Compatibility SH2, T Bit SH2E SH4 0 Yes Yes Yes Yes SH-2A Yes Yes Yes
(Specified register bank entry) 6
(Rm) MACH, Rm + 4 Rm 1 (Rm) MACL, Rm + 4 Rm 1 (Rm) PR, Rm + 4 Rm No operation Bank R0 to R14, GBR, MACH, MACL, PR 1 1 9*
RTE
0000000000101011
Delayed branch, stack area PC/SR 1T Sleep R0 (specified register bank entry)
6
Yes
Yes
Yes
SETT SLEEP STBANK R0,@Rn
0000000000011000 0000000000011011 0100nnnn11100001
1 5 7
1
Yes Yes
Yes Yes
Yes Yes Yes
Rev. 2.00 Sep. 07, 2007 Page 58 of 1312 REJ09B0320-0200
Section 2 CPU
Execution Instruction STC STC STC STC STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA SR,Rn TBR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0000nnnn00000010 0000nnnn01001010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation SR Rn TBR Rn GBR Rn VBR Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC/SR stack area, (imm x 4 + VBR) PC Cycles 2 1 1 1 2 1 1 1 1 1 1 1 1 5
Compatibility SH2, T Bit SH2E SH4 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory register) is the same as the register used by the next instruction. * In the event of bank overflow, the number of cycles is 19.
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Section 2 CPU
2.4.8
Floating Point Operation Instructions
Table 2.17 Floating Point Operation Instructions
Compatibility Execution Instruction FABS FABS FADD FADD FCMP/EQ FRn DRn FRm, FRn DRm, DRn FRm, FRn Instruction Code 1111nnnn01011101 1111nnn001011101 1111nnnnmmmm0000 1111nnn0mmm00000 1111nnnnmmmm0100 Operation |FRn|FRn |DRn|DRn FRn+FRmFRn DRn+DRmDRn (FRn=FRm)? 1:0T Cycles 1 1 1 6 1 T Bit Operation result FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn=DRm)? 1:0T 2 Operation result FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn>FRm)? 1:0T 1 Operation result FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn>DRm)? 1:0T 2 Operation result FCNVDS FCNVSD FDIV FDIV FLDI0 FLDI1 FLDS FLOAT FLOAT FMAC FMOV FMOV FMOV.S FMOV.D FMOV.S FMOV.D DRm, FPUL FPUL, DRn FRm, FRn DRm, DRn FRn FRn FRm, FPUL FPUL,FRn FPUL,DRn FR0,FRm,FRn FRm, FRn DRm, DRn @(R0, Rm), FRn @(R0, Rm), DRn @Rm+, FRn @Rm+, DRn 1111mmm010111101 1111nnn010101101 1111nnnnmmmm0011 1111nnn0mmm00011 1111nnnn10001101 1111nnnn10011101 1111mmmm00011101 1111nnnn00101101 1111nnn000101101 1111nnnnmmmm1110 1111nnnnmmmm1100 1111nnn0mmm01100 1111nnnnmmmm0110 1111nnn0mmmm0110 1111nnnnmmmm1001 1111nnn0mmmm1001 (float)DRmFPUL (double)FPULDRn FRn/FRmFRn DRn/DRmDRn 0x00000000FRn 0x3F800000FRn FRmFPUL (float)FPULFRn (double)FPULDRn FR0xFRm+FRnFRn FRmFRn DRmDRn (R0+Rm) FRn (R0+Rm) DRn (Rm) FRn, Rm+=4 (Rm) DRn, Rm+=8 2 2 10 23 1 1 1 1 2 1 1 2 1 2 1 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SH2E Yes SH4 Yes Yes Yes Yes Yes SH-2A/ SH2A-FPU Yes Yes Yes Yes Yes
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Section 2 CPU
Compatibility Execution Instruction FMOV.S FMOV.D FMOV.S @Rm, FRn @Rm, DRn @(disp12,Rm),FRn Instruction Code 1111nnnnmmmm1000 1111nnn0mmmm1000 0011nnnnmmmm0001 0111dddddddddddd FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd FMOV.S FMOV.D FMOV.S FMOV.D FMOV.S FMOV.D FMOV.S FRm, @(R0,Rn) DRm, @( R0,Rn ) FRm, @-Rn DRm, @-Rn FRm, @Rn DRm, @Rn 1111nnnnmmmm0111 1111nnnnmmm00111 1111nnnnmmmm1011 1111nnnnmmm01011 1111nnnnmmmm1010 1111nnnnmmm01010 FRm (R0+Rn) DRm (R0+Rn) Rn-=4, FRm(Rn) Rn-=8, DRm(Rn) FRm(Rn) DRm(Rn) 1 2 1 2 1 2 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (dispx8+Rm) DRn 2 Yes Operation (Rm) FRn (Rm) DRn (dispx4+Rm) FRn Cycles 1 2 1 T Bit SH2E Yes SH4 Yes Yes SH-2A/ SH2A-FPU Yes Yes Yes
FRm, @(disp12,Rn) 0011nnnnmmmm000100 FRm(dispx4+Rn) 11dddddddddddd
FMOV.D
DRm, @(disp12,Rn) 0011nnnnmmm0000100 DRm(dispx8+Rn) 11dddddddddddd
2
Yes
FMUL FMUL FNEG FNEG FSCHG FSQRT FSQRT FSTS FSUB FSUB FTRC FTRC
FRm, FRn DRm, DRn FRn DRn
1111nnnnmmmm0010 1111nnn0mmm00010 1111nnnn01001101 1111nnn001001101 1111001111111101
FRnxFRmFRn DRnxDRmDRn -FRnFRn -DRnDRn FPSCR.SZ=~FPSCR.SZ FRnFRn DRnDRn FPULFRn FRn-FRmFRn DRn-DRmDRn (long)FRmFPUL (long)DRmFPUL
1 6 1 1 1 9 22 1 1 6 1 2

Yes
Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes
Yes Yes Yes Yes Yes
FRn DRn FPUL,FRn FRm, FRn DRm, DRn FRm, FPUL DRm, FPUL
1111nnnn01101101 1111nnn001101101 1111nnnn00001101 1111nnnnmmmm0001 1111nnn0mmm00001 1111mmmm00111101 1111mmm000111101
Yes Yes
Yes Yes Yes
Yes
Yes Yes
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Section 2 CPU
2.4.9
FPU-Related CPU Instructions
Table 2.18 FPU-Related CPU Instructions
Compatibility Execution Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+, FPSCR @Rm+, FPUL FPSCR, Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Instruction Code 0100mmmm01101010 0100mmmm01011010 0100mmmm01100110 0100mmmm01010110 0000nnnn01101010 0000nnnn01011010 0100nnnn01100010 0100nnnn01010010 Operation RmFPSCR RmFPUL (Rm)FPSCR, Rm+=4 (Rm)FPUL, Rm+=4 FPSCRRn FPULRn Rn-=4, FPSCR(Rn) Rn-=4, FPUL(Rn) Cycles 1 1 1 1 1 1 1 1 T Bit SH2E Yes Yes Yes Yes Yes Yes Yes Yes SH4 Yes Yes Yes Yes Yes Yes Yes Yes SH-2A/ SH2A-FPU Yes Yes Yes Yes Yes Yes Yes Yes
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Section 2 CPU
2.4.10
Bit Manipulation Instructions
Table 2.19 Bit Manipulation Instructions
Execution Instruction BAND.B #imm3,@(disp12,Rn) Instruction Code 0011nnnn0iii1001 0100dddddddddddd BANDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1100dddddddddddd BCLR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0000dddddddddddd BCLR BLD.B #imm3,Rn #imm3,@(disp12,Rn) 10000110nnnn0iii 0011nnnn0iii1001 0011dddddddddddd BLD #imm3,Rn 10000111nnnn1iii imm of Rn T 1 0 imm of Rn (imm of (disp + Rn)) T 1 3 Operation result Operation result BLDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1011dddddddddddd BOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0101dddddddddddd BORNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1101dddddddddddd BSET.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0001dddddddddddd BSET BST.B #imm3,Rn #imm3,@(disp12,Rn) 10000110nnnn1iii 0011nnnn0iii1001 0010dddddddddddd BST BXOR.B #imm3,Rn #imm3,@(disp12,Rn) 10000111nnnn0iii 0011nnnn0iii1001 0110dddddddddddd T imm of Rn (imm of (disp + Rn)) ^ T T 1 3 Operation result Yes Yes 1 imm of Rn T (imm of (disp + Rn)) 1 3 Yes Yes 1 ( imm of (disp + Rn)) 3 ~( imm of (disp + Rn)) | T T 3 ~(imm of (disp + Rn)) T ( imm of (disp + Rn)) | T T 3 3 Operation result Operation result Operation result Yes Yes Yes Yes Yes Yes Yes 0 (imm of (disp + Rn)) 3 ~(imm of (disp + Rn)) & T T 3 Operation (imm of (disp + Rn)) & T T Cycles 3 T Bit Operation result Ope-ration result Yes Yes Compatibility SH2, SH2E SH4 SH-2A Yes
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Section 2 CPU
2.5
Processing States
The CPU has four processing states: reset, exception handling, program execution, and powerdown. Figure 2.6 shows the transitions between the states.
Manual reset from any state Power-on reset from any state
Manual reset state
Power-on reset state Reset state Reset canceled Exception handling state NMI interrupt, IRQ interrupt*, Manual reset, and Power-on reset
Interrupt source or DMA address error occurs
NMI interrupt or IRQ interrupt occurs
Exception handling source occurs
Exception handling ends
Program execution state
STBY bit cleared for SLEEP instruction
STBY bit set and DEEP bit clear for SLEEP instruction
STBY and DEEP bits set for SLEEP instruction
Sleep mode
Software standby mode
Deep standby mode Power-down state
Note: * IRQ can be released only by PE7 to PE4 and PC25 to PC22
Figure 2.6 Transitions between Processing States
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Section 2 CPU
(1)
Reset State
In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State
The exception handling state is a transient state that occurs when exception handling sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception handling vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception handling vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. (3) Program Execution State
In the program execution state, the CPU sequentially executes the program. (4) Power-Down State
In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP instruction places the CPU in sleep mode, software standby mode, or deep standby mode.
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Section 2 CPU
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Section 3 Floating-Point Unit (FPU)
Section 3 Floating-Point Unit (FPU)
3.1 Features
The FPU has the following features. * Conforms to IEEE754 standard * 16 single-precision floating-point registers (can also be referenced as eight double-precision registers) * Two rounding modes: Round to nearest and round to zero * Denormalization modes: Flush to zero * Five exception sources: Invalid operation, divide by zero, overflow, underflow, and inexact * Comprehensive instructions: Single-precision, double-precision, and system control When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt to execute an FPU instruction will cause an FPU disable exception.
3.2
3.2.1
Data Formats
Floating-Point Format
A floating-point number consists of the following three fields: * Sign (s) * Exponent (e) * Fraction (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 3.1 and 3.2.
31 s 30 e 23 22 f 0
Figure 3.1 Format of Single-Precision Floating-Point Number
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Section 3 Floating-Point Unit (FPU)
63 s
62 e
52
51 f
0
Figure 3.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows:
e = E + bias
The range of unbiased exponent E is Emin - 1 to Emax + 1. The two values Emin - 1 and Emax + 1 are distinguished as follows. Emin - 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). Table 3.1 shows Emin and Emax values. Table 3.1
Parameter Total bit width Sign bit Exponent field Fraction field Precision Bias Emax Emin
Floating-Point Number Formats and Parameters
Single-Precision 32 bits 1 bit 8 bits 23 bits 24 bits +127 +127 -126 Double-Precision 64 bits 1 bit 11 bits 52 bits 53 bits +1023 +1023 -1022
Floating-point number value v is determined as follows: If E = Emax + 1 and f 0, v is a non-number (NaN) irrespective of sign s If E = Emax + 1 and f = 0, v = (-1)s (infinity) [positive or negative infinity] If Emin E Emax, v = (-1)s2E (1.f) [normalized number] If E = Emin - 1 and f 0, v = (-1)s2Emin (0.f) [denormalized number] If E = Emin - 1 and f = 0, v = (-1)s0 [positive or negative zero] Table 3.2 shows the ranges of the various numbers in hexadecimal notation.
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Section 3 Floating-Point Unit (FPU)
Table 3.2
Type
Floating-Point Ranges
Single-Precision H'7FFF FFFF to H'7FC0 0000 H'7FBF FFFF to H'7F80 0001 H'7F80 0000 H'7F7F FFFF to H'0080 0000 H'007F FFFF to H'0000 0001 H'0000 0000 H'8000 0000 H'8000 0001 to H'807F FFFF H'8080 0000 to H'FF7F FFFF H'FF80 0000 H'FF80 0001 to H'FFBF FFFF H'FFC0 0000 to H'FFFF FFFF Double-Precision H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 H'7FF7 FFFF FFFF FFFF to H'7FF0 0000 0000 0001 H'7FF0 0000 0000 0000 H'7FEF FFFF FFFF FFFF to H'0010 0000 0000 0000 H'000F FFFF FFFF FFFF to H'0000 0000 0000 0001 H'0000 0000 0000 0000 H'8000 0000 0000 0000 H'8000 0000 0000 0001 to H'800F FFFF FFFF FFFF H'8010 0000 0000 0000 to H'FFEF FFFF FFFF FFFF H'FFF0 0000 0000 0000 H'FFF0 0000 0000 0001 to H'FFF7 FFFF FFFF FFFF H'FFF8 0000 0000 0000 to H'FFFF FFFF FFFF FFFF
Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number
3.2.2
Non-Numbers (NaN)
Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: * Sign bit: Don't care * Exponent field: All bits are 1 * Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0.
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Section 3 Floating-Point Unit (FPU)
31 x
30 11111111
23
22 Nxxxxxxxxxxxxxxxxxxxxxx
0
N = 1: sNaN N = 0: qNaN
Figure 3.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. * When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN. * When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this case, the contents of the operation destination register are unchanged. If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit in FPSCR. An exception will not be generated in this case. The qNAN values as operation results are as follows: * Single-precision qNaN: H'7FBF FFFF * Double-precision qNaN: H'7FF7 FFFF FFFF FFFF See the individual instruction descriptions for details of floating-point operations when a nonnumber (NaN) is input. 3.2.3 Denormalized Numbers
For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. In the SH2A-FPU, the DN bit in the status register FPSCR is always set to 1, therefore a denormalized number (source operand or operation result) is always flushed to 0 in a floatingpoint operation that generates a value (an operation other than copy, FNEG, or FABS). When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is processed as it is. See the individual instruction descriptions for details of floating-point operations when a denormalized number is input.
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Section 3 Floating-Point Unit (FPU)
3.3
3.3.1
Register Descriptions
Floating-Point Registers
Figure 3.4 shows the floating-point register configuration. There are sixteen 32-bit floating-point registers FPR0 to FPR15, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14. The correspondence between FRPn and the reference name is determined by the PR and SZ bits in FPSCR. Refer figure 3.4. 1. Floating-point registers, FPRi (16 registers) FPR0 to FPR15 2. Single-precision floating-point registers, FRi (16 registers) FR0 to FR15 indicate FPR0 to FPR15 3. Double-precision floating-point registers or single-precision floating-point vector registers in pairs, DRi (8 registers) A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}
Reference name Transfer instruction case: FPSCR.SZ = 0 FPSCR.SZ = 1 Operation instruction case: FPSCR.PR = 0 FPSCR.PR = 1 FR0 DR0 FR1 FR2 DR2 FR3 FR4 DR4 FR5 FR6 DR6 FR7 FR8 DR8 FR9 FR10 DR10 FR11 FR12 DR12 FR13 FR14 DR14 FR15 Register name
FPR0 FPR1 FPR2 FPR3 FPR4 FPR5 FPR6 FPR7 FPR8 FPR9 FPR10 FPR11 FPR12 FPR13 FPR14 FPR15
Figure 3.4 Floating-Point Registers
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Section 3 Floating-Point Unit (FPU)
3.3.2
Floating-Point Status/Control Register (FPSCR)
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode.
Bit: 31 Initial value: R/W: Bit: 0 R 15 30 0 R 14 29 0 R 13 28 0 R 12 27 0 R 11 26 0 R 10 25 0 R 9 Enable 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 24 0 R 8 23 0 R 7 22 QIS 0 R/W 6 21 0 R 5 20 SZ 0 R/W 4 Flag 0 R/W 0 R/W 0 R/W 19 PR 0 R/W 3 18 DN 1 R 2 17 16
Cause 0 R/W 1 RM1 0 R/W 0 R/W 0 RM0 1 R/W
Cause Initial value: R/W: 0 R/W 0 R/W 0 R/W
Bit 31 to 23
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
22
QIS
0
R/W
Nonnunerical Processing Mode 0: Processes qNaN or as such 1: Treats qNaN or as the same as sNaN (valid only when the V bit in FPSCR enable is set to 1)
21
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
20
SZ
0
R/W
Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits)
19
PR
0
R/W
Precision Mode 0: Floating-point instructions are executed as single-precision operations 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined)
18
DN
1
R
Denormalization Mode (Always fixed to 1 in SH2AFPU) 1: Denormalized number is treated as zero
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Section 3 Floating-Point Unit (FPU)
Bit 17 to 12 11 to 7 6 to 2
Bit Name Cause Enable Flag
Initial Value All 0 All 0 All 0
R/W R/W R/W R/W
Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field When an FPU exception occurs, the bits corresponding to the FPU exception cause field and FPU exception flag field are set to 1. Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 3.3. Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved
1 0
RM1 RM0
0 1
R/W R/W
Table 3.3
Field Name Cause Enable Flag
Bit Allocation for FPU Exception Handling
FPU Error (E) FPU exception cause field FPU exception enable field Bit 17 None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2
FPU exception flag None field
Note: No FPU error occurs in the SH2A-FPU.
3.3.3
Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register that is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number, the processing flow is as follows:
R1 (LDS instruction) FPUL (single-precision FLOAT instruction) FR1
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Section 3 Floating-Point Unit (FPU)
3.4
Rounding
In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. Which of the two rounding methods is to be used is determined by the RM bits in FPSCR. FPSCR.RM[1:0] = 00: Round to Nearest FPSCR.RM[1:0] = 01: Round to Zero (1) Round to Nearest
The operation result is rounded to the nearest expressible value. If there are two nearest expressible values, the one with an LSB of 0 is selected. If the unrounded value is 2Emax (2 - 2-P) or more, the result will be infinity with the same sign as the unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. (2) Round to Zero
The digits below the round bit of the unrounded value are discarded. If the unrounded value is larger than the maximum expressible absolute value, the value will become the maximum expressible absolute value.
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Section 3 Floating-Point Unit (FPU)
3.5
3.5.1
Floating-Point Exceptions
FPU Exception Sources
The exception sources are as follows: * FPU error (E): When FPSCR.DN = 0 and a denormalized number is input (No chance to occur in the SH2A-FPU) * Invalid operation (V): In case of an invalid operation, such as NaN input * Division by zero (Z): Division with a zero divisor * Overflow (O): When the operation result overflows * Underflow (U): When the operation result underflows * Inexact exception (I): When overflow, underflow, or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled. When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the corresponding bit in the FPU exception flag field remains unchanged. 3.5.2 FPU Exception Handling
FPU exception handling is initiated in the following cases: * FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No chance to occur in the SH2A-FPU) * Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation * Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor * Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result overflow * Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result underflow * Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation result
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Section 3 Floating-Point Unit (FPU)
These possibilities are shown in the individual instruction descriptions. All exception events that originate in the FPU are assigned as the same exception event. The meaning of an exception is determined by software by reading from FPSCR and interpreting the information it contains. If no bits are set in the FPU exception cause field of FPSCR when one or more of bits O, U, I, and V are set in the FPU exception enable field, this indicates that an actual exception source is not generated. Also, the destination register is not changed by any FPU exception handling operation. Except for the above, the FPU disables exception handling. In every processing, the bit corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the operation result. * Invalid operation (V): qNaN is generated as the result. * Division by zero (Z): Infinity with the same sign as the unrounded value is generated. * Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated. * Underflow (U): Zero with the same sign as the unrounded value is generated. * Inexact exception (I): An inexact result is generated.
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Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (I), a peripheral clock (P), and a bus clock (B). The CPG consists of a crystal oscillator, PLL circuits, and divider circuits.
4.1
Features
* Three clock operating modes The mode is selected from among the three clock operating modes by the selection of the following three conditions: the frequency-divisor in use, whether the PLLs are on or off, and whether the internal crystal resonator or the input on the external clock-signal line is used. * Three clocks generated independently An internal clock (I) for the CPU and cache; a peripheral clock (P) for the on-chip peripheral modules; a bus clock (B = CKIO) for the external bus interface. * Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control The clock can be stopped by sleep mode, software standby mode, and deep standby mode. Specific modules can also be stopped using the module standby function. For details on clock control in the power-down modes, see section 27, Power-Down Modes.
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Section 4 Clock Pulse Generator (CPG)
Figure 4.1 shows a block diagram of the clock pulse generator.
On-chip oscillator Divider x1 x1/2 x1/3 x1/4 x1/6 x1/8 x1/12
PLL circuit 1 (x1, 2, 3, 4, 6, 8) CKIO
Internal clock (I, Max. : 120 MHz (Regular specifications), 100 MHz (Wide-range specifications)) Bus clock (B = CKIO, Max. 60 MHz)
XTAL
Crystal oscillator
PLL circuit 2 (x2, 4)
EXTAL
Peripheral clock (P, Max. 40 MHz)
CPG control unit MD_CLK1 MD_CLK0
Clock frequency control circuit
Standby control circuit
FRQCR
STBCR
STBCR2
STBCR3
STBCR4
STBCR5
Bus interface
[Legend] FRQCR: STBCR: STBCR2: STBCR3: STBCR4: STBCR5:
Peripheral bus Frequency control register Standby control register Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5
Figure 4.1 Block Diagram of Clock Pulse Generator
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Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows: (1) PLL Circuit 1
PLL circuit 1 multiplies the input clock frequency from the CKIO pin by 1, 2, 3, 4, 6, or 8. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin. (2) PLL Circuit 2
PLL circuit 2 multiplies the input clock frequency from the crystal oscillator or EXTAL pin by 2 or 4. The multiplication rate is fixed according to the clock operating mode. The clock operating mode is specified by the MD_CLK1 and MD_CLK0 pins. For details on the clock operating mode, see table 4.2. Note that the settings of these pins cannot be changed during operation. If changed, the operation of this LSI cannot be guaranteed. (3) Crystal Oscillator
The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating mode. (4) Divider
Divider generates a clock signal at the operating frequency used by the internal or peripheral clock. The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register (FRQCR). (5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD_CLK1 and MD_CLK0 pins and the frequency control register (FRQCR). (6) Standby Control Circuit
The standby control circuit controls the states of the clock pulse generator and other modules during clock switching, or in sleep, software, and deep standby mode.
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Section 4 Clock Pulse Generator (CPG)
(7)
Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock (P). (8) Standby Control Register
The standby control register has bits for controlling the power-down modes. See section 27, Power-Down Modes, for more information.
4.2
Input/Output Pins
Table 4.1 lists the clock pulse generator pins and their functions. Table 4.1 Pin Configuration and Functions of the Clock Pulse Generator
Function (Clock Operating Modes 0 and 2) Sets the clock operating mode. Sets the clock operating mode. Connected to the crystal resonator. (Leave this pin open when the crystal resonator is not in use.) Connected to the crystal resonator or used to input an external clock. Clock output pin. Function (Clock Operating Mode 3) Sets the clock operating mode. Sets the clock operating mode. Leave this pin open.
Pin Name
Symbol
I/O Input Input Output
Mode control pins MD_CLK0 MD_CLK1 Crystal input/output pins (clock input pins) XTAL
EXTAL
Input
Pull-up this pin.
Clock input/output CKIO pin
I/O
Clock input pin.
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Section 4 Clock Pulse Generator (CPG)
4.3
Clock Operating Modes
Table 4.2 shows the relationship between the combinations of the mode control pins (MD_CLK1 and MD_CLK0) and the clock operating modes. Table 4.2 shows the usable frequency ranges in the clock operating modes. Table 4.2 Clock Operating Modes
Pin Values Mode MD_CLK1 0 2 3 0 1 1
MD_CLK0
Clock I/O Source EXTAL or crystal resonator EXTAL or crystal resonator CKIO Output CKIO CKIO
PLL Circuit 2 PLL Circuit 1 On/Off On/Off ON (x4) ON (x2) OFF
CKIO Frequency
0 0 1
ON (x1, 2, 3, 4) (EXTAL or crystal resonator) x4 ON (x1, 2, 3, 4, (EXTAL or crystal 6, 8) resonator) x2 ON (x1, 2, 3, 4, (CKIO) 6, 8)
* Mode 0 The frequency of the signal received from the EXTAL pin or crystal resonator is quadrupled by the PLL circuit 2 before it is supplied to the LSI as the clock signal. This enables to use the external clock of lower frequency. Either a crystal resonator with a frequency in the range from 10 to 15 MHz or an external signal in the same frequency range input on the EXTAL pin may be used. The frequency range of CKIO is from 40 to 60 MHz. * Mode 2 The frequency of the signal received from the EXTAL pin or crystal resonator is doubled by the PLL circuit 2 before it is supplied to the LSI as the clock signal. This enables to use the external clock of lower frequency. An external signal with a frequency in the range from 10 to 30 MHz or a crystal resonator with 10 to 20 MHz may be used. The frequency range of CKIO is from 20 to 60 MHz. * Mode 3 In mode 3, the CKIO pin functions as an input pin and draws an external clock signal. The PLL circuit 1 shapes its waveform and the setting of the frequency control register multiplies its frequency before the clock enters the LSI. Frequency between 20 to 60 MHz can be input to the CKIO pin. For reduced current and hence power consumption, pull up the EXTAL pin and open the XTAL pin when the LSI is used in mode 3.
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Section 4 Clock Pulse Generator (CPG)
Table 4.3
Relationship between Clock Operating Mode and Frequency Range
PLL Frequency Ratio of Internal Clock Frequencies
1 2
Clock Operating Mode 0 FRQCR Setting H'1000 H'1001 H'1002 H'1003 H'1004 H'1005 H'1006 H'1101 H'1103 H'1104 H'1105 H'1106 H'1111 H'1113 H'1114 H'1115 H'1116 H'1202 H'1204 H'1206 H'1222 H'1224 H'122C H'1226 H'122E PLL
Multiplier PLL
Selectable Frequency Range (MHz) Output Clock Input Clock* 10 10 to 15 10 to 15 10 to 15 10 to 15 10 to 15 10 to 15 10 10 to 15 10 to 15 10 to 15 10 to 15 10 10 to 15 10 to 15 10 to 15 10 to 15 10 10 10 10 10 10 to 15 10 10 to 15 (CKIO Pin)* 40 40 to 60 40 to 60 40 to 60 40 to 60 40 to 60 40 to 60 40 40 to 60 40 to 60 40 to 60 40 to 60 40 40 to 60 40 to 60 40 to 60 40 to 60 40 40 40 40 40 40 to 60 40 40 to 60
3
Internal Clock Bus Clock (I)* 40 40 to 60 40 to 60 40 to 60 40 to 60 40 to 60 40 to 60 80 80 to 120 80 to 120 80 to 120 80 to 120 40 40 to 60 40 to 60 40 to 60 40 to 60 120 120 120 120 120 40 to 60 40 40 to 60
3
Peripheral Clock (P)* 40 20 to 30 13.33 to 20 10 to 15 6.7 to 10 5 to 7.5 3.33 to 5 40 20 to 30 13.33 to 20 10 to 15 6.7 to 10 40 20 to 30 13.33 to 20 10 to 15 6.7 to 10 40 20 10 40 20 20 to 30 10 10 to 15
3
Circuit 1 Circuit 2 (I:B:P)* ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) 4:4:4 4:4:2 4:4:4/3 4:4:1 4:4:2/3 4:4:1/2 4:4:1/3 8:4:4 8:4:2 8:4:4/3 8:4:1 8:4:2/3 4:4:4 4:4:2 4:4:4/3 4:4:1 4:4:2/3 4:4:4 4:4:2 4:4:1 4:4:4 4:4:2 4:4:2 4:4:1 4:4:1
(B)* 40
3
40 to 60 40 to 60 40 to 60 40 to 60 40 to 60 40 to 60 40 40 to 60 40 to 60 40 to 60 40 to 60 40 40 to 60 40 to 60 40 to 60 40 to 60 40 40 40 40 40 40 to 60 40 40 to 60
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Section 4 Clock Pulse Generator (CPG)
PLL Frequency Clock Operating Mode 0 FRQCR Setting H'1313 H'1315 H'1316 H'1333 H'1335 H'1336 2 H'1000 H'1001 H'1002 H'1003 H'1004 H'1005 H'1006 H'1101 H'1103 H'1104 H'1105 H'1106 H'1111 H'1113 H'1114 H'1115 H'1116 H'1202 H'120C H'120E H'1206 H'1222 H'1224 H'122C PLL Multiplier PLL
Ratio of Internal Clock Frequencies
1 2
Selectable Frequency Range (MHz) Output Clock Input Clock* 10 10 to 12.5 10 to 12.5 10 10 to 12.5 10 to 12.5 10 to 20 10 to 30 10 to 30 10 to 30 10 to 30 10 to 30 10 to 30 10 to 20 10 to 30 10 to 30 10 to 30 10 to 30 10 to 20 10 to 30 10 to 30 10 to 30 10 to 30 10 to 20 20 20 10 to 20 10 to 20 10 to 20 20 to 30 (CKIO Pin)* 40 40 to 50 40 to 50 40 40 to 50 40 to 50 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 40 40 20 to 40 20 to 40 20 to 40 40 to 60
3
Internal Clock Bus Clock (I)* 80 80 to 100 80 to 100 40 40 to 50 40 to 50 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 40 to 80 40 to 120 40 to 120 40 to 120 40 to 120 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 60 to 120 120 120 60 to 120 20 to 40 20 to 40 40 to 60
3
Peripheral Clock (P)* 40 20 to 25 13.33 to 16.67 40 20 to 25 13.33 to 16.67 20 to 40 10 to 30 6.67 to 20 5 to 15 3.33 to 10 2.5 to 7.5 1.67 to 5 20 to 40 10 to 30 6.67 to 20 5 to 15 3.3 to 10 20 to 40 10 to 30 6.67 to 20 5 to 15 3.3 to 10 20 to 40 20 10 5 to 10 20 to 40 10 to 20 20 to 30
3
Circuit 1 Circuit 2 (I:B:P)* ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) 8:4:4 8:4:2 8:4:4/3 4:4:4 4:4:2 4:4:4/3 2:2:2 2:2:1 2:2:2/3 2:2:1/2 2:2:1/3 2:2:1/4 2:2:1/6 4:2:2 4:2:1 4:2:2/3 4:2:1/2 4:2:1/3 2:2:2 2:2:1 2:2:2/3 2:2:1/2 2:2:1/3 6:2:2 6:2:1 6:2:1/2 6:2:1/2 2:2:2 2:2:1 2:2:1
(B)* 40
3
40 to 50 40 to 50 40 40 to 50 40 to 50 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 40 40 20 to 40 20 to 40 20 to 40 40 to 60
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Section 4 Clock Pulse Generator (CPG)
PLL Frequency Multiplier Clock Operating Mode 2 FRQCR Setting H'1226 H'1303 H'1305 H'1306 H'1313 H'1315 H'1316 H'1333 H'1335 H'1336 H'1404 H'1406 H'1414 H'1416 H'1424 H'1426 H'1444 H'1446 H'1515 H'1535 H'1555 3 H'1000 H'1001 H'1002 H'1003 H'1004 H'1005 H'1006 PLL PLL Ratio of Internal Clock Frequencies
1
Selectable Frequency Range (MHz) Output Clock Input Clock* 10 to 20 10 to 15 10 to 15 10 to 15 10 to 20 10 to 25 10 to 25 10 to 20 10 to 25 10 to 25 10 10 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 16.67 10 to 12.5 10 to 12.5 10 to 12.5 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60
2
Internal Clock Bus Clock (I)*
3
Peripheral Clock (P)* 5 to 10 20 to 30 10 to 15 6.67 to 10 20 to 40 10 to 25 6.67 to 16.67 20 to 40 10 to 25 6.67 to 16.67 20 10 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 25 20 to 25 20 to 25 20 to 40 10 to 30 6.67 to 20 5 to 15 3.33 to 10 2.5 to 7.5 1.67 to 5
3
Circuit 1 Circuit 2 (I:B:P)* ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x8) ON (x8) ON (x8) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x1) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) OFF OFF OFF OFF OFF OFF OFF 2:2:1/2 8:2:2 8:2:1 8:2:2/3 4:2:2 4:2:1 4:2:2/3 2:2:2 2:2:1 2:2:2/3 12:2:2 12:2:1 6:2:2 6:2:1 4:2:2 4:2:1 2:2:2 2:2:1 8:2:2 4:2:2 2:2:2 1:1:1 1:1:1/2 1:1:1/3 1:1:1/4 1:1:1/6 1:1:1/8 1:1:1/12
(CKIO Pin)* 20 to 40 20 to 30 20 to 30 20 to 30 20 to 40 20 to 50 20 to 50 20 to 40 20 to 50 20 to 50 20 20 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 25 20 to 25 20 to 25
3
(B)*
3
20 to 40 80 to 120 80 to 120 80 to 120 40 to 80 40 to 100 40 to 100 20 to 40 20 to 50 20 to 50 120 120 60 to 100 60 to 100 40 to 66.67 40 to 66.67 20 to 33.33 20 to 33.33 80 to 100 40 to 50 20 to 25 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60
20 to 40 20 to 30 20 to 30 20 to 30 20 to 40 20 to 50 20 to 50 20 to 40 20 to 50 20 to 50 20 20 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 25 20 to 25 20 to 25 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60 20 to 60
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Section 4 Clock Pulse Generator (CPG)
PLL Frequency Multiplier Clock Operating Mode 3 FRQCR Setting H'1101 H'1103 H'1104 H'1105 H'1106 H'1111 H'1113 H'1114 H'1115 H'1116 H'1202 H'120C H'1206 H'1222 H'1224 H'122C H'1226 H'122E H'1303 H'1305 H'1306 H'1313 H'1315 H'1316 H'1333 H'1335 H'1336 PLL PLL Ratio of Internal Clock Frequencies
1
Selectable Frequency Range (MHz) Output Clock Input Clock* 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 40 20 to 40 20 to 40 20 to 40 20 to 60 20 to 40 40 to 60 20 to 30 20 to 30 20 to 30 20 to 40 20 to 50 20 to 50 20 to 40 20 to 50 20 to 50
2
Internal Clock Bus Clock (I)*
3
Peripheral Clock (P)* 20 to 40 10 to 30 6.67 to 20 5 to 15 3.33 to 10 20 to 40 10 to 30 6.67 to 20 5 to 15 3.33 to 10 20 to 40 20 5 to 10 20 to 40 10 to 20 20 to 30 5 to 10 10 to 15 20 to 30 10 to 15 6.67 to 10 20 to 40 10 to 25 6.67 to 16.67 20 to 40 10 to 25 6.67 to 16.67
3
Circuit 1 Circuit 2 (I:B:P)* ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x2) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x3) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) ON (x4) OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 2:1:1 2:1:1/2 2:1:1/3 2:1:1/4 2:1:1/6 1:1:1 1:1:1/2 1:1:1/3 1:1:1/4 1:1:1/6 3:1:1 3:1:1/2 3:1:1/4 1:1:1 1:1:1/2 1:1:1/2 1:1:1/4 1:1:1/4 4:1:1 4:1:1/2 4:1:1/3 2:1:1 2:1:1/2 2:1:1/3 1:1:1 1:1:1/2 1:1:1/3
(CKIO Pin)*
3
(B)*
3
40 to 80 40 to 120 40 to 120 40 to 120 40 to 120 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 60 to 120 120 60 to 120 20 to 40 20 to 40 40 to 60 20 to 40 40 to 60 80 to 120 80 to 120 80 to 120 40 to 80 40 to 100 40 to 100 20 to 40 20 to 50 20 to 50
20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 20 to 60 20 to 60 20 to 60 20 to 60 20 to 40 40 20 to 40 20 to 40 20 to 40 40 to 60 20 to 40 40 to 60 20 to 30 20 to 30 20 to 30 20 to 40 20 to 50 20 to 50 20 to 40 20 to 50 20 to 50
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Section 4 Clock Pulse Generator (CPG)
PLL Frequency Multiplier Clock Operating Mode 3 FRQCR Setting H'1404 H'1406 H'1414 H'1416 H'1424 H'1426 H'1444 H'1446 H'1515 H'1535 H'1555 PLL PLL Ratio of Internal Clock Frequencies
1
Selectable Frequency Range (MHz) Output Clock Input Clock* 20 20 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 25 20 to 25 20 to 25
2
Internal Clock Bus Clock (I)* 120 120 60 to 100 60 to 100 40 to 66.67 40 to 66.67 20 to 33.33 20 to 33.33 80 to 100 40 to 50 20 to 25
3
Peripheral Clock (P)* 20 10 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 33.33 10 to 16.67 20 to 25 20 to 25 20 to 25
3
Circuit 1 Circuit 2 (I:B:P)* ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x6) ON (x8) ON (x8) ON (x8) OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 6:1:1 6:1:1/2 3:1:1 3:1:1/2 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1
(CKIO Pin)*
3
(B)* 20 20
3
20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 33.33 20 to 25 20 to 25 20 to 25
Notes:
Caution:
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1. 2. In modes 0 and 2, the frequency of the clock input from the EXTAL pin or the frequency of the crystal resonator. In mode 3, the frequency of the clock input from the CKIO pin. 3. Use an internal clock (I) frequency of 120 MHz or lower for the regular specifications and 100 MHz or lower for the wide-range specifications. Use a CKIO pin or bus clock (B) frequency of 60 MHz or lower. P must be from 5 through 40 MHz. 1. The frequency of the internal clock is the frequency of the signal input to the CKIO pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Do not set a frequency for the internal clock below the frequency of the signal on the CKIO pin. 2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the divider's divisor. Set the frequency of the peripheral clock to 40 MHz or below. In addition, do not set a higher frequency for the internal clock than the frequency on the CKIO pin. 3. The frequency multiplier of PLL circuit 1 can be selected as x1, x2, x3, x4, x6, or x8. The divisor of the divider can be selected as x1, x1/2, x1/3, x1/4, x1/6, x1/8, or x1/12. The settings are made in the frequency-control register (FRQCR). 4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL circuit 1 is not more than 200 MHz.
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Section 4 Clock Pulse Generator (CPG)
4.4
Register Descriptions
The clock pulse generator has the following registers. Table 4.4 Register Configuration
Abbreviation R/W FRQCR CKIOCR R/W R/W Initial Value Address H'1003 H'10/H'00 Access Size
Register Name Frequency control register CKIO control register
H'FFFE0010 16 H'FFFE3894 8, 16, 32
4.4.1
Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and peripheral clock (P). Only word access can be used on FRQCR. FRQCR is initialized to H'1003 only by a power-on reset or in deep standby mode. FRQCR retains its previous value by a manual reset or in software standby mode. The previous value is also retained when an internal reset is triggered by an overflow of the WDT.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12
CKOEN
11 -- 0 R
10
9 STC[2:0]
8
7 --
6
5 IFC[2:0]
4
3 RNGS
2
1 PFC[2:0]
0
1 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
Bit 15 to 13
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 4 Clock Pulse Generator (CPG)
Bit 12
Bit Name CKOEN
Initial Value 1
R/W R/W
Description Clock Output Enable Specifies whether a clock is output from the CKIO pin, or whether the CKIO pin is placed in the levelfixed state during software standby mode or cancellation of software standby mode. If this bit is cleared to 0, the CKIO pin is fixed at low during software standby mode or cancellation of software standby mode. Therefore, the malfunction of an external circuit because of an unstable CKIO clock during cancellation of software standby mode can be prevented. In clock operating mode 3, the CKIO pin functions as an input regardless of this bit value. 0: The CKIO pin is fixed to the low level during software standby mode or cancellation of software standby mode. 1: Clock is output from CKIO pin (low level in software standby mode).
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10 to 8
STC[2:0]
000
R/W
Frequency Multiplication Ratio of PLL Circuit 1 000: x 1 time 001: x 2 times 010: x 3 times 011: x 4 times 100: x 6 times 101: x 8 times
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 4 Clock Pulse Generator (CPG)
Bit 6 to 4
Bit Name IFC[2:0]
Initial Value 000
R/W R/W
Description Internal Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1. 000: x 1 time 001: x 1/2 time 010: x 1/3 time 011: x 1/4 time 100: x 1/6 time 101: x 1/8 time
3
RNGS
0
R/W
Output Range Select for PLL Circuit 1 When the multiplication ratio for the PLL circuit 1 is specified to x 3, set this bit according to the output frequency of the PLL circuit 1. 0: Low frequency mode (Output frequency of the PLL circuit 1 is equal to or smaller than 120 MHz.) 1: High frequency mode (Multiplication ratio for the PLL circuit 1 is specified to x 3 and its output frequency exceeds 120 MHz.)
2 to 0
PFC[2:0]
011
R/W
Peripheral Clock Frequency Division Ratio These bits specify the frequency division ratio of the peripheral clock with respect to the output frequency of PLL circuit 1. 000: x 1 time 001: x 1/2 time 010: x 1/3 time 011: x 1/4 time 100: x 1/6 time 101: x 1/8 time 110: x 1/12 time
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Section 4 Clock Pulse Generator (CPG)
4.4.2
CKIO Control Register (CKIOCR)
CKIOCR is an 8-bit readable/writable register used to control output of the CKIO pin. When this LSI is started in clock operating mode 3, writing 1 to this register is invalid. When this LSI is started in clock operating mode 3, CKIOCR is initialized to H'00 by a power-on reset caused by the RES pin or in deep standby mode. When this LSI is started in clock operating mode 0 or 2, CKIOCR is initialized to H'01 by a power-on reset caused by the RES pin or in deep standby mode. This register is not initialized by an internal reset triggered by an overflow of the WDT, a manual reset, in sleep mode, or in software standby mode.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0
CKIO OE
0/1* R/W
Bit 7 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
CKIOOE
0/1*
R/W
CKIO Output Enable Enables output of the CKIO pin. 0: Output from CKIO is not enabled. 1: Output from CKIO is enabled.
Note:
*
The initial value depends on the clock operating mode of the LSI.
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Section 4 Clock Pulse Generator (CPG)
4.5
Changing the Frequency
The frequency of the internal clock (I) and peripheral clock (P) can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these are controlled by software through the frequency control register (FRQCR). The methods are described below. 4.5.1 Changing the Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR.TME = 0: WDT stops WTCSR.CKS[2:0]: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and PFC[2:0] bits. 4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral clocks both stop and the WDT is supplied with the clock. The clock will continue to be output at the CKIO pin. This state is the same as software standby mode. Whether or not registers are initialized depends on the module. For details, see section 27, Power-Down Modes. 5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins operating again. The WDT stops after it overflows.
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Section 4 Clock Pulse Generator (CPG)
4.5.2
Changing the Division Ratio
Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not. 1. In the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011. 2. Set the desired value in the IFC[2:0] and PFC[2:0] bits. The values that can be set are limited by the clock operating mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, this LSI will malfunction. 3. After the register bits (IFC[2:0] and PFC[2:0]) have been set, the clock is supplied of the new division ratio. Note: When executing the SLEEP instruction after the frequency has been changed, be sure to read the frequency control register (FRQCR) three times before executing the SLEEP instruction.
4.6
4.6.1
Notes on Board Design
Note on Inputting External Clock
Figure 4.2 is an example of connecting the external clock input. When putting the XTAL pin in open state, make sure the parasitic capacitance is less than or equal to 10 pF. To stably input the external clock with enough PLL stabilizing time at power on or releasing the standby, wait longer than the oscillation stabilizing time.
EXTAL
External clock input
XTAL
Open state
Example of connection with XTAL pin open
Figure 4.2 Example of Connecting External Clock For details on input conditions of the external clock, see section 31.3.1, Clock Timing.
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Section 4 Clock Pulse Generator (CPG)
4.6.2
Note on Using Crystal Resonator
Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components.
Signal lines prohibited Reference value CL1 = 10 to 22 pF CL2 = 10 to 22 pF
CL1
CL2
EXTAL
XTAL
Note: The values for CL1 and CL2 should be determined after consultation with the crystal resonator manufacturer.
This LSI
Figure 4.3 Note on Using Crystal Resonator 4.6.3 Note on Resonator
Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the parameters for the oscillation circuit will depend on the floating capacitance of the resonator and the user board, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin.
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Section 4 Clock Pulse Generator (CPG)
4.6.4
Note on Using a PLL Oscillation Circuit
In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. In clock operating mode 3, the EXTAL pin is pulled up and the XTAL pin is left open. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pin Vcc and the digital power supply pins VccR and PVcc should not supply the same resources on the board if at all possible.
Signal lines prohibited
Power supply
PLLVcc
Vcc
PLLVss
Vss
Figure 4.4 Note on Using PLL Oscillation Circuit 4.6.5 Note on Changing the Multiplication Rate
If the multiplication rate is changed by the frequency control register (FRQCR) during transfer by the DMAC, the DMAC stops its operation without waiting for the completion of the transfer. Thus, the DMA transfer is not guaranteed. Therefore, when changing the multiplication rate with the frequency control register (FRQCR), wait for the completion of the DMA transfer or stop the DMA transfer to change the setting of the frequency control register (FRQCR).
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Section 5 Exception Handling
Section 5 Exception Handling
5.1
5.1.1
Overview
Types of Exception Handling and Priority
Exception handling is started by sources, such as resets, address errors, bus errors, register bank errors, interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling sources occur at once, they are processed according to the priority shown. Table 5.1
Type Reset
Types of Exception Handling and Priority Order
Exception Handling Power-on reset Manual reset Priority High
Address error Bus error
CPU address error Bus error
Instructions FPU exception Integer division exception (division by zero) Integer division exception (overflow) Register bank error Interrupts Bank underflow Bank overflow NMI User break H-UDI IRQ PINT Low
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Section 5 Exception Handling
Type Interrupts
Exception Handling On-chip peripheral modules A/D converter (ADC) CD-ROM decoder (ROM-DEC) Multifunction timer pulse unit 2 (MTU2) Realtime clock (RTC) Watchdog timer (WDT) IC bus interface 3 (IIC3) Direct memory access controller (DMAC) Serial communication interface with FIFO (SCIF) Controller area network (RCAN-ET) IEBusTM controller (IEB) Serial sound interface (SSI) 8-bit timer (TMR)
Priority High
Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed branch instruction*1, instructions that rewrite the PC*2, 32-bit 3 instructions* , RESBANK instruction, DIVS instruction, and DIVU instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N. 3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
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Section 5 Exception Handling
5.1.2
Exception Handling Operations
The exception handling sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2
Exception Reset
Timing of Exception Source Detection and Start of Exception Handling
Source Power-on reset Timing of Source Detection and Start of Handling Starts when the RES pin changes from low to high, when the H-UDI reset negate command is set after the H-UDI reset assert command has been set, or when the WDT overflows. Starts when the MRES pin changes from low to high or when the WDT overflows. Detected when instruction is decoded and starts when the previous executing instruction finishes executing.
Manual reset Address error Bus error Interrupts Register bank Bank underflow error Bank overflow
Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. In the state where saving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except immediately after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed immediately after a delayed branch instruction (delay slot), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value (H'80000000) by -1. Exception handling starts triggered by disabled operation exception of floating-point operation instruction (IEEE754 standard), division exception by zero, overflow, underflow, or imprecise exception. Setting the QIS bit in FPSCR or inputting qNaN as well as as the floating-point operation instruction source also starts exception handling.
Instructions
Trap instruction General illegal instructions Slot illegal instructions
Integer division instructions Floating-point operation instruction
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Section 5 Exception Handling
When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Handling Vector Table, for more information. The vector base register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the interrupt controller (INTC) is also initialized to 0. FPSCR is initialized to H'00040001 by a power-on reset. The program begins running from the PC address fetched from the exception handling vector table. (2) Exception Handling Triggered by Address Errors, Bus Errors, Register Bank Errors, Interrupts, and Instructions
SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling other than the NMI or user break, with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector number of the interrupt exception handling to be executed are saved to the register banks. In the case of exception handling due to an address error, bus error, register bank error, NMI interrupt, user break interrupt, or instruction, saving to a register bank is not performed. When saving is performed to all register banks, automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception will be generated. In the case of interrupt exception handling, the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or instruction, the I3 to I0 bits are not affected. The start address is then fetched from the exception handling vector table and the program begins running from that address.
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Section 5 Exception Handling
5.1.3
Exception Handling Vector Table
Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception handling, the start addresses of the exception service routines are fetched from the exception handling vector table, which is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Handling Vector Table
Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) CPU address error Bus error Interrupts FPU exception H-UDI Bank overflow Bank underflow Integer division exception (division by zero) Integer division exception (overflow) NMI User break 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 H'00000038 to H'0000003B H'0000003C to H'0000003F H'00000040 to H'00000043 H'00000044 to H'00000047 H'00000048 to H'0000004B
Exception Sources Power-on reset
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Section 5 Exception Handling
Exception Sources (Reserved by system)
Vector Numbers 19 : 31
Vector Table Address Offset H'0000004C to H'0000004F : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF H'00000100 to H'00000103 : H'000003FC to H'000003FF
Trap instruction (user vector)
32 : 63
External interrupts (IRQ, PINT), on-chip peripheral module interrupts*
64 : 255
Note:
*
The vector numbers and vector table address offsets for each external interrupt and onchip peripheral module interrupt are given in table 6.4 in section 6, Interrupt Controller (INTC).
Table 5.4
Calculating Exception Handling Vector Table Addresses
Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4
Exception Source Resets Address errors, bus errors, register bank errors, interrupts, instructions
Notes: 1. Vector table address offset: See table 5.3. 2. Vector number: See table 5.3.
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Section 5 Exception Handling
5.2
5.2.1
Resets
Input/Output Pins
Table 5.5 shows the configuration of pins relating to the resets. Table 5.5
Pin Name Power-on reset Manual reset
Pin Configuration
Symbol RES MRES I/O Input Input Function When this pin is driven low, this LSI shifts to the power-on reset processing When this pin is driven low, this LSI shifts to the manual reset processing.
5.2.2
Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of resets, power-on and manual. As shown in table 5.6, the CPU state is initialized by both a power-on reset and a manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip peripheral module registers except a few registers are initialized by a power-on reset, but not by a manual reset. Table 5.6 Reset States
Conditions for Transition to Reset State WDT H-UDI Command MRES Overflow -- -- -- -- Power-on reset Internal States On-Chip Peripheral Modules, I/O Port Initialized* Initialized*
1 1
Type Power-on reset
RES Low High High
CPU Initialized Initialized Initialized
WRCSR of WDT, FRQCR of CPG Initialized Initialized Not initialized
H-UDI reset assert -- command is set Command other than H-UDI reset assert is set --
Initialized*
1
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Section 5 Exception Handling
Conditions for Transition to Reset State WDT H-UDI Command MRES Overflow Command other than H-UDI reset assert is set Command other than H-UDI reset assert is set Low --
Internal States On-Chip Peripheral Modules, I/O Port Not initialized*
2
Type Manual reset
RES High
CPU Initialized
WRCSR of WDT, FRQCR of CPG Not initialized
High
High
Manual reset
Initialized
Not initialized*
2
Not initialized
Notes: 1. Some registers are excluded. For details, see section 30.3, Register States in Each Operating Mode. 2. The BN bit in IBNR of the INTC is initialized.
5.2.3 (1)
Power-On Reset Power-On Reset by Means of RES Pin
When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc when the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip peripheral module registers are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset state. In the power-on reset state, power-on reset exception handling starts when the RES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of the INTC is also initialized to 0. FPSCR is initialized to H'00040001. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on.
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Section 5 Exception Handling
(2)
Power-On Reset by Means of H-UDI Reset Assert Command
When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of an H-UDI reset assert command is equivalent to power-on reset by means of the RES pin. Setting the H-UDI reset negate command cancels the power-on reset state. The time required between an H-UDI reset assert command and H-UDI reset negate command is the same as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state generated by an H-UDI reset assert command, setting the H-UDI reset negate command starts power-on reset exception handling. The CPU operates in the same way as when a power-on reset was caused by the RES pin. (3) Power-On Reset Initiated by WDT
When a setting is made for a power-on reset to be generated in the WDT's watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal generated by the WDT. If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the WDT, the CPU operates in the same way as when a poweron reset was caused by the RES pin.
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Section 5 Exception Handling
5.2.4 (1)
Manual Reset Manual Reset by Means of MRES Pin
When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without fail, the MRES pin should be kept at the low level for at least 20-tcyc. In the manual reset state, the CPU's internal state is initialized, but all the on-chip peripheral module registers are not initialized. In the manual reset state, manual reset exception handling starts when the MRES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. (2) Manual Reset Initiated by WDT
When a setting is made for a manual reset to be generated in the WDT's watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the manual reset state. When manual reset exception processing is started by the WDT, the CPU operates in the same way as when a manual reset was caused by the MRES pin. (3) Notes at a Manual Reset
When a manual reset is generated, the bus cycle is retained. Thus, manual reset exception handling will be deferred until the CPU acquires the bus mastership. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the fixed internal manual reset interval cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception handling is not executed. The CPU and the BN bit in IBNR of the INTC are initialized by a manual reset. The FPU and other modules are not initialized.
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Section 5 Exception Handling
5.3
5.3.1
Address Errors
Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.7. Table 5.7 Bus Cycles and Address Errors
Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from area other than H'F0000000 to H'F5FFFFFFF in cache 1 address array space* Instruction fetched from H'F0000000 to H'F5FFFFFFF in cache address array 1 space* Data read/write CPU Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space*2 Longword data accessed in 16-bit onchip peripheral module space*2 Longword data accessed in 8-bit on-chip peripheral module space*2 Address Errors None (normal) Address error occurs None (normal)
Address error occurs
None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) None (normal)
Notes: 1. For details on cache address array space, see section 8, Cache. 2. For details on peripheral module space, see section 9, Bus State Controller (BSC).
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Section 5 Exception Handling
5.3.2
Address Error Exception Handling
When an address error occurs, address error exception handling starts after the bus cycle in which the address error occurred ends and execution of the instruction being executed completes. The CPU operates as follows. 1. The exception service routine start address which corresponds to the address error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.
5.4
5.4.1
Bus Error
Bus Error Generation Source
In bus monitor, notification of bus error occurrence to the CPU can be set. The notification is generated when incorrect address access or bus timeout is detected. For details, see section 10, Bus Monitor. 5.4.2 Bus Error Exception Handling
When a bus error occurs, bus error exception handling starts after the bus cycle in which the bus error occurred ends and execution of the instruction being executed completes. The CPU operates as follows. 1. The exception service routine start address which corresponds to the bus error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.
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Section 5 Exception Handling
5.5
5.5.1 (1)
Register Bank Errors
Register Bank Error Sources Bank Overflow
In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. (2) Bank Underflow
Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving has not been performed to register banks. 5.5.2 Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a bank overflow, and the start address of the executed RESBANK instruction for a bank underflow. To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.
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Section 5 Exception Handling
5.6
5.6.1
Interrupts
Interrupt Sources
Table 5.8 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules. Table 5.8
Type NMI User break H-UDI IRQ PINT On-chip peripheral module
Interrupt Sources
Request Source NMI pin (external input) User break controller (UBC) User debugging interface (H-UDI) IRQ0 to IRQ7 pins (external input) PINT0 to PINT7 pins (external input) A/D converter (ADC) CD-ROM decoder (ROM-DEC) Multifunction timer pulse unit 2 (MTU2) Realtime clock (RTC) Watchdog timer (WDT) IC bus interface 3 (IIC3) Direct memory access controller (DMAC) Serial communication interface with FIFO (SCIF) Controller area network (RCAN-ET) IEBus controller (IEB) Serial sound interface (SSI) 8-bit timer (TMR)
TM
Number of Sources 1 1 1 8 8 1 6 28 3 1 15 9 32 2 1 2 6
Each interrupt source is allocated a different vector number and vector table offset. See table 6.4 in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table address offsets.
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Section 5 Exception Handling
5.6.2
Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16) of the INTC as shown in table 5.9. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to IPR16), for details of IPR01, IPR02, and IPR05 to IPR16. Table 5.9
Type NMI User break H-UDI IRQ PINT On-chip peripheral module 0 to 15
Interrupt Priority Order
Priority Level 16 15 15 0 to 15 Comment Fixed priority level. Cannot be masked Fixed priority level Fixed priority level Set with interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16) Set with interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16)
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Section 5 Exception Handling
5.6.3
Interrupt Exception Handling
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR). When an interrupt is accepted, interrupt exception handling begins. In interrupt exception handling, the CPU fetches the exception service routine start address which corresponds to the accepted interrupt from the exception handling vector table, and saves SR and the program counter (PC) to the stack. In the case of interrupt exception handling other than the NMI or user break, with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector number of the interrupt exception handling to be executed are saved in the register banks. In the case of exception handling due to an address error, bus error, NMI interrupt, user break interrupt, or instruction, saving is not performed to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If the interrupt controller is set to accept register bank overflow exceptions (the BOVE bit in IBNR of INTC is set to 1), a register bank overflow exception will occur. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address of the interrupt exception service routine fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. See section 6.6, Operation, for further details of interrupt exception handling.
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Section 5 Exception Handling
5.7
5.7.1
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, and integer division exceptions, as shown in table 5.10. Table 5.10 Types of Exceptions Triggered by Instructions
Type Trap instruction Slot illegal instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. Comment
General illegal instructions Integer division exceptions Floating-point operation instruction
Undefined code anywhere besides in a delay slot Division by zero Negative maximum value / (-1) Instructions that cause disabled operation exception defined by IEEE754 standard or division exception by zero. Instructions that could cause overflow, underflow, or imprecise exception. DIVU, DIVS DIVS FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, FSQRT
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Section 5 Exception Handling
5.7.2
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 5.7.3 Slot Illegal Instructions
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates as follows: 1. The exception service routine start address is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code, the instruction that rewrites the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 5.7.4 General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction (delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot illegal instructions, however, the program counter value stored is the start address of the undefined code.
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Section 5 Exception Handling
5.7.5
Integer Division Instructions
When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception are DIVU and DIVS. The only source instruction of overflow exception is DIVS, and overflow exception occurs only when the negative maximum value is divided by -1. The CPU operates as follows: 1. The exception service routine start address which corresponds to the integer division instruction exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the integer division instruction at which the exception occurred. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 5.7.6 Floating-point Operation Instruction
When the bits V, Z, O, U, or I in the enabled field of the floating point status/control register (FPSCR) are set, a FPU exception is generated. This means that instructions that cause disabled operation exception defined by IEEE754 standard, division exception by zero, overflow (possible instruction), underflow (possible instruction), or imprecise exception (possible instruction) are yielded. Floating-point operation instructions that can be exception sources are FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and FSQRT. FPU exceptions occur only when the said enabled bits are set. When the FPU detects exception sources, the FPU operation stops and exception occurrence is notified to the CPU. The CPU starts the exception handling as follows: 1. The exception service routine start address which corresponds to the FPU exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch.
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Section 5 Exception Handling
The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an FPU exception has been accepted, and remains set until explicitly cleared by the user through an instruction. The FPU exception source field (Cause) of FPSCR changes each time an FPU instruction is executed. When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in FPSCR is also set, FPU exception is generated when qNAN or is input to a floating point operation instruction source.
5.8
When Exception Sources Are Not Accepted
When an address error, bus error, FPU exception, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.11. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source Address Error Not accepted FPU Exception Register Bank Error (Overflow)
Point of Occurrence Immediately after a delayed branch instruction* Note: *
Bus Error
Interrupt
Not accepted Not accepted Not accepted Not accepted
Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF.
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Section 5 Exception Handling
5.9
Stack Status after Exception Handling Ends
The status of the stack after exception handling ends is as shown in table 5.12. Table 5.12 Stack Status After Exception Handling Ends
Exception Type Address error
SP
Stack Status
Address of instruction after executed instruction SR
32 bits
32 bits
Interrupt
SP
Address of instruction after executed instruction SR
32 bits
32 bits
Bus error
SP
Address of instruction after executed instruction SR
32 bits
32 bits
FPU exception
SP
Address of instruction after executed instruction SR
32 bits
32 bits
Register bank error (overflow)
SP
Address of instruction after executed instruction SR
32 bits
32 bits
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Section 5 Exception Handling
Exception Type Register bank error (underflow)
Stack Status
SP
Start address of relevant RESBANK instruction SR
32 bits
32 bits
Trap instruction
SP
Address of instruction after TRAPA instruction SR
32 bits
32 bits
Slot illegal instruction
SP
Jump destination address of delayed branch instruction SR
32 bits
32 bits
General illegal instruction
SP
Start address of general illegal instruction SR
32 bits 32 bits
Integer division instruction
SP
Start address of relevant integer division instruction SR
32 bits
32 bits
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Section 5 Exception Handling
5.10
5.10.1
Usage Notes
Value of Stack Pointer (SP)
The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 5.10.2 Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 5.10.3 Address Errors Caused by Stacking of Address Error Exception Handling
When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.) and address error exception handling will start up as soon as the first exception handling is ended. Address errors will then also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. During the stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined.
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Section 5 Exception Handling
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Section 6 Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority.
6.1
Features
* 16 levels of interrupt priority can be set By setting the 14 interrupt priority registers, the priorities of the IRQ, PINT, and on-chip peripheral module interrupts can be set to one of 16 levels for each source. * NMI noise canceller function This controller provides an NMI input level bit that indicates the NMI pin state. The interrupt exception service routine can verify the pin state by reading this bit and use the information to implement a noise canceling function. * Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. Figure 6.1 shows a block diagram of the INTC.
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Section 6 Interrupt Controller (INTC)
NMI IRQ7 to IRQ0 PINT7 to PINT0 UBC H-UDI ADC ROM-DEC MTU2 RTC WDT IIC3 DMAC SCIF RCAN-ET IEB SSI TMR (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Input control
Comparator Priority identifier
Interrupt request SR I3 I2 I1 I0 CPU
ICR0 ICR2 PINTER IBCR
ICR1 IRQRR PIRR IBNR IPR IPR01, IPR02, IPR05 to IPR16
Module bus INTC User break controller User debugging interface A/D converter CD-ROM decoder Multi-function timer pulse unit 2 Realtime clock Watchdog timer I2C bus interface 3 Direct memory access controller Serial communication interface with FIFO Controller area network IEBusTM controller Serial sound interface
Bus interface
[Legend] UBC: H-UDI: ADC: ROM-DEC: MTU2: RTC: WDT: IIC3: DMAC: SCIF: RCAN-ET: IEB: SSI:
8-bit timer TMR: Interrupt control register 0 ICR0: Interrupt control register 1 ICR1: Interrupt control register 2 ICR2: IRQRR: IRQ interrupt request register PINTER: PINT interrupt enable register PINT interrupt request register PIRR: Bank control register IBCR: Bank number register IBNR: IPR01, IPR02, IPR05 to IPR16: Interrupt priority registers 01, 02, 05 to 16
Figure 6.1 Block Diagram of INTC
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Peripheral bus
Section 6 Interrupt Controller (INTC)
6.2
Input/Output Pins
Table 6.1 shows the pin configuration of the INTC. Table 6.1
Pin Name Nonmaskable interrupt input pin Interrupt request input pins
Pin Configuration
Symbol NMI IRQ7 to IRQ0 PINT7 to PINT0 I/O Input Input Input Function Input of nonmaskable interrupt request signal Input of maskable interrupt request signals
6.3
Register Descriptions
The INTC has the following registers. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 6.2 Register Configuration
Abbreviation R/W ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR01 IPR02 IPR05 IPR06 IPR07 R/W R/W R/W R/(W)* R/W R R/W R/W R/W R/W R/W R/W R/W
2
Register Name Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register PINT interrupt enable register PINT interrupt request register Bank control register Bank number register Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07
Initial Value *
1
Address H'FFFD9400 H'FFFD9402 H'FFFD9404 H'FFFD9406 H'FFFD9408 H'FFFD940A H'FFFD940C H'FFFD940E H'FFFD9418 H'FFFD941A H'FFFD9420 H'FFFD9800 H'FFFD9802
Access Size 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16 16, 32 16
H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000
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Section 6 Interrupt Controller (INTC)
Register Name Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 Interrupt priority register 15 Interrupt priority register 16 DMA transfer request enable register 0 DMA transfer request enable register 1 DMA transfer request enable register 2 DMA transfer request enable register 3
Abbreviation R/W IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 IPR15 IPR16 DREQER0 DREQER1 DREQER2 DREQER3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'00 H'00 H'00 H'00
Address H'FFFD9804 H'FFFD9806 H'FFFD9808 H'FFFD980A H'FFFD980C H'FFFD980E H'FFFD9810 H'FFFD9812 H'FFFD9814 H'FFFF1600 H'FFFF1601 H'FFFF1602 H'FFFF1603
Access Size 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16 8, 16, 32 8 8, 16 8
Notes: 1. When the NMI pin is high, becomes H'8000; when low, becomes H'0000. 2. Only 0 can be written after reading 1, to clear the flag.
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Section 6 Interrupt Controller (INTC)
6.3.1
Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to IPR16)
IPR01, IPR02, and IPR05 to IPR16 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. Table 6.3 shows the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR05 to IPR16.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Table 6.3
Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR16
Bits 15 to 12 IRQ0 IRQ4 PINT0 to PINT7 ROM-DEC Bits 11 to 8 IRQ1 IRQ5 Reserved Bits 7 to 4 IRQ2 IRQ6 ADI Bits 3 to 0 IRQ3 IRQ7 Reserved MTU1 (TGI1A, TGI1B) MTU3 (TGI3A to TGI3D) MTU5 (TGI5U, TGI5V, TGI5W) Reserved DMAC1 SCIF1 SCIF5
Register Name Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12
MTU0 MTU0 (TGI0A to TGI0D) (TCI0V, TGI0E, TGI0F) MTU2 (TGI2A, TGI2B) MTU2 (TCI2V, TCI2U)
MTU1 (TCI1V, TCI1U) MTU3 (TGI3V)
MTU4 MTU4 (TGI4A to TGI4D) (TGI4V) WDT IIC2 DMAC3 SCIF3 IIC0 DMAC0 SCIF0 SCIF4
RTC IIC1 DMAC2 SCIF2
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Section 6 Interrupt Controller (INTC)
Register Name Interrupt priority register 13 Interrupt priority register 14 Interrupt priority register 15 Interrupt priority register 16
Bits 15 to 12 SCIF6 DMAC5 Reserved SSI0
Bits 11 to 8 SCIF7 DMAC6 RCAN-ET0 SSI1
Bits 7 to 4 DMINTA DMAC7 RCAN-ET1 TMR0
Bits 3 to 0 DMAC4 Reserved IEB TMR1
As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set. Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the highest level). IPR01, IPR02, and IPR05 to IPR16 are initialized to H'0000 by a power-on reset or in deep standby mode.
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Section 6 Interrupt Controller (INTC)
6.3.2
Interrupt Control Register 0 (ICR0)
ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by a power-on reset or in deep standby mode.
Bit: 15
NMIL
14 -- 0 R
13 -- 0 R
12 -- 0 R
11 -- 0 R
10 -- 0 R
9 -- 0 R
8
NMIE
7 -- 0 R
6 -- 0 R
5 -- 0 R
4 -- 0 R
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
Initial value: R/W:
* R
0 R/W
Note: * 1 when the NMI pin is high, and 0 when the NMI pin is low.
Bit 15
Bit Name NMIL
Initial Value *
R/W R
Description NMI Input Level Sets the level of the signal input at the NMI pin. The NMI pin level can be obtained by reading this bit. This bit cannot be modified. 0: Low level is input to NMI pin 1: High level is input to NMI pin
14 to 9
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
NMIE
0
R/W
NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input
7 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 6 Interrupt Controller (INTC)
6.3.3
Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a power-on reset or in deep standby mode.
Bit: 15
IRQ7 1S
14
IRQ7 0S
13
IRQ6 1S
12
IRQ6 0S
11
IRQ5 1S
10
IRQ5 0S
9
IRQ4 1S
8
IRQ4 0S
7
IRQ3 1S
6
IRQ3 0S
5
IRQ2 1S
4
IRQ2 0S
3
IRQ1 1S
2
IRQ1 0S
1
IRQ0 1S
0
IRQ0 0S
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [Legend] n = 7 to 0
Bit Name IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description IRQ Sense Select These bits select whether interrupt signals corresponding to pins IRQ7 to IRQ0 are detected by a low level, falling edge, rising edge, or both edges. 00: Interrupt request is detected on low level of IRQn input 01: Interrupt request is detected on falling edge of IRQn input 10: Interrupt request is detected on rising edge of IRQn input 11: Interrupt request is detected on both edges of IRQn input
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Section 6 Interrupt Controller (INTC)
6.3.4
Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7 to PINT0 individually: low level or high level. ICR2 is initialized by a power-on reset or in deep standby mode.
Bit: 15
--
14
--
13
--
12
--
11
--
10
--
9
--
8
--
7
PINT 7S
6
PINT 6S
5
PINT 5S
4
PINT 4S
3
PINT 3S
2
PINT 2S
1
PINT 1S
0
PINT 0S
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7 6 5 4 3 2 1 0 [Legend] n = 7 to 0
PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
PINT Sense Select These bits select whether interrupt signals corresponding to pins PINT7 to PINT0 are detected by a low level or high level. 0: Interrupt request is detected on low level of PINTn input 1: Interrupt request is detected on high level of PINTn input
6.3.5
IRQ Interrupt Request Register (IRQRR)
IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts. IRQRR is initialized by a power-on reset or in deep standby mode.
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Section 6 Interrupt Controller (INTC)
Bit:
15 --
14 -- 0 R
13 -- 0 R
12 -- 0 R
11 -- 0 R
10 -- 0 R
9 -- 0 R
8 -- 0 R
7
6
5
4
3
2
1
0
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial value: R/W: Note: *
0 R
0 0 0 0 0 0 0 0 R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Only 0 can be written to clear the flag after 1 is read.
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7 6 5 4 3 2 1 0
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0 0 0 0 0 0 0 0
R/(W)* IRQ Interrupt Request R/(W)* These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. R/(W)* R/(W)* Level detection: R/(W)* 0: IRQn interrupt request has not occurred R/(W)* [Clearing condition] R/(W)* * IRQn input is high R/(W)* 1: IRQn interrupt has occurred [Setting condition] * IRQn input is low
Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions] * * Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF Cleared by executing IRQn interrupt exception handling
1: IRQn interrupt request is detected [Setting condition] * [Legend] n = 7 to 0 Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin
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Section 6 Interrupt Controller (INTC)
6.3.6
PINT Interrupt Enable Register (PINTER)
PINTER is a 16-bit register that enables interrupt request inputs to external interrupt input pins PINT7 to PINT0. PINTER is initialized by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7
PINT 7E
6
PINT 6E
5
PINT 5E
4
PINT 4E
3
PINT 3E
2
PINT 2E
1
PINT 1E
0
PINT 0E
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7 6 5 4 3 2 1 0 [Legend] n = 7 to 0
PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
PINT Enable These bits select whether to enable interrupt request inputs to external interrupt input pins PINT7 to PINT0. 0: PINTn input interrupt request is disabled 1: PINTn input interrupt request is enabled
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Section 6 Interrupt Controller (INTC)
6.3.7
PINT Interrupt Request Register (PIRR)
PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. PIRR is initialized by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7
PINT 7R
6
PINT 6R
5
PINT 5R
4
PINT 4R
3
PINT 3R
2
PINT 2R
1
PINT 1R
0
PINT 0R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7 6 5 4 3 2 1 0 [Legend] n = 7 to 0
PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R
0 0 0 0 0 0 0 0
R R R R R R R R
PINT Interrupt Request These bits indicate the status of the PINT7 to PINT0 interrupt requests. 0: No interrupt request at PINTn pin 1: Interrupt request at PINTn pin
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Section 6 Interrupt Controller (INTC)
6.3.8
Bank Control Register (IBCR)
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. IBCR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 E15 Initial value: 0 R/W: R/W 14 E14 0 R/W 13 E13 0 R/W 12 E12 0 R/W 11 E11 0 R/W 10 E10 0 R/W 9 E9 0 R/W 8 E8 0 R/W 7 E7 0 R/W 6 E6 0 R/W 5 E5 0 R/W 4 E4 0 R/W 3 E3 0 R/W 2 E2 0 R/W 1 E1 0 R/W 0 -- 0 R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Description Enable These bits enable or disable use of register banks for interrupt priority levels 15 to 1. However, use of register banks is always disabled for the user break interrupts. 0: Use of register banks is disabled 1: Use of register banks is enabled
Reserved This bit is always read as 0. The write value should always be 0.
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Section 6 Interrupt Controller (INTC)
6.3.9
Bank Number Register (IBNR)
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to BN0. IBNR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 14 13 BOVE 0 R/W 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 0 R 3 2 1 0
BE[1:0] Initial value: 0 R/W: R/W 0 R/W
BN[3:0]* 0 R 0 R 0 R
Bit 15, 14
Bit Name BE[1:0]
Initial Value 00
R/W R/W
Description Register Bank Enable These bits enable or disable use of register banks. 00: Use of register banks is disabled for all interrupts. The setting of IBCR is ignored. 01: Use of register banks is enabled for all interrupts except NMI and user break. The setting of IBCR is ignored. 10: Reserved (setting prohibited) 11: Use of register banks is controlled by the setting of IBCR.
13
BOVE
0
R/W
Register Bank Overflow Enable Enables of disables register bank overflow exception. 0: Generation of register bank overflow exception is disabled 1: Generation of register bank overflow exception is enabled
12 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 6 Interrupt Controller (INTC)
Bit 3 to 0
Bit Name BN[3:0]*
Initial Value 0000
R/W R
Description Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the register bank indicated by these bits, and BN is incremented by 1. After BN is decremented by 1 due to execution of a RESBANK (restore from register bank) instruction, restoration from the register bank is performed.
Note:
*
Bits BN[3:0] are initialized at a manual reset.
6.3.10
DMA Transfer Request Enable Register 0 (DREQER0)
DMA transfer request enable register 0 (DREQER0) is an 8-bit readable/writable register that enables/disables the IIC3 DMA transfer requests, and enables/disables CPU interrupt requests. DMA transfer request enable register 0 is initialized by a power-on reset or in deep standby mode.
Bit: 7 6 5 4 3 2 1 0
Reserved Initial value: 0 R/W: R/W 0 R/W
IIC3 IIC3 IIC3 IIC3 IIC3 IIC3 2ch TX 2ch RX 1ch TX 1ch RX 0ch TX 0ch RX
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name Reserved Reserved IIC3 2ch TX IIC3 2ch RX IIC3 1ch TX IIC3 1ch RX IIC3 0ch TX IIC3 0ch RX
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description DMA Transfer Request Enable Bits These bits enable/disable DMA transfer requests, and enable/disable CPU interrupt requests. 0: DMA transfer request disabled, CPU interrupt request enabled 1: DMA transfer request enabled, CPU interrupt request disabled
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Section 6 Interrupt Controller (INTC)
6.3.11
DMA Transfer Request Enable Register 1 (DREQER1)
DMA transfer request enable register 1 (DREQER1) is an 8-bit readable/writable register that enables/disables the SCIF (channels 0 to 3) DMA transfer requests, and enables/disables CPU interrupt requests. DMA transfer request enable register 1 is initialized by a power-on reset or in deep standby mode.
Bit: 7 6 5 4 3 2 1 0
SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF 3ch TX 3ch RX 2ch TX 2ch RX 1ch TX 1ch RX 0ch TX 0ch RX
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name SCIF 3ch TX SCIF 3ch RX SCIF 2ch TX SCIF 2ch RX SCIF 1ch TX SCIF 1ch RX SCIF 0ch TX SCIF 0ch RX
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description DMA Transfer Request Enable Bits These bits enable/disable DMA transfer requests, and enable/disable CPU interrupt requests. 0: DMA transfer request disabled, CPU interrupt request enabled 1: DMA transfer request enabled, CPU interrupt request disabled
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Section 6 Interrupt Controller (INTC)
6.3.12
DMA Transfer Request Enable Register 2 (DREQER2)
DMA transfer request enable register 2 (DREQER2) is an 8-bit readable/writable register that enables/disables the SCIF (channels 4 to 7) DMA transfer requests, and enables/disables CPU interrupt requests. DMA transfer request enable register 2 is initialized by a power-on reset or in deep standby mode.
Bit: 7 6 5 4 3 2 1 0
SCIF SCIF SCIF SCIF SCIF SCIF SCIF SCIF 7ch TX 7ch RX 6ch TX 6ch RX 5ch TX 5ch RX 4ch TX 4ch RX
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name SCIF 7ch TX SCIF 7ch RX SCIF 6ch TX SCIF 6ch RX SCIF 5ch TX SCIF 5ch RX SCIF 4ch TX SCIF 4ch RX
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description DMA Transfer Request Enable Bits These bits enable/disable DMA transfer requests, and enable/disable CPU interrupt requests. 0: DMA transfer request disabled, CPU interrupt request enabled 1: DMA transfer request enabled, CPU interrupt request disabled
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Section 6 Interrupt Controller (INTC)
6.3.13
DMA Transfer Request Enable Register 3 (DREQER3)
DMA transfer request enable register 3 (DREQER3) is an 8-bit readable/writable register that enables/disables the ADC, MTU2 (channels 0 to 4), and RCAN-ET (channels 0 and 1) DMA transfer requests, and enables/disables CPU interrupt requests. DMA transfer request enable register 3 is initialized by a power-on reset or in deep standby mode.
Bit: 7 6 5 4 3 2 ADC MTU2 MTU2 MTU2 MTU2 MTU2 4ch 3ch 2ch 1ch 0ch 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1
RCAN-ET
0
RCAN-ET
1ch
0ch
Initial value: 0 R/W: R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name ADC MTU2 4ch MTU2 3ch MTU2 2ch MTU2 1ch MTU2 0ch RCAN-ET 1ch RCAN-ET 0ch
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description DMA Transfer Request Enable Bits These bits enable/disable DMA transfer requests, and enable/disable CPU interrupt requests. 0: DMA transfer request disabled, CPU interrupt request enabled 1: DMA transfer request enabled, CPU interrupt request disabled
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Section 6 Interrupt Controller (INTC)
6.4
Interrupt Sources
There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level 0, that interrupt is masked at all times. 6.4.1 NMI Interrupt
The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) selects whether the rising edge or falling edge is detected. Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. 6.4.2 User Break Interrupt
A user break interrupt which occurs when a break condition set in the user break controller (UBC) matches has a priority level of 15. The user break exception handling sets the I3 to I0 bits in SR to level 15. For user break interrupts, see section 7, User Break Controller (UBC). 6.4.3 H-UDI Interrupt
The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial input of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained until they are accepted. The H-UDI exception handling sets the I3 to I0 bits in SR to level 15. For H-UDI interrupts, see section 28, User Debugging Interface (H-UDI).
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Section 6 Interrupt Controller (INTC)
6.4.4
IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. As regard to the setting method of pins IRQ7 to IRQ0, see section 25, Pin Function Controller (PFC). For the IRQ interrupts, low-level, fallingedge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority registers 01 and 02 (IPR01 and IPR02). When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the INTC while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ interrupt request detection is retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request detection. The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted IRQ interrupt. When restoring from the service routine of IRQ interrupt exception handling, execute the RTE instruction after an interrupt request has been cleared in the IRQ interrupt request register (IRQRR).
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Section 6 Interrupt Controller (INTC)
6.4.5
PINT Interrupts
PINT interrupts are input from pins PINT7 to PINT0. As regard to the setting method of pins PINT7 to PINT0, see section 25, Pin Function Controller (PFC). Input of the interrupt requests is enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register (PINTER). For the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control register 2 (ICR2). A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0 interrupts by bits 15 to 12 in interrupt priority register 05 (IPR05). When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is sent to the INTC while the PINT7 to PINT0 pins are low. An interrupt request signal is stopped being sent to the INTC when the PINT7 to PINT0 pins are driven high. The status of the interrupt requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the PINT interrupt request register (PIRR). The above description also applies to when using highlevel sensing, except for the polarity being reversed. The PINT interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the PINT interrupt. When restoring from the service routine of PINT interrupt exception handling, execute the RTE instruction after an interrupt request has been cleared in the PINT interrupt request register (PIRR). 6.4.6 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules: * * * * * * * * * * * * A/D converter (ADC) CD-ROM decoder (ROM-DEC) Multi-function timer pulse unit 2 (MTU2) Realtime clock (RTC) Watchdog timer (WDT) I2C bus interface 3 (IIC3) Direct memory access controller (DMAC) Serial communication interface with FIFO (SCIF) Controller area network (RCAN-ET) IEBusTM controller (IEB) Serial sound interface (SSI) 8-bit timer (TMR)
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Section 6 Interrupt Controller (INTC)
As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from 0 to 15 can be set for each module by interrupt priority registers 05 to 16 (IPR05 to IPR16). The on-chip peripheral module interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip peripheral module interrupt.
6.5
Interrupt Exception Handling Vector Table and Priority
Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and vector table address offsets. In interrupt exception handling, the exception service routine start address is fetched from the vector table indicated by the vector table address. For details of calculation of the vector table address, see table 5.4, Calculating Exception Handling Vector Table Addresses, in section 5, Exception Handling. The priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16). However, if two or more interrupts specified by the same IPR among IPR05 to IPR16 occur, the priorities are defined as shown in the IPR setting unit internal priority of table 6.4, and the priorities cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priorities indicated in table 6.4.
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Section 6 Interrupt Controller (INTC)
Table 6.4
Interrupt Exception Handling Vectors and Priorities
Interrupt Vector Interrupt Priority (Initial Value) 16 15 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR Setting Unit Internal Default Priority Priority -- -- -- -- -- -- -- -- -- -- -- Low High
Interrupt Source Number NMI User break H-UDI IRQ IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Vector 11 12 14 64 65 66 67 68 69 70 71
Vector Table Address Offset H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000038 to H'0000003B H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F
Corresponding IPR (Bit) -- -- -- IPR01 (15 to 12) IPR01 (11 to 8) IPR01 (7 to 4) IPR01 (3 to 0) IPR02 (15 to 12) IPR02 (11 to 8) IPR02 (7 to 4) IPR02 (3 to 0)
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Section 6 Interrupt Controller (INTC)
Interrupt Vector Interrupt Priority (Initial Value) 0 to 15 (0)
Interrupt Source Number PINT PINT0 PINT1 PINT2 PINT3 PINT4 PINT5 PINT6 PINT7 ADC ROMDEC ADI ISY IERR ITARG ISEC IBUF IREADY
Vector 80 81 82 83 84 85 86 87 92 102 103 104 105 106 107
Vector Table Address Offset H'00000140 to H'00000143 H'00000144 to H'00000147 H'00000148 to H'0000014B H'0000014C to H'0000014F H'00000150 to H'00000153 H'00000154 to H'00000157 H'00000158 to H'0000015B H'0000015C to H'0000015F H'00000170 to H'00000173 H'00000198 to H'0000019B H'0000019C to H'0000019F H'000001A0 to H'000001A3 H'000001A4 to H'000001A7 H'000001A8 to H'000001AB H'000001AC to H'000001AF
Corresponding IPR (Bit) IPR05 (15 to 12)
IPR Setting Unit Internal Default Priority Priority 1 2 3 4 5 6 7 8 High
0 to 15 (0) 0 to 15 (0)
IPR05 (7 to 4) IPR06 (15 to 12)
-- 1 2 3 4 5 6 Low
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Section 6 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority (Initial Value)
Interrupt Source Number MTU2 MTU0 TGI0A TGI0B TGI0C TGI0D TCI0V TCI0E TCI0F MTU1 TGI1A TGI1B TCI1V TCI1U MTU2 TGI2A TGI2B TCI2V TCI2U
Vector 108 109 110 111 112 113 114 116 117 120 121 124 125 128 129
Vector Table Address Offset H'000001B0 to H'000001B3 H'000001B4 to H'000001B7 H'000001B8 to H'000001BB H'000001BC to H'000001BF H'000001C0 to H'000001C3 H'000001C4 to H'000001C7 H'000001C8 to H'000001CB H'000001D0 to H'000001D3 H'000001D4 to H'000001D7 H'000001E0 to H'000001E3 H'000001E4 to H'000001E7 H'000001F0 to H'000001F3 H'000001F4 to H'000001F7 H'00000200 to H'00000203 H'00000204 to H'00000207
Corresponding IPR (Bit)
IPR Setting Unit Internal Default Priority Priority 1 2 3 4 High
0 to 15 (0) IPR06 (11 to 8)
0 to 15 (0) IPR06 (7 to 4)
1 2 3
0 to 15 (0) IPR06 (3 to 0)
1 2
0 to 15 (0) IPR07 (15 to 12)
1 2
0 to 15 (0) IPR07 (11 to 8)
1 2
0 to 15 (0) IPR07 (7 to 4)
1 2 Low
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Section 6 Interrupt Controller (INTC)
Interrupt Vector Interrupt Priority (Initial Value) 0 to 15 (0)
Interrupt Source Number MTU2 MTU3 TGI3A TGI3B TGI3C TGI3D TCI3V MTU4 TGI4A TGI4B TGI4C TGI4D TCI4V MTU5 TGI5U TGI5V TGI5W RTC ARM PRD CUP
Vector 132 133 134 135 136 140 141 142 143 144 148 149 150 152 153 154
Vector Table Address Offset H'00000210 to H'00000213 H'00000214 to H'00000217 H'00000218 to H'0000021B H'0000021C to H'0000021F H'00000220 to H'00000223 H'00000230 to H'00000233 H'00000234 to H'00000237 H'00000238 to H'0000023B H'0000023C to H'0000023F H'00000240 to H'00000243 H'00000250 to H'00000253 H'00000254 to H'00000257 H'00000258 to H'0000025B H'00000260 to H'00000263 H'00000264 to H'00000267 H'00000268 to H'0000026B
Corresponding IPR (Bit) IPR07 (3 to 0)
IPR Setting Unit Internal Default Priority Priority 1 2 3 4 High
0 to 15 (0) 0 to 15 (0)
IPR08 (15 to 12) IPR08 (11 to 8)
-- 1 2 3 4
0 to 15 (0) 0 to 15 (0)
IPR08 (7 to 4) IPR08 (3 to 0)
-- 1 2 3
0 to 15 (0)
IPR09 (15 to 12)
1 2 3 Low
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Section 6 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority (Initial Value) 0 to 15 (0) 0 to 15 (0)
Interrupt Source Number WDT IIC3 ITI IIC0 STPI0 NAKI0 RXI0 TXI0 TEI0 IIC1 STPI1 NAKI1 RXI1 TXI1 TEI1 IIC2 STPI2 NAKI2 RXI2 TXI2 TEI2
Vector 156 157 158 159 160 161 164 165 166 167 168 170 171 172 173 174
Vector Table Address Offset H'00000270 to H'00000273 H'00000274 to H'00000277 H'00000278 to H'0000027B H'0000027C to H'0000027F H'00000280 to H'00000283 H'00000284 to H'00000287 H'00000290 to H'00000293 H'00000294 to H'00000297 H'00000298 to H'0000029B H'0000029C to H'0000029F H'000002A0 to H'000002A3 H'000002A8 to H'000002AB H'000002AC to H'000002AF H'000002B0 to H'000002B3 H'000002B4 to H'000002B7 H'000002B8 to H'000002BB
Corresponding IPR (Bit) IPR09 (11 to 8) IPR09 (7 to 4)
IPR Setting Unit Internal Default Priority Priority -- 1 2 3 4 5 High
0 to 15 (0)
IPR10 (15 to 12)
1 2 3 4 5
0 to 15 (0)
IPR10 (11 to 8)
1 2 3 4 5 Low
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Section 6 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority (Initial Value) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
Interrupt Source Number
Vector
Vector Table Address Offset H'000002C0 to H'000002C3 H'000002C4 to H'000002C7 H'000002C8 to H'000002CB H'000002CC to H'000002CF H'000002D0 to H'000002D3 H'000002D4 to H'000002D7 H'000002D8 to H'000002DB H'000002DC to H'000002DF H'000002E0 to H'000002E3 H'000002E4 to H'000002E7 H'000002E8 to H'000002EB H'000002EC to H'000002EF H'000002F0 to H'000002F3 H'000002F4 to H'000002F7 H'000002F8 to H'000002FB H'000002FC to H'000002FF
Corresponding IPR (Bit) IPR10 (7 to 4) IPR10 (3 to 0) IPR11 (15 to 12) IPR11 (11 to 8) IPR11 (7 to 4)
IPR Setting Unit Internal Default Priority Priority -- -- -- -- 1 2 3 4 High
DMAC DMAC0 DMINT0 176 DMAC1 DMINT1 177 DMAC2 DMINT2 178 DMAC3 DMINT3 179 SCIF SCIF0 BRI0 ERI0 RXI0 TXI0 SCIF1 BRI1 ERI1 RXI1 TXI1 SCIF2 BRI2 ERI2 RXI2 TXI2 180 181 182 183 184 185 186 187 188 189 190 191
0 to 15 (0)
IPR11 (3 to 0)
1 2 3 4
0 to 15 (0)
IPR12 (15 to 12)
1 2 3 4 Low
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Section 6 Interrupt Controller (INTC)
Interrupt Vector Interrupt Source Number SCIF SCIF3 BRI3 ERI3 RXI3 TXI3 SCIF4 BRI4 ERI4 RXI4 TXI4 SCIF5 BRI5 ERI5 RXI5 TXI5 SCIF6 BRI6 ERI6 RXI6 TXI6 Vector Table Address Offset H'00000300 to H'00000303 H'00000304 to H'00000307 H'00000308 to H'0000030B H'0000030C to H'0000030F H'00000310 to H'00000313 H'00000314 to H'00000317 H'00000318 to H'0000031B H'0000031C to H'0000031F H'00000320 to H'00000323 H'00000324 to H'00000327 H'00000328 to H'0000032B H'0000032C to H'0000032F H'00000330 to H'00000333 H'00000334 to H'00000337 H'00000338 to H'0000033B H'0000033C to H'0000033F
Vector 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207
Interrupt Priority (Initial Value) 0 to 15 (0)
Corresponding IPR (Bit) IPR12 (11 to 8)
IPR Setting Unit Internal Default Priority Priority 1 2 3 4 High
0 to 15 (0)
IPR12 (7 to 4)
1 2 3 4
0 to 15 (0)
IPR12 (3 to 0)
1 2 3 4
0 to 15 (0)
IPR13 (15 to 12)
1 2 3 4 Low
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Section 6 Interrupt Controller (INTC)
Interrupt Vector Interrupt Source Number SCIF SCIF7 BRI7 ERI7 RXI7 TXI7 DMAC DMINTA Vector Table Address Offset H'00000340 to H'00000343 H'00000344 to H'00000347 H'00000348 to H'0000034B H'0000034C to H'0000034F H'00000350 to H'00000353 H'00000360 to H'00000363 H'00000364 to H'00000367 H'00000368 to H'0000036B H'0000036C to H'0000036F H'00000390 to H'00000393 H'00000394 to H'00000397 H'00000398 to H'0000039B H'0000039C to H'0000039F H'000003A0 to H'000003A3
Vector 208 209 210 211 212
Interrupt Priority (Initial Value) 0 to 15 (0)
Corresponding IPR (Bit) IPR13 (11 to 8)
IPR Setting Unit Internal Default Priority Priority 1 2 3 4 High
0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
IPR13 (7 to 4) IPR13 (3 to 0) IPR14 (15 to 12) IPR14 (11 to 8) IPR14 (7 to 4) IPR15 (11 to 8)
-- -- -- -- -- 1 2 3 4 5 Low
DMAC4 DMINT4 216 DMAC5 DMINT5 217 DMAC6 DMINT6 218 DMAC7 DMINT7 219 RCAN- RCANET ET0 ERS OVR SLE RM0 RM1 228 229 230 231 232
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Section 6 Interrupt Controller (INTC)
Interrupt Vector Interrupt Source Number RCAN- RCANET ET1 ERS OVR SLE RM0 RM1 IEB SSI SSI0 SSI1 TMR TMR0 CMIA0 CMIB0 OVI0 TMR1 CMIA1 CMIB1 OVI1 Vector Table Address Offset H'000003A8 to H'000003AB H'000003AC to H'000003AF H'000003B0 to H'000003B3 H'000003B4 to H'000003B7 H'000003B8 to H'000003BB H'000003C0 to H'000003C3 H'000003D0 to H'000003D3 H'000003D4 to H'000003D7 H'000003D8 to H'000003DB H'000003DC to H'000003DF H'000003E0 to H'000003E3 H'000003F0 to H'000003F3 H'000003F4 to H'000003F7 H'000003F8 to H'000003FB
Vector 234 235 236 237 238 240 244 245 246 247 248 252 253 254
Interrupt Priority (Initial Value) 0 to 15 (0)
Corresponding IPR (Bit) IPR15 (7 to 4)
IPR Setting Unit Internal Default Priority Priority 1 2 3 4 5 High
0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)
IPR15 (3 to 0) IPR16 (15 to 12) IPR16 (11 to 8) IPR16 (7 to 4)
-- -- -- 1 2 3
0 to 15 (0)
IPR16 (3 to 0)
1 2 3 Low
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Section 6 Interrupt Controller (INTC)
6.6
6.6.1
Operation
Interrupt Operation Sequence
The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers 01, 02, and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16). Lower priority interrupts are ignored*. If two of these interrupts have the same priority level or if multiple interrupts occur within a single IPR, the interrupt with the highest priority is selected, according to the default priority and IPR setting unit internal priority shown in table 6.4. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (figure 6.4). 5. The start address of the interrupt exception service routine is fetched from the exception handling vector table corresponding to the accepted interrupt. 6. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt is copied to bits I3 to I0 in SR. 7. The program counter (PC) is saved onto the stack. 8. The CPU jumps to the fetched start address of the interrupt exception service routine and starts executing the program. The jump that occurs is not a delayed branch. Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-sensing are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ Interrupts. Interrupts held pending due to edge-sensing are cleared by a power-on reset or in deep standby mode.
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Section 6 Interrupt Controller (INTC)
Program execution state
Interrupt? Yes
No
NMI? Yes
No
No User break? Yes H-UDI interrupt? Yes No No No No
Level 15 interrupt? Yes
Level 14 interrupt? Yes I3 to I0 level 13? No
Yes
I3 to I0 level 14? No
Level 1 interrupt? Yes Yes I3 to I0 = level 0? No
Read exception handling vector table Save SR to stack Copy accept-interrupt level to I3 to I0 Save PC to stack Branch to interrupt exception service routine
Figure 6.2 Interrupt Operation Flow
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Section 6 Interrupt Controller (INTC)
6.6.2
Stack after Interrupt Exception Handling
Figure 6.3 shows the stack after interrupt exception handling.
Address 4n - 8 4n - 4 4n PC*1 SR 32 bits 32 bits SP*2
Notes:
1. 2.
PC: Start address of the next instruction (return destination instruction) after the executed instruction Always make sure that SP is a multiple of 4.
Figure 6.3 Stack after Interrupt Exception Handling
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Section 6 Interrupt Controller (INTC)
6.7
Interrupt Response Time
Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the interrupt exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 6.5 Interrupt Response Time
Number of States Peripheral Module 2 Icyc + 1 Bcyc + 1 Pcyc
Item
NMI
User Break 3 Icyc
H-UDI 2 Icyc + 1 Pcyc
IRQ, PINT 2 Icyc + 3 Bcyc + 1 Pcyc
Remarks
2 Icyc + Time from occurrence of interrupt request until interrupt 2 Bcyc + 1 Pcyc controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU Time from input of interrupt request signal to CPU until sequence currently being executed is completed, interrupt exception handling starts, and first instruction in interrupt exception service routine is fetched No register banking Min. Max.
3 Icyc + m1 + m2 4 Icyc + 2 (m1 + m2) + m3
Min. is when the interrupt wait time is zero. Max. is when a higherpriority interrupt request has occurred during interrupt exception handling. 3 Icyc + m1 + m2 12 Icyc + m1 + m2 Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction.
Register banking without register bank overflow Register banking with register bank overflow
Min. Max.

Min. Max.

3 Icyc + m1 + m2 3 Icyc + m1 + m2 + 19 (m4)
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Section 6 Interrupt Controller (INTC)
Number of States Peripheral Module 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2
Item Interrupt response time No register banking Min.
NMI 5 Icyc + 2 Bcyc + 1 Pcyc + m1 + m2
User Break H-UDI 6 Icyc + m1 + m2 5 Icyc + 1 Pcyc + m1 + m2
IRQ, PINT 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 6 Icyc + 3 Bcyc + 1 Pcyc + 2 (m1 + m2) + m3 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 14 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 + 19 (m4)
Remarks 120-MHz operation*1*2: 0.067 to 0.142 s
Max.
6 Icyc + 7 Icyc + 2 Bcyc + 2 (m1 + m2) 1 Pcyc + + m3 2 (m1 + m2) + m3
6 Icyc + 1 Pcyc + 2 (m1 + m2) + m3
6 Icyc + 120-MHz operation*1*2: 0.100 to 0.175 s 1 Bcyc + 1 Pcyc + 2 (m1 + m2) + m3 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 14 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 + 19 (m4) 120-MHz operation*1*2: 0.092 to 0.142 s
Register banking without register bank overflow
Min.
5 Icyc + 1 Pcyc + m1 + m2
Max.
14 Icyc + 1 Pcyc + m1 + m2
120-MHz operation*1*2: 0.167 to 0.217 s
Register banking with register bank overflow
Min.
5 Icyc + 1 Pcyc + m1 + m2
120-MHz operation*1*2: 0.092 to 0.142 s
Max.
5 Icyc + 1 Pcyc + m1 + m2 + 19 (m4)
120-MHz operation*1*2: 0.245 to 0.300 s
Notes: m1 to m4 are the number of states needed for the following memory accesses. m1: Vector address read (longword read) m2: SR save (longword write) m3: PC save (longword write) m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. 1. In the case of m1 = m2 = m3 = m4 = 1 Icyc. 2. In the case of I:B:P = 120:60:30 [MHz].
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Section 6 Interrupt Controller (INTC)
Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3
Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine
F
D
E
E
M
M
M F D E
[Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) F: Instruction fetch. Instruction is fetched from memory in which program is stored. D: Instruction decoding. Fetched instruction is decoded. E: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. M: Memory access. Memory data access is performed.
Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking)
2 Icyc + 3 Bcyc + 1 Pcyc IRQ m1 F First instruction in interrupt service routine First instruction in multiple interrupt service routine D D E E M m2 M m3 M F E D E M M M F D m1 m2 3 Icyc + m1 1 Icyc + m1 + 2(m2) + m3
Interrupt acceptance [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack)
Multiple interrupt acceptance
Figure 6.5 Example of Pipeline Operation for Multiple Interrupts (No Register Banking)
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Section 6 Interrupt Controller (INTC)
Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3
Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack)
F
D
E
E
M
M
M F
E D E
Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking without Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc IRQ 9 Icyc 3 Icyc + m1 + m2
RESBANK instruction Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack)
F
D
E
E
E
E
E
E
E
E
E D E E
m1 m2 m3 M M M F E D
Interrupt acceptance
Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow)
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Section 6 Interrupt Controller (INTC)
Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) 3 Icyc m1 m2 m3
F
D
E
E
M
M
M F
... ...
M ... D
Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc IRQ RESBANK instruction Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine Interrupt acceptance [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) m4: Restoration of banked registers F D E M M M ... M 2 Icyc + 17(m4) 1 Icyc + m1 + m2 + 2(m4) m4 m4 M D M E W E M M M F ... ... D m1 m2 m3
Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking with Register Bank Overflow)
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Section 6 Interrupt Controller (INTC)
6.8
Register Banks
This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 6.10 shows the register bank configuration.
Registers General registers R0 R1 : : R14 R15 Control registers SR GBR VBR TBR MACH MACL PR PC Interrupt generated (save) Register banks R0 R1 : : R14 GBR MACH MACL PR IVO Bank 0 Bank 1 .... Bank 14
System registers
RESBANK instruction (restore)
Bank control registers (interrupt controller) Bank control register Bank number register Note: VTO: : Banked register Vector table address offset IBCR IBNR
Figure 6.10 Overview of Register Bank Configuration
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Section 6 Interrupt Controller (INTC)
6.8.1 (1)
Register Banks and Bank Control Registers Banked Register
The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset (VTO) are banked. (2) Input/Output of Banks
This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in lastout (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place in the reverse order, beginning from the last bank saved to. 6.8.2 (1) Bank Save and Restore Operations Saving to Bank
Figure 6.11 shows register bank save operations. The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU: (a) Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the interrupt is generated. (b) The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN, bank i. (c) The BN value is incremented by 1.
Register banks +1 (c) BN (a) Bank 0 Bank 1 : : Bank i Bank i + 1 : : Bank 14 Registers
R0 to R14 GBR MACH MACL PR VTO
(b)
Figure 6.11 Bank Save Operations
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Section 6 Interrupt Controller (INTC)
Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the exception service routine.
3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3
Instruction (instruction replacing interrupt exception handling)
F
D
E
E
M
M
M
E
(1) VTO, PR, GBR, MACL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 Saved to bank Overrun fetch First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) F (4) R4, R5, R6, R7 (5) R0, R1, R2, R3
F
D
E
Figure 6.12 Bank Save Timing (2) Restoration from Bank
The RESBANK (restore from register bank) instruction is used to restore data saved in a register bank. After restoring data from the register banks with the RESBANK instruction at the end of the interrupt service routine, execute the RTE instruction to return from exception handling.
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Section 6 Interrupt Controller (INTC)
6.8.3
Save and Restore Operations after Saving to All Banks
If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register banks, automatic saving to the stack is performed instead of register bank saving if the BOVE bit in the bank number register (IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception occurs and data is not saved to the stack. Save and restore operations when using the stack are as follows: (1) Saving to Stack
1. The status register (SR) and program counter (PC) are saved to the stack during interrupt exception handling. 2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14, R13, ..., R1, and R0. 3. The register bank overflow bit (BO) in SR is set to 1. 4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. (2) Restoration from Stack
When the RESBANK (restore from register bank) instruction is executed with the register bank overflow bit (BO) in SR set to 1, the CPU operates as follows: 1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. The registers are restored from the stack in the order of R0, R1, ..., R13, R14, PR, GBR, MACH, and MACL. 2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15.
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Section 6 Interrupt Controller (INTC)
6.8.4
Register Bank Exception
There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow
This exception occurs if, after data has been saved to all of the register banks, an interrupt for which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number register (IBNR) remains set to the bank count of 15 and saving is not performed to the register bank. (2) Register Bank Underflow
This exception occurs if the RESBANK (restore from register bank) instruction is executed when no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH, MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number register (IBNR) remains set to 0. 6.8.5 Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. When this happens, the CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a register bank overflow, and the start address of the executed RESBANK instruction for a register bank underflow. To prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. Program execution starts from the exception service routine start address.
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Section 6 Interrupt Controller (INTC)
6.9
Data Transfer with Interrupt Request Signals
Interrupt request signals can be used to activate the DMAC and transfer data. Interrupt sources that are specified to activate the DMAC are masked by setting the DMA transfer enable bit in DREQER0 to DREQER3 to 1 without being input to the INTC. 6.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but not DMAC Activation
1. Clear the corresponding DMAC transfer request enable bit in DREQER0 to DREQER3 to 0. 2. When an interrupt occurs, the interrupt request will be sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt handling routine. 6.9.2 Handling Interrupt Request Signals as Sources for DMAC Activation but not CPU Interrupt
1. Select* the signals as DMAC activating sources by setting the corresponding DMAC transfer request enable bit in DREQER0 to DREQER3 to 1. This masks the CPU interrupt source regardless of the interrupt priority register settings. 2. When an interrupt occurs, the activation source will be sent to the DMAC. 3. The DMAC clears the activation source during the transfer. Note: * As for the method to select the DMAC request sources, see section 11, Direct Memory Access Controller (DMAC).
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Section 6 Interrupt Controller (INTC)
6.10
6.10.1
Usage Note
Timing to Clear an Interrupt Source
The interrupt source flags should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction.
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Section 7 User Break Controller (UBC)
Section 7 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Instruction fetch or data read/write of CPU, data size, data contents, address value, and stop timing in the case of instruction fetch are break conditions that can be set in the UBC. Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is performed by issuing bus cycles on the memory access bus (M bus). The UBC monitors the C bus and internal bus (I bus).
7.1
Features
1. The following break comparison conditions can be set. Number of break channels: two channels (channels 0 and 1) User break can be requested as the independent condition on channels 0 and 1. * Address Comparison of the 32-bit address is maskable in 1-bit units. One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus (IAB)) can be selected. * Data Comparison of the 32-bit data is maskable in 1-bit units. One of the two data buses (M data bus (MDB) and I data bus (IDB)) can be selected. * Bus cycle Instruction fetch (only when C bus is selected) or data access * Read/write * Operand size Byte, word, and longword 2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt exception processing is set before or after an instruction is executed. 3. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin.
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Section 7 User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
Internal bus (I bus) Access control IDB IAB CPU bus (C bus) MDB MAB FAB Access comparator BBR_0 BAR_0 Address comparator BAMR_0 Internaal bus (I bus)
Data comparator
BDR_0 BDMR_0
Channel 0
Access comparator
BBR_1 BAR_1
Address comparator
BAMR_1
Data comparator
BDR_1 BDMR_1
Channel 1
BRCR Control
User break request UBCTRG pin output [Legend] BBR: Break bus cycle register BAR: Break address register BAMR: Break address mask register BDR: Break data register BDMR: Break data mask register BRCR: Break control register
Figure 7.1 Block Diagram of UBC
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Section 7 User Break Controller (UBC)
7.2
Input/Output Pin
Table 7.1 shows the pin configuration of the UBC. Table 7.1
Pin Name UBC trigger
Pin Configuration
Symbol UBCTRG I/O Output Function Indicates that a setting condition is satisfied on either channel 0 or 1 of the UBC.
7.3
Register Descriptions
The UBC has the following registers. Table 7.2
Channel 0
Register Configuration
Register Name Break address register_0 Break address mask register_0 Break bus cycle register_0 Break data register_0 Break data mask register_0 Abbreviation BAR_0 BAMR_0 BBR_0 BDR_0 BDMR_0 BAR_1 BAMR_1 BBR_1 BDR_1 BDMR_1 BRCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 Address H'FFFC0400 H'FFFC0404 Access Size 32 32
H'FFFC04A0 16 H'FFFC0408 32
H'FFFC040C 32 H'FFFC0410 H'FFFC0414 32 32
1
Break address register_1 Break address mask register_1 Break bus cycle register_1 Break data register_1 Break data mask register_1
H'FFFC04B0 16 H'FFFC0418 32
H'FFFC041C 32 H'FFFC04C0 32
Common
Break control register
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Section 7 User Break Controller (UBC)
7.3.1
Break Address Register (BAR)
BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset or in deep standby, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BA8 0 R/W 0 R/W 7 BA7 0 R/W 0 R/W 6 BA6 0 R/W 0 R/W 5 BA5 0 R/W 0 R/W 4 BA4 0 R/W 0 R/W 3 BA3 0 R/W 0 R/W 2 BA2 0 R/W 0 R/W 1 BA1 0 R/W 0 R/W 0 BA0 0 R/W
BA15 BA14 BA13 BA12 BA11 BA10 BA9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 0
Bit Name
Initial Value
R/W R/W
Description Break Address Store an address on the CPU address bus (FAB or MAB) or IAB specifying break conditions. When the C bus and instruction fetch cycle are selected by BBR, specify an FAB address in bits BA31 to BA0. When the C bus and data access cycle are selected by BBR, specify an MAB address in bits BA31 to BA0.
BA31 to BA0 All 0
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.
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Section 7 User Break Controller (UBC)
7.3.2
Break Address Mask Register (BAMR)
BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address bits specified by BAR. BAMR is initialized to H'00000000 by a power-on reset or in deep standby, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name BAM31 to BAM0
Initial Value All 0
R/W R/W
Description Break Address Mask Specify bits masked in the break address bits specified by BAR (BA31 to BA0). 0: Break address bit BAn is included in the break condition 1: Break address bit BAn is masked and not included in the break condition Note: n = 31 to 0
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Section 7 User Break Controller (UBC)
7.3.3
Break Data Register (BDR)
BDR is a 32-bit readable/writable register. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the two data buses for a break condition. BDR is initialized to H'00000000 by a power-on reset or in deep standby, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BD8 0 R/W 0 R/W 7 BD7 0 R/W 0 R/W 6 BD6 0 R/W 0 R/W 5 BD5 0 R/W 0 R/W 4 BD4 0 R/W 0 R/W 3 BD3 0 R/W 0 R/W 2 BD2 0 R/W 0 R/W 1 BD1 0 R/W 0 R/W 0 BD0 0 R/W
BD15 BD14 BD13 BD12 BD11 BD10 BD9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 0
Bit Name
Initial Value
R/W R/W
Description Break Data Bits Store data which specifies a break condition. If the I bus is selected in BBR, specify the break data on IDB in bits BD31 to BD0. If the C bus is selected in BBR, specify the break data on MDB in bits BD31 to BD0.
BD31 to BD0 All 0
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0.
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Section 7 User Break Controller (UBC)
7.3.4
Break Data Mask Register (BDMR)
BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits specified by BDR. BDMR is initialized to H'00000000 by a power-on reset or in deep standby, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16
Initial value: 0 R/W: R/W Bit: 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name BDM31 to BDM0
Initial Value All 0
R/W R/W
Description Break Data Mask Specify bits masked in the break data bits specified by BDR (BD31 to BD0). 0: Break data bit BDn is included in the break condition 1: Break data bit BDn is masked and not included in the break condition Note: n = 31 to 0
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0.
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Section 7 User Break Controller (UBC)
7.3.5
Break Bus Cycle Register (BBR)
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions. BBR is initialized to H'0000 by a power-on reset and in deep standby, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UBID DBE 0 R/W 0 R/W 0 R/W
CP[3:0] 0 R/W 0 R/W 0 R/W
CD[1:0] 0 R/W 0 R/W
ID[1:0] 0 R/W 0 R/W
RW[1:0] 0 R/W 0 R/W
SZ[1:0] 0 R/W 0 R/W
Bit 15, 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. User Break Interrupt Disable Disables or enables user break interrupt requests when a break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled Data Break Enable Selects whether the data bus condition is included in the break conditions. 0: Data bus condition is not included in break conditions 1: Data bus condition is included in break conditions I-Bus Bus Select Select the bus master when the bus cycle of the break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). xxx1: CPU cycle is included in break conditions xx1x: Reserved. Setting prohibited x1xx: Reserved. Setting prohibited 1xxx: Reserved. Setting prohibited
13
UBID
0
R/W
12
DBE
0
R/W
11 to 8
CP[3:0]
0000
R/W
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Section 7 User Break Controller (UBC)
Bit 7, 6
Bit Name CD[1:0]
Initial Value 00
R/W R/W
Description C Bus Cycle/I Bus Cycle Select Select the C bus cycle or I bus cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle
5, 4
ID[1:0]
00
R/W
Instruction Fetch/Data Access Select Select the instruction fetch cycle or data access cycle as the bus cycle of the break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle
3, 2
RW[1:0]
00
R/W
Read/Write Select Select the read cycle or write cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle
1, 0
SZ[1:0]
00
R/W
Operand Size Select Select the operand size of the bus cycle for the break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access
[Legend] x: Don't care
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Section 7 User Break Controller (UBC)
7.3.6
Break Control Register (BRCR)
BRCR sets the following conditions: 1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle is set before or after instruction execution. 2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied. BRCR is a 32-bit readable/writable register that has break condition match flags and bits for setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid (previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on reset and in deep standby, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit: 31 Initial value: R/W: Bit: 0 R 15 30 0 R 14 29 0 R 13 28 0 R 12 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 16
CKS[1:0] 0 R/W 1 0 R 0 R/W 0 0 R
SCMFC SCMFC SCMFD SCMFD 0 1 0 1
PCB1 PCB0 0 R/W 0 R/W
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 18
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
17, 16
CKS[1:0]
00
R/W
Clock Select Specifies the pulse width output to the UBCTRG pin when a break condition is satisfied. 00: Pulse width of UBCTRG is one bus clock cycle 01: Pulse width of UBCTRG is two bus clock cycles 10: Pulse width of UBCTRG is four bus clock cycles 11: Pulse width of UBCTRG is eight bus clock cycles
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Section 7 User Break Controller (UBC)
Bit 15
Bit Name SCMFC0
Initial Value 0
R/W R/W
Description C Bus Cycle Condition Match Flag 0 When the C bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 0 does not match 1: The C bus cycle condition for channel 0 matches
14
SCMFC1
0
R/W
C Bus Cycle Condition Match Flag 1 When the C bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 1 does not match 1: The C bus cycle condition for channel 1 matches
13
SCMFD0
0
R/W
I Bus Cycle Condition Match Flag 0 When the I bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 0 does not match 1: The I bus cycle condition for channel 0 matches
12
SCMFD1
0
R/W
I Bus Cycle Condition Match Flag 1 When the I bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 1 does not match 1: The I bus cycle condition for channel 1 matches
11 to 7
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 7 User Break Controller (UBC)
Bit 6
Bit Name PCB1
Initial Value 0
R/W R/W
Description PC Break Select 1 Selects the break timing of the instruction fetch cycle for channel 1 as before or after instruction execution. 0: PC break of channel 1 is generated before instruction execution 1: PC break of channel 1 is generated after instruction execution
5
PCB0
0
R/W
PC Break Select 0 Selects the break timing of the instruction fetch cycle for channel 0 as before or after instruction execution. 0: PC break of channel 0 is generated before instruction execution 1: PC break of channel 0 is generated after instruction execution
4 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 7 User Break Controller (UBC)
7.4
7.4.1
Operation
Flow of the User Break Operation
The flow from setting of break conditions to user break exception handling is described below: 1. The break address is set in the break address register (BAR). The masked address bits are set in the break address mask register (BAMR). The break data is set in the break data register (BDR). The masked data bits are set in the break data mask register (BDMR). The bus break conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set to 00. The relevant break control conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBR, and branch after reading from the last written register. The newly written register values become valid from the instruction at the branch destination. 2. In the case where the break conditions are satisfied and the user break interrupt request is enabled, the UBC sends a user break request to the INTC, sets the C bus condition match flag (SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the width set by the CKS[1:0] bits. Setting the UBID bit in BBR to 1 enables external monitoring of the trigger output without requesting user break interrupts. 3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the user break interrupt has a priority level of 15, it is accepted when the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are checked, and condition match flags are set if the conditions match. For details on ascertaining the priority, see section 6, Interrupt Controller (INTC). 4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been satisfied. Clear the condition match flags during the user break interrupt exception processing routine. The interrupt occurs again if this operation is not performed. 5. There is a chance that the break set in channel 0 and the break set in channel 1 occur around the same time. In this case, there will be only one break request to the INTC, but these two break channel match flags may both be set. 6. When selecting the I bus as the break condition, note as follows: Whether or not the access the CPU issued on the C bus is issued on the I bus depends on the setting of the cache. As regard to the I bus operation that depends on cache conditions, see table 8.8 in section 8, Cache.
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Section 7 User Break Controller (UBC)
When a break condition is specified for the I bus, only the data access cycle is monitored. The instruction fetch cycle (including cache update cycle) is not monitored. If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the break is to be accepted cannot be clearly defined. 7.4.2 Break on Instruction Fetch Cycle
1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBR), the break condition is the FAB bus instruction fetch cycle. Whether a start of user break interrupt exception processing is set before or after the execution of the instruction can be selected with the PCB0 or PCB1 bit in the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1. 2. A break for instruction fetch which is set as a break before instruction execution occurs when it is confirmed that the instruction has been fetched and will be executed. This means a break does not occur for instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the user break interrupt request is not received until the execution of the first instruction at the branch destination. Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When setting a break condition for break after instruction execution, the instruction set with the break condition is executed and then the break is generated prior to execution of the next instruction. As with pre-execution breaks, a break does not occur with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, the user break interrupt request is not received until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated.
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Section 7 User Break Controller (UBC)
7.4.3
Break on Data Access Cycle
1. If the C bus is specified as a break condition for data access break, condition comparison is performed for the logical addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles on the bus specified by the I bus select bits, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 6 in section 7.4.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 7.3. Table 7.3
Access Size Longword Word Byte
Data Access Cycle Addresses and Operand Size Comparison Conditions
Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set in the break address register (BAR), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size in the break bus cycle register (BBR). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in the four bytes at bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 of the break data register (BDR) and break data mask register (BDMR). To specify word data for this case, set the same data in the two words at bits 31 to 16 and 15 to 0. 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the data access cycle is selected, the instruction at which the break will occur cannot be determined.
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Section 7 User Break Controller (UBC)
7.4.4
Value of Saved Program Counter
When a user break interrupt request is received, the address of the instruction from where execution is to be resumed is saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access cycle is specified as a break condition, the instruction at which the break should occur cannot be uniquely determined. 1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved to the stack. The instruction that matched the condition is not executed, and the break occurs before it. However, when a delay slot instruction matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved to the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However, when a delayed branch instruction or delay slot matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition: The address after executing several instructions of the instruction that matched the break condition is saved to the stack.
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Section 7 User Break Controller (UBC)
7.4.5 (1)
Usage Examples Break Condition Specified for C Bus Instruction Fetch Cycle
(Example 1-1) * Register specifications BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Address: H'00000404, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2) * Register specifications BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415, BAMR_1 = H'00000000, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000000 Address: H'00027128, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/write/word Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel 0, a user break does not occur since instruction fetch is not a write cycle. On channel 1, a user break does not occur since instruction fetch is performed for an even address.
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Section 7 User Break Controller (UBC)
(Example 1-3) * Register specifications BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_0 = H'0054, BAR_1= H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Address: H'00008404, Address mask: H'00000FFF Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. (2) Break Condition Specified for C Bus Data Access Cycle
(Example 2-1) * Register specifications BAR_0 = H'00123456, BAMR_0 = H'00000000, BBR_0 = H'0064, BAR_1= H'000ABCDE, BAMR_1 = H'000000FF, BBR_1 = H'106A, BDR_1 = H'A512A512, BDMR_1 = H'00000000, BRCR = H'00000000 Address: H'00123456, Address mask: H'00000000 Bus cycle: C bus/data access/read (operand size is not included in the condition) Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: C bus/data access/write/word On channel 0, a user break occurs with longword read from address H'00123456, word read from address H'00123456, or byte read from address H'00123456. On channel 1, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.
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Section 7 User Break Controller (UBC)
(3)
Break Condition Specified for I Bus Data Access Cycle
(Example 3-1) * Register specifications BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0094, BAR_1= H'00055555, BAMR_1 = H'00000000, BBR_1 = H'11A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F, BRCR = H'00000000 Address: H'00314156, Address mask: H'00000000 Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition) Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus/data access/write/byte On channel 0, the setting of I bus/instruction fetch is ignored. On channel 1, a user break occurs when the CPU writes byte data H'7x in address H'00055555 on the I bus.
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Section 7 User Break Controller (UBC)
7.5
Usage Notes
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. The UBC cannot monitor access to the C bus and I bus cycles in the same channel. 3. When a user break interrupt request and another exception source occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, Exception Handling. If an exception source with higher priority occurs, the user break interrupt request is not received. 4. Note the following when a break occurs in a delay slot. If a pre-execution break is set at a delay slot instruction, the user break interrupt request is not received immediately before execution of the branch destination. 5. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. 6. Do not set an address within an interrupt exception handling routine whose interrupt priority level is at least 15 (including user break interrupts) as a break address. 7. Do not set break after instruction execution for the SLEEP instruction or for the delayed branch instruction where the SLEEP instruction is placed at its delay slot. 8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are placed. If the address of the lower 16 bits is set and a break before instruction execution is set as a break condition, the break is handled as a break after instruction execution. 9. Do not set a break after instruction execution for the DIVU or DIVS instruction. If a break after instruction execution is set for the DIVU or DIVS instruction and an exception or interrupt occurs during execution of the DIVU or DIVS instruction, a break after instruction execution occurs even though execution of the DIVU or DIVS instruction is halted. 10. Do not set a pre-execution break for the instruction that comes after the DIVU or DIVS instruction. If a pre-execution break is set for the instruction that comes after the DIVU or DIVS instruction and an exception or interrupt occurs during execution of the DIVU or DIVS instruction, a pre-execution break occurs even though execution of the DIVU or DIVS instruction is halted.
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Section 7 User Break Controller (UBC)
11. Do not set a pre-execution break and a break after instruction execution simultaneously in one address. For example, if a pre-execution break for channel 0 and a break after instruction execution for channel 1 are set simultaneously for one address, a break generated prior to instruction execution for channel 0 can set a condition-match flag after the instruction execution for channel 1.
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Section 7 User Break Controller (UBC)
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Section 8 Cache
Section 8 Cache
8.1 Features
* Capacity Instruction cache: 8 Kbytes Operand cache: 8 Kbytes * Structure: Instructions/data separated, 4-way set associative * Cache lock function (only for operand cache): Way 2 and way 3 are lockable * Line size: 16 bytes * Number of entries: 128 entries/way * Write system: Write-back/write-through selectable * Replacement method: Least-recently-used (LRU) algorithm 8.1.1 Cache Structure
The cache separates data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 2 Kbytes (16 bytes x 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure 8.1 shows the operand cache structure. The instruction cache structure is the same as the operand cache structure except for not having the U bit.
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Section 8 Cache
Address array (ways 0 to 3)
Data array (ways 0 to 3)
LRU
Entry 0 Entry 1 . . . . . .
V U Tag address
0 1 . . . . . .
LW0
LW1
LW2
LW3
0 1 . . . . . .
Entry 127 23 (1 + 1 + 21) bits
127 128 (32 x 4) bits LW0 to LW3: Longword data 0 to 3
127 6 bits
Figure 8.1 Operand Cache Structure (1) Address Array
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit (only for operand cache) indicates whether the entry has been written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the external memory access. It is composed of 21 bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, as values of addresses in the cache valid space are from H'00000000 to H'1FFFFFFF (see section 9, Bus State Controller (BSC)), the upper three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset and in deep standby mode but not initialized by a manual reset or in software standby mode. The tag address is not initialized by a power-on reset or manual reset or in software standby mode. The tag address becomes undefined after deep standby. (2) Data Array
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on reset or manual reset or in software standby mode. The data array becomes undefined after deep standby.
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Section 8 Cache
(3)
LRU
With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way that has been least recently accessed. Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between LRU and way replacement is shown in table 8.1 when the cache lock function (only for operand cache) is not used (concerning the case where the cache lock function is used, see section 8.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 8.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 8.1. The LRU bits are initialized to B'000000 by a power-on reset and in deep standby but not initialized by a manual reset or in software standby mode. Table 8.1 LRU and Way Replacement (Cache Lock Function Not Used)
Way to be Replaced 3 2 1 0
LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111
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Section 8 Cache
8.2
Register Descriptions
The cache has the following registers. Table 8.2 Register Configuration
Abbreviation CCR1 CCR2 R/W R/W R/W Initial Value H'00000000 H'00000000 Address H'FFFC1000 H'FFFC1004 Access Size 32 32
Register Name Cache control register 1 Cache control register 2
8.2.1
Cache Control Register 1 (CCR1)
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or write-back mode for operand cache. Programs that change the contents of CCR1 should be placed in an address space that is not cached, and an address space that is cached should be accessed after reading the contents of CCR1. CCR1 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a manual reset or in software standby mode.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 ICF 0 R/W 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 ICE 0 R/W 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 OCF 0 R/W 18 0 R 2 0 R 17 0 R 1 WT 0 R/W 16 0 R 0 OCE 0 R/W
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Section 8 Cache
Bit 31 to 12
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Flush Writing 1 flushes all instruction cache entries (clears the V and LRU bits of all instruction cache entries to 0). Always reads 0. Write-back to external memory is not performed when the instruction cache is flushed. Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Enable Indicates whether the instruction cache function is enabled or disabled. 0: Instruction cache disabled 1: Instruction cache enabled
11
ICF
0
R/W
10, 9
All 0
R
8
ICE
0
R/W
7 to 4
All 0
R
3
OCF
0
R/W
2
0
R
1
WT
0
R/W
Reserved These bits are always read as 0. The write value should always be 0. Operand Cache Flush Writing 1 flushes all operand cache entries (clears the V, U, and LRU bits of all operand cache entries to 0). Always reads 0. Write-back to external memory is not performed when the operand cache is flushed. Reserved This bit is always read as 0. The write value should always be 0. Write Through Selects write-back mode or write-through mode. 0: Write-back mode 1: Write-through mode
0
OCE
0
R/W
Operand Cache Enable Indicates whether the operand cache function is enabled or disabled. 0: Operand cache disabled 1: Operand cache enabled
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Section 8 Cache
8.2.2
Cache Control Register 2 (CCR2)
CCR2 is used to enable or disable the cache locking function for operand cache and is valid in cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to 1. In non-cache-locking mode, the cache locking function is invalid. When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF @Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The relationship between the setting of each bit and a way, to be replaced when the prefetch instruction is executed, are listed in table 8.3. On the other hand, when the prefetch instruction is executed and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1 specified in cache locking mode while one-line data already exists in way 0 which is specified by Rn, a cache hit occurs and data is not fetched to way 3. In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in CCR2 and ways to be replaced are listed in table 8.4. Programs that change the contents of CCR2 should be placed in an address space that is not cached, and an address space that is cached should be accessed after reading the contents of CCR2. CCR2 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a manual reset or in software standby mode.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 24 0 R 8 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 16 LE 0 R/W 0
W3 W3 LOAD* LOCK
W2 W2 LOAD* LOCK
0 R/W
0 R/W
0 R/W
0 R/W
Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
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Section 8 Cache
Bit 31 to 17
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
16
LE
0
R/W
Lock Enable Enables or disables the cache locking function. 0: Non-cache locking mode 1: Cache locking mode
15 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9 8
W3LOAD* W3LOCK
0 0
R/W R/W
Way 3 Load Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD = 1 and W3LOCK = 1 in cache locking mode, the data is always loaded into way 3. Under any other condition, the cache miss data is loaded into the way to which LRU points.
7 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1 0
W2LOAD* W2LOCK
0 0
R/W R/W
Way 2 Load Way 2 Lock When a cache miss occurs by the prefetch instruction while W2LOAD = 1 and W2LOCK =1 in cache locking mode, the data is always loaded into way 2. Under any other condition, the cache miss data is loaded into the way to which LRU points.
Note:
*
The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
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Section 8 Cache
Table 8.3
LE 0 1 1 1 1 1 1
Way to be Replaced when a Cache Miss Occurs in PREF Instruction
W3LOAD* x x x 0 0 0 1 W3LOCK x 0 0 1 1 x 1 W2LOAD* x x 0 x 0 1 0 W2LOCK x 0 1 0 1 1 x Way to be Replaced Decided by LRU (table 8.1) Decided by LRU (table 8.1) Decided by LRU (table 8.5) Decided by LRU (table 8.6) Decided by LRU (table 8.7) Way 2 Way 3
[Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Table 8.4
LE 0 1 1 1 1
Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction
W3LOAD* x x x x x W3LOCK x 0 0 1 1 W2LOAD* x x x x x W2LOCK x 0 1 0 1 Way to be Replaced Decided by LRU (table 8.1) Decided by LRU (table 8.1) Decided by LRU (table 8.5) Decided by LRU (table 8.6) Decided by LRU (table 8.7)
[Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time.
Table 8.5
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0)
Way to be Replaced 3 1 0
LRU (Bits 5 to 0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
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Section 8 Cache
Table 8.6
LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1)
Way to be Replaced 2 1 0
LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Table 8.7
LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
Way to be Replaced 1 0
LRU (Bits 5 to 0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
8.3
Operation
Operations for the operand cache are described here. Operations for the instruction cache are similar to those for the operand cache except for the address array not having the U bit, and there being no prefetch operation or write operation, or a write-back buffer. 8.3.1 Searching Cache
If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is accessed, the cache will be searched to see if the desired data is in the cache. Figure 8.2 illustrates the method by which the cache is searched. Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits 31 to 11 of the address used to access memory are compared with the read tag address. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 8.2 shows a hit on way 1.
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Section 8 Cache
Access address 31 11 10 4 3 210
Entry selection Address array (ways 0 to 3)
Longword (LW) selection Data array (ways 0 to 3)
Entry 0 Entry 1
V
U Tag address
Entry 0 Entry 1
LW0
LW1
LW2
LW3
. . . . . . . . .
Entry 127
. . . . . . . . .
Entry 127
CMP0 CMP1 CMP2 CMP3
Hit signal (way 1) [Legend] CMP0 to CMP3: Comparison circuits 0 to 3
Figure 8.2 Cache Search Scheme
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Section 8 Cache
8.3.2 (1)
Read Access Read Hit
In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. (2) Read Miss
An external bus cycle starts and the entry is updated. The way replaced follows table 8.4. Entries are updated in 16-byte units. When the desired data that caused the miss is loaded from external memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. 8.3.3 (1) Prefetch Operation (Only for Operand Cache) Prefetch Hit
LRU is updated so that the hit way becomes the latest. The contents in other caches are not modified. No data is transferred to the CPU. (2) Prefetch Miss
No data is transferred to the CPU. The way to be replaced follows table 8.3. Other operations are the same in case of read miss. 8.3.4 (1) Write Operation (Only for Operand Cache) Write Hit
In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit way becomes the latest. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way becomes the latest.
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Section 8 Cache
(2)
Write Miss
In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is updated. The way to be replaced follows table 8.4. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 8.3.5 Write-Back Buffer (Only for Operand Cache)
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 8.3 shows the configuration of the write-back buffer.
A (31 to 4)
Longword 0
Longword 1
Longword 2
Longword 3
A (31 to 4): Physical address written to external memory (upper three bits are 0) Longword 0 to 3: One line of cache data to be written to external memory
Figure 8.3 Write-Back Buffer Configuration Operations in sections 8.3.2 to 8.3.5 are compiled in table 8.8
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Section 8 Cache
Table 8.8
Cache Operations
External Memory Hit/ Write-back mode/ write through mode Accession U Bit (through internal bus) Not generated Cache Contents Not renewed
Cache Instruction cache
CPU Cycle Instruction fetch
miss Hit
Miss
Cache renewal cycle is generated.
Renewed to new values by cache renewal cycle Not renewed
Operand cache
Prefetch/ read
Hit
Either mode is available x
Not generated
Miss
Write-through mode
Cache renewal cycle is generated.
Renewed to new values by cache renewal cycle Renewed to new values by cache renewal cycle Renewed to new values by cache renewal cycle
Write-back mode
0
Cache renewal cycle is generated
1
Cache renewal cycle is generated. Succeedingly write-back cycle in writeback buffer is generated
Write
Hit
Write-through mode
Write cycle CPU issues is Renewed to new values by generated. write cycle the CPU issues Renewed to new values by write cycle the CPU issues
Write-back mode
x
Not generated
Miss
Write-through mode
Write cycle CPU issues is Not renewed* generated.
Write-back mode
0
Cache renewal cycle is generated.
Renewed to new values by cache renewal cycle. Subsequently renewed again to new values in write cycle CPU issues.
1
Cache renewal cycle is generated. Succeedingly write-back cycle in writeback buffer is generated
Renewed to new values by cache renewal cycle. Subsequently renewed again to new values in write cycle CPU issues.
[Legend] x: Don't care Note: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte write access * Neither LRU renewed. LRU is renewed in all other cases.
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Section 8 Cache
8.3.6
Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is mapped in the address space to be cached, operate the memory-mapped cache to invalidate and write back as required.
8.4
Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 8.4.1 Address Array
To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. In the address field, specify the entry address selecting the entry, the W bit for selecting the way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is fixed at longword, specify B'00 for bits 1 and 0 of the address. The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always specify 0 for the upper three bits (bits 31 to 29) of the tag address. For the address and data formats, see figure 8.4. The following three operations are possible for the address array. (1) Address Array Read
The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry address specified by the address and the entry corresponding to the way. For the read operation, associative operation is not performed regardless of whether the associative bit (A bit) specified by the address is 1 or 0.
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Section 8 Cache
(2)
Address-Array Write (Non-Associative Operation)
When the associative bit (A bit) in the address field is cleared to 0, write the tag address, LRU bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address specified by the address and the entry corresponding to the way. When writing to a cache line for which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. (3) Address-Array Write (Associative Operation)
When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field are compared with the tag address that is specified by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that has a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. 8.4.2 Data Array
To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. Specify the entry address for selecting the entry, the L bit indicating the longword position within the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword, specify B'00 for bits 1 and 0 of the address. For the address and data formats, see figure 8.4. The following two operations are possible for the data array. Information in the address array is not modified by this operation.
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Section 8 Cache
(1)
Data Array Read
The data specified by the L bit in the address is read from the entry address specified by the address and the entry corresponding to the way. (2) Data Array Write
The longword data specified by the data is written to the position specified by the L bit in the address from the entry address specified by the address and the entry corresponding to the way.
1. Instruction cache 1.1 Address array access (a) Address specification Read access 31 23 22 13 12 11 10 W 4 Entry address 3 0 2 * 1 0 0 0 2. Operand cache 2.1 Address array access (a) Address specification Read access 31 23 22 13 12 11 10 W Entry address 4 3 0 2 * 1 0 0 0 111100001 *----------* Write access 31 23 22
111100000 *----------* Write access 31 23 22
13 12 11 10 W
4 Entry address
3 A
2 *
1 0
0 0
13 12 11 10 W Entry address
4
3 A
2 *
1 0
0 0
111100000 *----------*
111100001 *----------*
(b) Data specification (both read and write accesses) 43 31 29 28 11 10 9 0 0 0 Tag address (28 to 11) E LRU X
2 X
1 X
0 V
(b) Data specification (both read and write accesses) 43 31 29 28 11 10 9 0 0 0 Tag address (28 to 11) E LRU X
2 X
1 U
0 V
1.2 Data array access (both read and write accesses) (a) Address specification 31 23 22 13 12 11 10 W 4 3 L 2 1 0 0 0
2.2 Data array access (both read and write accesses) (a) Address specification 31 23 22 13 12 11 10 W Entry address 4 3 L 2 1 0 0 0
111100010 *----------* (b) Data specification 31
Entry address
111100011 *----------* (b) Data specification
0 Longword data
31 Longword data
0
[Legend] *: Don't care E: Bit 10 of entry address for read, don't care for write X: 0 for read, don't care for write
Figure 8.4 Specifying Address and Data for Memory-Mapped Cache Access
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Section 8 Cache
8.4.3 (1)
Usage Examples Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. An example when a write data is specified in R0 and an address is specified in R1 is shown below.
; R0=H'0110 0010; tag address(28-11)=B'0 0001 0001 0000 0000 0, U=0, V=0 ; R1=H'F080 0088; operand cache address array access, entry=B'000 1000, A=1 ; MOV.L R0,@R1
(2)
Reading the Data of a Specific Entry
The data section of a specific cache entry can be read by the memory mapping cache access. The longword indicated in the data field of the data array in figure 8.4 is read into the register. An example when an address is specified in R0 and data is read in R1 is shown below.
; R0=H'F100 004C; instruction cache data array access, entry=B'000 0100, ; Way=0, longword address=3 ; MOV.L @R0,R1
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Section 8 Cache
8.4.4
Notes
1. Programs that access memory-mapped cache should be placed in an address space that is not cached. 2. Rewriting the address array contents so that two or more ways are hit simultaneously is prohibited. Operation is not guaranteed if the address array contents are changed so that two or more ways are hit simultaneously. 3. Memory-mapped cache can be accessed only by the CPU and not by the DMAC. Registers can be accessed by the CPU and the DMAC.
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Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. This enables the LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1
Features
1. External address space * A maximum of 64 Mbytes for the SDRAM and each for areas CS0 to CS6 (256 Mbytes for CS6) * Ability to select the data bus width (8, 16, or 32 bits) independently for each address space 2. Normal space interface * Supports an interface for direct connection to SRAM * Cycle wait function: Maximum of 31 wait states (maximum of seven wait states for page access cycles) * Wait control Ability to select the assert/negate timing for chip select signals Ability to select the assert/negate timing for the read strobe and write strobe signals Ability to select the data output start/end timing Ability to select the delay for chip select signals * Write access modes: One-write strobe and byte-write strobe modes * Page access mode: Support for page read and page write (64-bit, 128-bit, and 256-bit page units) 3. SDRAM interface * Ability to set SDRAM in up to two areas * Refresh functions Auto-refresh (on-chip programmable refresh counter) Self-refresh * Ability to select the access timing (support for low column latency, column latency, and low active interval settings) * Initialization sequencer function, power-down function, deep-power-down function, and mode register setting function implemented on-chip Figure 9.1 shows a block diagram of the BSC.
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Section 9 Bus State Controller (BSC)
CS6 to CS0 RD WR3 to WR0 WAIT
Area controller (CSC)
CSMODn CS1WCNTn CS2WCNTn
Internal bus
A27 to A0 BC3 to BC0 D31 to D0
Access controller
CSnCNT CSnREC SDCmCNT
SDCS1, SDCS0 SDRAS, SDCAS SDWE, SDCKE DQM3 to DQM0
SDRAM controller (SDRAMC)
SDRFCNT0/1 SDIR0/1 SDmADR SDmTR SDmMOD
SDPWDCNT SDDPWDCNT SDSTR SDCKSCNT
[Legend] CSMODn: CS1WCNTn: CS2WCNTn: CSnCNT: CSnREC: SDCmCNT: SDRFCNT0/1: SDIR0/1: SDmADR: SDmTR: SDmMOD: SDPWDCNT: SDDPWDCNT: SDSTR: SDCKSCNT:
CSn mode register CSn wait control register 1 CSn wait control register 2 CSn control register CSn recovery cycle setting register SDRAMCm control register SDRAM refresh control register 0/1 SDRAM initialization register 0/1 SDRAMm address register SDRAMm timing register SDRAMm mode register SDRAM power-down control register SDRAM deep-power-down control register SDRAM status register SDRAM clock stop control signal setting register
Note: n = 0 to 6, m = 0 and 1
Figure 9.1 Block Diagram of BSC
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Section 9 Bus State Controller (BSC)
9.2
Input/Output Pins
Table 9.1 shows the pin configuration of the BSC. Table 9.1
Name A27 to A0 D31 to D0 CS6 to CS0 RD WR3 WR2 WR1
Pin Configuration
I/O Output I/O Output Output Output Output Output Function Address bus Data bus Chip select Read pulse signal (read data output enable signal) When accessing the 32-bit bus area, indicates that D31 to D24 are being written to in byte-write mode. When accessing the 32-bit bus area, indicates that D23 to D16 are being written to in byte-write mode. When accessing the 32-bit bus area, indicates that D15 to D8 are being written to in byte-write mode. When accessing the 16-bit bus area, indicates that D15 to D8 are being written to in byte-write mode.
WR0 BC3 BC2 BC1
Output Output Output Output
When accessing the 8-bit bus area, indicates that D7 to D0 are being written to in byte-write mode. When accessing the 32-bit bus area, indicates that D31 to D24 are being accessed in byte-access mode. When accessing the 32-bit bus area, indicates that D23 to D16 are being written to in byte-write mode. When accessing the 32-bit bus area, indicates that D15 to D8 are being accessed in byte-access mode. When accessing the 16-bit bus area, indicates that D15 to D8 are being accessed in byte-access mode.
BC0 SDCS1, SDCS0 SDRAS SDCAS SDWE
Output Output Output Output Output
When accessing the 8-bit bus area, indicates that D7 to D0 are being accessed in byte-access mode. Connects to CS pin when SDRAM is connected. Connects to RAS pin when SDRAM is connected. Connects to CAS pin when SDRAM is connected. Connects to WE pin when SDRAM is connected.
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Section 9 Bus State Controller (BSC)
Name SDCKE DQM3 DQM2 DQM1 DQM0
I/O Output Output Output Output Output
Function Connects to CKE pin when SDRAM is connected. Connects to DQMUU pin when SDRAM is connected by 32-bit SDRAM. Connects to DQMUL pin when SDRAM is connected by 32-bit SDRAM. Connects to DQMLU pin when SDRAM is connected by 32-bit bus. Connects to DQMU pin when SDRAM is connected by 16-bit bus. Connects to DQMLL pin when SDRAM is connected by 32-bit bus. Connects to DQML pin when SDRAM is connected by 16-bit bus. Connects to DQM pin when SDRAM is connected by 8-bit bus.
WAIT
Input
External wait input
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Section 9 Bus State Controller (BSC)
9.3
9.3.1
Area Overview
Address Map
In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cachedisabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address. External address spaces CS5 to CS0 are cache-enabled when internal address A29 = 0 and cachedisabled when A29 = 1. The CS6 space is always cache-disabled. The kind of memory to be connected and the data bus width are specified independently for each partial space. The address map for the external address space is listed below. Table 9.2 Address Map
Space CS0 CS1 SDRAM0 SDRAM1 CS2 CS3 CS4 CS5 CS0 CS1 SDRAM0 SDRAM1 CS2 CS3 CS4 CS5 Memory to be Connected Normal space Normal space SDRAM SDRAM Normal space Normal space Normal space Normal space Normal space Normal space SDRAM SDRAM Normal space Normal space Normal space Normal space Cachedisabled Cache Cacheenabled
Internal Address H'00000000 to H'03FFFFFF H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF H'0C000000 to H'0FFFFFFF H'10000000 to H'13FFFFFF H'14000000 to H'17FFFFFF H'18000000 to H'1BFFFFFF H'1C000000 to H'1FFFFFFF H'20000000 to H'23FFFFFF H'24000000 to H'27FFFFFF H'28000000 to H'2BFFFFFF H'2C000000 to H'2FFFFFFF H'30000000 to H'33FFFFFF H'34000000 to H'37FFFFFF H'38000000 to H'3BFFFFFF H'3C000000 to H'3FFFFFFF
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Section 9 Bus State Controller (BSC)
Internal Address H'40000000 to H'4FFFFFFF H'50000000 to H'E7FFFFFF H'E8000000 to H'EFFFFFFF H'F0000000 to H'FF3FFFFF H'FF400000 to H'FFF7FFFF H'FFF80000 to H'FFFBFFFF H'FFFC0000 to H'FFFFFFFF Note: *
Space CS6 Other Other Other Other Other Other
Memory to be Connected Normal space Reserved area* On-chip peripheral modules, reserved area* Cache address array space, reserved area* On-chip peripheral modules, reserved area* On-chip RAM, reserved area* On-chip peripheral modules, reserved area*
Cache Cachedisabled -- -- -- -- -- --
For the on-chip RAM space, access the addresses shown in section 26, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 30, List of Registers. Do not access addresses which are not described in these sections. Otherwise, correct operation cannot be guaranteed.
9.3.2
Data Bus Width and Pin Function Setting for Individual Areas
In this LSI the data bus width of area 0 can be set to 8, 16, or 32 bits through external pins during a power-on reset. The data bus widths of areas 1 to 6 can be modified through register settings during program execution. Note that the selectable data bus widths may be limited depending on the connected memory type. After a power-on reset, the LSI starts execution of the program stored in the external memory allocated in area 0. For details on pin function settings, see section 25, Pin Function Controller (PFC). Table 9.3
MD1 1
Correspondence between External Pin (MD1 and MD0) Settings and Data Bus Width
MD0 1 0 Data Bus Width 32 bits 16 bits 8 bits Reserved (setting prohibited)
0
1 0
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Section 9 Bus State Controller (BSC)
9.4
Register Descriptions
The BSC has the following registers. All registers are initialized by a power-on reset or in deep standby mode. Do not access spaces other than area 0 until settings are completed for the connected memory interface. Table 9.4 Register Configuration
Abbreviation CS0CNT R/W R/W Initial Value H'00010000/ H'00110000/ H'00210000* CS0 recovery cycle setting register CS1 control register CS1 recovery cycle setting register CS2 control register CS2 recovery cycle setting register CS3 control register CS3 recovery cycle setting register CS4 control register CS4 recovery cycle setting register CS5 control register CS5 recovery cycle setting register CS6 control register CS6 recovery cycle setting register CS0REC CS1CNT CS1REC CS2CNT CS2REC CS3CNT CS3REC CS4CNT CS4REC CS5CNT CS5REC CS6CNT CS6REC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'FF420008 H'FF420010 H'FF420018 H'FF420020 H'FF420028 H'FF420030 H'FF420038 H'FF420040 H'FF420048 H'FF420050 H'FF420058 H'FF420060 H'FF420068 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 Address H'FF420000 Access Size 8, 16, 32
Register Name CS0 control register
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Section 9 Bus State Controller (BSC)
Register Name SDRAMC0 control register SDRAMC1 control register CS0 mode register CS0 wait control register 1 CS0 wait control register 2 CS1 mode register CS1 wait control register 1 CS1 wait control register 2 CS2 mode register CS2 wait control register 1 CS2 wait control register 2 CS3 mode register CS3 wait control register 1 CS3 wait control register 2 CS4 mode register CS4 wait control register 1 CS4 wait control register 2 CS5 mode register CS5 wait control register 1 CS5 wait control register 2 CS6 mode register CS6 wait control register 1 CS6 wait control register 2 SDRAM refresh control register 0 SDRAM refresh control register 1
Abbreviation SDC0CNT SDC1CNT CSMOD0 CS1WCNT0 CS2WCNT0 CSMOD1 CS1WCNT1 CS2WCNT1 CSMOD2 CS1WCNT2 CS2WCNT2 CSMOD3 CS1WCNT3 CS2WCNT3 CSMOD4 CS1WCNT4 CS2WCNT4 CSMOD5 CS1WCNT5 CS2WCNT5 CSMOD6 CS1WCNT6 CS2WCNT6 SDRFCNT0 SDRFCNT1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value H'00000000 H'00000000 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'1F1F0707 H'00000007 H'00000000 H'0000xxxx H'00000xxx H'00000000
Address H'FF420100 H'FF420110 H'FF421000 H'FF421004 H'FF421008 H'FF421010 H'FF421014 H'FF421018 H'FF421020 H'FF421024 H'FF421028 H'FF421030 H'FF421034 H'FF421038 H'FF421040 H'FF421044 H'FF421048 H'FF421050 H'FF421054 H'FF421058 H'FF421060 H'FF421064 H'FF421068 H'FF422000 H'FF422004 H'FF422008 H'FF42200C
Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32
SDRAM initialization register 0 SDIR0 SDRAM initialization register 1 SDIR1
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Section 9 Bus State Controller (BSC)
Register Name SDRAM power-down control register SDRAM deep-power-down control register SDRAM0 address register SDRAM0 timing register SDRAM0 mode register SDRAM1 address register SDRAM1 timing register SDRAM1 mode register SDRAM status register SDRAM clock stop control signal setting register AC characteristics switching register Note: *
Abbreviation SDPWDCNT
R/W R/W
Initial Value H'00000000 H'00000000 H'00000x0x H'000xxx0x H'0000xxxx H'00000x0x H'000xxx0x H'0000xxxx H'00000000 H'0000000F H'00000000
Address H'FF422010 H'FF422014 H'FF422020 H'FF422024 H'FF422028 H'FF422040 H'FF422044 H'FF422048 H'FF4220E4 H'FF4220E8
Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32
SDDPWDCNT R/W SD0ADR SD0TR SD0MOD SD1ADR SD1TR SD1MOD SDSTR SDCKSCNT ACSWR R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'FFFD8808 8, 16, 32
Depends on the setting of the MD pin.
9.4.1
CSn Control Register (CSnCNT) (n = 0 to 6)
CSnCNT selects the width of the external bus and controls the operation of the CSC interface.
Bit: 31 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 20 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16
EXENB
BSIZE[1:0] 0*1 0 *1 R/W R/W 5 -- 0 R 4 -- 0 R
0 *2 R/W 0 -- 0 R
Bit: 15 -- Initial value: R/W: 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 22
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Section 9 Bus State Controller (BSC)
Bit 21, 20
Bit Name BSIZE[1:0]
Initial Value 00*
1
R/W R/W
Description External Bus Width Select These bits specify the width of the data bus for the external device of the corresponding channel of CSC. The initial value for the data bus width for CSC channel 0 (CS0) differs depending on the settings of pins MD1 and MD0. 10: 8-bit bus 00: 16-bit bus 01: 32-bit bus
19 to 17
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
16
EXENB
0*2
R/W
Operation Enable This bit enables or disables the operation for the corresponding channel of CSC. The initial value corresponding to CS0 only is operation enabled (EXENB = 1). 0: Operation disabled 1: Operation enabled
15 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Notes: 1. The initial value of the BSIZE bits in CS0 differs depending on the settings of pins MD1 and MD0. 2. The initial value of the EXENB bit in CS0 is 1.
To disable the operation for each channel, forcibly write out data tentatively stored in internal write buffer. The procedure is as follows: 1. Execute read access to the channel whose operation is to be disabled. 2. Then, write 0 to the EXENB bit (operation disabled).
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Section 9 Bus State Controller (BSC)
9.4.2
CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6)
CSnREC specifies the number of data recovery cycles to be inserted after read or write accesses.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 0 R/W 11 -- 0 R 27 26 25 24 23 -- 0 R/W 8 -- 0 R 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 0 R/W 3 -- 0 R 19 18 17 16
WRCV[3:0] 0 R/W 10 -- 0 R 0 R/W 9 -- 0 R
RRCV[3:0] 0 R/W 2 -- 0 R 0 R/W 1 -- 0 R 0 R/W 0 -- 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
27 to 24 WRCV[3:0]
0000
R/W
Post-Write Data Recovery Cycle Setting These bits specify the number of data recovery cycles to be inserted after write accesses to the external bus. If a value other than 0 is selected, between 1 and 15 data recovery cycles are inserted when a write access to the external bus is followed by a read access to the external bus. (Data recovery cycles are inserted even when access is performed sequentially to the same CSC channel.) Note that if idle cycles occur between accesses to the external bus, the number of data recovery cycles inserted is reduced by the number of idle cycles. 0000: 0 cycle 0001: 1 cycles : 1111: 15 cycles
23 to 20
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial Value 0000
R/W R/W
Description Post-Read Data Recovery Cycle Setting These bits specify the number of data recovery cycles to be inserted after read accesses to the external bus. If a value other than 0 is selected, data recovery cycles are inserted in the following cases: If a read access to the external bus is followed by a write access to the external bus. (Data recovery cycles are inserted even when access is performed sequentially to the same CSC channel.) If a read access to the external bus is followed by a read access to a different CSC channel. (No data recovery cycles are inserted in cases of sequential read accesses to the same CSC channel.) Note that if idle cycles occur between accesses to the external bus, the number of data recovery cycles inserted is reduced by the number of idle cycles. 0000: 0 cycle 0001: 1 cycles : 1111: 15 cycles
19 to 16 RRCV[3:0]
15 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Notes: 1. When accessing SDRAM, there is no danger of data collision on the bus due to timing. Consequently, there is no data recovery cycle setting for SDRAM. (The value is fixed at 0 cycles.) 2. Writing to the CSn recovery cycle setting register (CSnREC) must be done while CSC for the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1 between the reset release and data write access to CS0.
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Section 9 Bus State Controller (BSC)
9.4.3
SDRAMCm Control Register (SDCmCNT) (m = 0, 1)
Bit: 31 -- 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 20 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16
EXENB
BSIZE[1:0] 0 R/W 5 -- 0 R 0 R/W 4 -- 0 R
Initial value: R/W: Bit:
0 R 15 --
0 R/W 0 -- 0 R
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 22
21, 20
BSIZE[1:0]
00
R/W
External Bus Width Select These bits specify the width of the data bus for the external device of the corresponding channel of CSC. 10: 8-bit bus 00: 16-bit bus 01: 32-bit bus
19 to 17
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
16
EXENB
0
R/W
Operation Enable This bit enables or disables the operation for the corresponding channel of CSC. 0: Operation disabled 1: Operation enabled
15 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
To disable the operation for each channel, forcibly write out data tentatively stored in internal write buffer. The procedure is as follows: 1. Execute read access to the channel whose operation is to be disabled. 2. Then, write 0 to the EXENB bit (operation disabled). 9.4.4 CSn Mode Register (CSMODn) (n = 0 to 6)
CSMODn selects the mode for page read access and the bit boundary for page access, enables page read/write access and external wait, and selects the mode for write access.
Bit: 31
PR MOD
30 -- 0 R 14 -- 0 R
29
28
27 -- 0 R 11 -- 0 R
26 -- 0 R 10 -- 0 R
25
PW ENB
24
PR ENB
23 -- 0 R 7 -- 0 R
22 -- 0 R 6 -- 0 R
21 -- 0 R 5 -- 0 R
20 -- 0 R 4 -- 0 R
19
EW ENB
18 -- 0 R 2 -- 0 R
17 -- 0 R 1 -- 0 R
16
WR MOD
PBCNT[1:0] 0 R/W 13 -- 0 R 0 R/W 12 -- 0 R
Initial value: 0 R/W: R/W Bit: 15 -- Initial value: R/W: 0 R
0 R/W 9 -- 0 R
0 R/W 8 -- 0 R
0 R/W 3 -- 0 R
0 R/W 0 -- 0 R
Bit 31
Bit Name PRMOD
Initial Value 0
R/W R/W
Description Page Read Access Mode Select This bit selects the operating mode for page read access. Clearing PRMOD to 0 selects the normal access compatible mode. In this mode the RD signal is negated each time a unit of data is read and an RD assert wait is inserted. Setting PRMOD to 1 selects the external data read sequential assert mode. In this mode RD is asserted continuously between page accesses. 0: Normal access compatible mode 1: External data read sequential assert mode
30
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit 29, 28
Bit Name
Initial Value
R/W R/W
Description Page Access Bit Boundary Select These bits select the bit boundary for page access operation. When the bit boundary specified by PBCNT is exceeded during page access, page access operation is halted temporarily (the CSn signal is negated), and then page access operation begins again. The value written to these bits is valid only when either of the PWENB bit or the PRENB bit is set to 1. 00: 64-bit boundary 01: 128-bit boundary 10: 256-bit boundary 11: Setting prohibited
PBCNT[1:0] 00
27, 26
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
25
PWENB
0
R/W
Page Write Access Enable This bit is used to enable page write access. 0: Page write access disabled 1: Page write access enabled
24
PRENB
0
R/W
Page Read Access Enable This bit is used to enable page read access. 0: Page write access disabled 1: Page write access enabled
23 to 20
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit 19
Bit Name EWENB
Initial Value 0
R/W R/W
Description External Wait Enable This bit is used to enable or disable external wait input. When EWENB is set to 1, external wait input is enabled and the number of wait states per cycle can be controlled using the external wait signal (WAIT). In this case wait cycles are inserted while the WAIT signal is low level. When EWENB is cleared to 0, the WAIT signal is invalid. 0: External wait disabled 1: External wait enabled
18, 17
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
16
WRMOD
0
R/W
Write Access Mode Select This bit selects the operating mode for write access. Clearing WRMOD to 0 selects the byte-write strobe mode. In this mode data writes are controlled by multiple write signals (WR3 to WR0) that correspond to the individual byte positions. Setting WRMOD to 1 selects the one-write strobe mode. In this mode, data writes are controlled by multiple byte control signals (BC3 to BC0) that correspond to the individual byte positions and a single write signal (WR0 for the 8-bit bus width channel, WR1 for the 16-bit bus width channel, and WR3 for the 32-bit bus width channel) 0: Byte-write strobe mode 1: One-write strobe mode
15 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Writing to the CSn mode register (CSMODn) must be done while CSC for the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1 between the reset release and data write access to CS0.
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Section 9 Bus State Controller (BSC)
9.4.5
CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6)
CS1WCNTn specifies the number of wait states inserted into the read/write cycle or page read/page write cycle.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 1 R/W 12 -- 0 R 28 27 26 25 24 23 -- 1 R/W 8 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 1 R/W 4 -- 0 R 20 19 18 17 16
CSRWAIT[4:0] 1 R/W 11 -- 0 R 1 R/W 10 1 R/W 9
CSWWAIT[4:0] 1 R/W 3 -- 0 R 1 R/W 2 1 R/W 1 1 R/W 0
CSPRWAIT[2:0] 1 R/W 1 R/W 1 R/W
CSPWWAIT[2:0] 1 R/W 1 R/W 1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 29
28 to 24 CSRWAIT [4:0]
11111
R/W
Read Cycle Wait Select These bits specify the number of wait states inserted into the initial normal read cycle and page read cycle. 00000: 0 wait states : 11111: 31 wait states
23 to 21
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
20 to 16 CSWWAIT [4:0]
11111
R/W
Write Cycle Wait Select These bits specify the number of wait states inserted into the initial normal write cycle and page write cycle. 00000: 0 wait states : 11111: 31 wait states
15 to 11
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit 10 to 8
Bit Name
Initial Value
R/W R/W
Description Page Read Cycle Wait Select These bits specify the number of wait states inserted into the second and subsequent page read cycles. This setting is valid when the page read access enable bit (PRENB) is set to 1. 000: 0 wait state : 111: 7 wait states
CSPRWAIT 111 [2:0]
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
CSPWWAIT 111 [2:0]
R/W
Page Write Cycle Wait Select These bits specify the number of wait states inserted into the second and subsequent page write cycles. This setting is valid when the page write access enable bit (PWENB) is set to 1. 000: 0 wait state : 111: 7 wait states
Notes: 1. Make sure the page read and page write cycle wait select (CSPRWAIT and CSPWWAIT) settings are within the range defined by the read and write cycle wait select (CSRWAIT and CSWWAIT) settings. Select each wait cycle number according the system configuration incorporated. 2. Writing to the CSn wait control register 1 (CS1WCNTn) must be done while CSC for the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1 between the reset release and data write access to CS0.
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Section 9 Bus State Controller (BSC)
9.4.6
CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6)
CS2WCNTn specifies the number of wait states and the number of delay cycles.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 29 CSON[2:0] 0 R/W 14 -- 0 R 0 R/W 13 -- 0 R 0 R/W 12 -- 0 R 28 27 -- 0 R 11 -- 0 R 26 25 WDON[2:0] 0 R/W 10 0 R/W 9 0 R/W 8 24 23 -- 0 R 7 -- 0 R 22 21 WRON[2:0] 0 R/W 6 0 R/W 5 0 R/W 4 20 19 -- 0 R 3 -- 0 R 18 17 RDON[2:0] 0 R/W 2 0 R/W 1 0 R/W 0 16
WDOFF[2:0] 0 R/W 0 R/W 0 R/W
CSWOFF[2:0] 0 R/W 0 R/W 0 R/W
CSROFF[2:0] 1 R/W 1 R/W 1 R/W
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30 to 28 CSON [2:0]
000
R/W
CS Assert Wait Select These bits specify the number of wait states inserted before the external chip select signal (CSn) is asserted. 000: 0 wait state : 111: 7 wait states
27
0
R
Reserved This bit is always read as 0. The write value should always be 0.
26 to 24 WDON [2:0]
000
R/W
Write Data Output Wait Select These bits specify the number of wait states inserted before data is output to the external data bus. 000: 0 wait state : 111: 7 wait states
23
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial Value 000
R/W R/W
Description WR Assert Wait Select These bits specify the number of wait states inserted before the external data write signal (WR3 to WR0) is asserted. 000: 0 wait state : 111: 7 wait states
22 to 20 WRON [2:0]
19
0
R
Reserved This bit is always read as 0. The write value should always be 0.
18 to 16 RDON [2:0]
000
R/W
RD Assert Wait Select These bits specify the number of wait states inserted before the external data read signal (RD) is asserted. 000: 0 wait state : 111: 7 wait states
15 to 11
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
10 to 8
WDOFF [2:0]
000
R/W
Write Data Output Delay Cycle Select These bits specify the number of cycles from the end of the wait cycle during write operation (negation of the WR3 to WR0 signals) and the negation of the external data bus. 000: 0 wait state : 111: 7 wait states
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit 6 to 4
Bit Name CSWOFF [2:0]
Initial Value 000
R/W R/W
Description Write Operation CS Delay Cycle Select These bits specify the number of cycles from the end of the wait cycle during write access operation (negation of the WR3 to WR0 signals) and the negation of the CS6 to CS0 signal. 000: 0 wait state : 111: 7 wait states
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2 to 0
CSROFF [2:0]
111
R/W
Read Operation CS Delay Cycle Select These bits specify the number of cycles from the end of the wait cycle during read access operation (negation of the RD signal) and the negation of the CS6 to CS0 signal. 000: 0 wait state : 111: 7 wait states
Notes: 1. Select each wait cycle number or extended cycle number according the system configuration incorporated. 2. Writing to the CSn wait control register 2 (CS2WCNTn) must be done while CSC for the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1 between the reset release and data write access to CS0. 3. Each bit must be set under the following restrictions. * When page access is disabled (PRENB, PWENB = 0) CSON min (CSRWAIT, CSWWAIT), WDON CSWWAIT WRON CSWWAIT, RDON CSRWAIT WDOFF CSWOFF * When page access is enabled (PRENB = 1 or PWENB = 1) In addition to the restrictions for disabled page access case, the following restrictions are required. CSON min (CSPRWAIT, CSPWWAIT) WRON CSPWWAIT, RDON CSPRWAIT WDON CSPWWAIT
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Section 9 Bus State Controller (BSC)
9.4.7
SDRAM Refresh Control Register 0 (SDRFCNT0)
SDRFCNT0 controls self-refresh operation.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0
DSFEN
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
DSFEN
0
R/W
SDRAM Common Self-Refresh Operation Enable This bit controls self-refresh operation for all channels simultaneously. Setting DSFEN to 1 performs autorefresh cycle operation, immediately after which selfrefresh operation begins. Clearing DSFEN to 0 ends self-refresh operation, and auto-refresh operation resumes immediately afterward. The value written to this bit is reflected when self-refresh operation starts, if DSFEN was set to 1, or when auto-refresh operation starts following the end of self-refresh operation, if DSFEN was cleared to 0. 0: Self-refresh disabled 1: Self-refresh enabled
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Section 9 Bus State Controller (BSC)
9.4.8
SDRAM Refresh Control Register 1 (SDRFCNT1)
SDRFCNT1 controls auto-refresh operation.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 30 -- 0 R 14 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 22 -- 0 R 6 21 -- 0 R 5 20 -- 0 R 4 19 -- 0 R 3 18 -- 0 R 2 17 -- 0 R 1 16
DRFEN
0 R/W 0
DREFW[3:0] Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W
DRFC[11:0] -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 17
16
DRFEN
0
R/W
Auto-Refresh Operation Enable This bit controls auto-refresh operation for all channels simultaneously. When DRFEN is cleared to 0, autorefresh operation does not take place. Auto-refresh operates when DRFEN is set to 1. Clearing this bit to 0 while auto-refresh is enabled causes DRFEN to be cleared to 0, and auto-refresh operation to halt, after the end of the next auto-refresh cycle. Setting this bit to 1 while auto-refresh is enabled causes auto-refresh operation to commence as soon as DRFEN is set to 1, and refresh requests are then generated at fixed intervals determined by a counter. The interval at which refresh requests are generated is determined by the set value of the auto-refresh request interval setting (DRFC) bits. Refresh requests are not accepted while SDRAM is being accessed; they must wait until the access completes. If a SDRAM access and refresh request are generated at the same time, the refresh request takes precedence. 0: Auto-refresh disabled 1: Auto-refresh enabled
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Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial Value Undefined
R/W R/W
Description Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting These bits specify the number of auto-refresh cycles and the number of self-refresh clearing cycles. The DREFW bits can be written to at any time, regardless of the state of the auto-refresh operation enable (DRFEN) bit. If auto-refresh is disabled, the value written to these bits takes effect immediately. If autorefresh is enabled, the value written to these bits takes effect immediately if an auto-refresh cycle is not in progress. If an auto-refresh cycle is in progress, the new value takes effect after the cycle completes. 0000: 1 cycle 0001: 2 cycles 0010: 3 cycles : 1111: 16 cycles
15 to 12 DREFW [3:0]
11 to 0
DRFC [11:0]
Undefined
R/W
Auto-Refresh Request Interval Setting These bits specify the auto-refresh interval. The DRFC bits can be written to at any time, regardless of the state of the auto-refresh operation enable (DRFEN) bit. If auto-refresh is disabled, the value written to these bits takes effect immediately. If auto-refresh is enabled, the value written to these bits is reflected in the operation of the refresh counter from the next autorefresh request generated. 000000000000: Setting prohibited 000000000001: 2 cycles 000000000010: 3 cycles : 111111111111: 4096 cycles
Note: Auto-refresh requests are not accepted while multiple read or write accesses are in progress, or during a transfer using DMAC, so the auto-refresh interval may become enlarged in some cases. Set the DRFC bits to an auto-refresh request interval value that satisfies the auto-refresh interval specification of the SDRAM being used. Furthermore, make sure to set the auto-refresh request interval to a duration longer than the auto-refresh cycle.
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Section 9 Bus State Controller (BSC)
Auto-Refresh Request Interval and DRFC Set Value: SDRAMC includes a 12-bit refresh counter that generates auto-refresh requests at fixed intervals. The following equation is used to calculate the set value for the DRFC bits from the auto-refresh request interval.
DRFC = (Auto-refresh request interval / System clock cycle) - 1
Auto-refresh requests are not accepted while SDRAM is being accessed; they must wait until the access completes. However, the counter value is updated regardless or whether or not the request was accepted. Note that if two or more auto-refresh requests are generated while SDRAM is being accessed, the second and subsequent requests are ignored. 9.4.9 SDRAM Initialization Register 0 (SDIR0)
SDIR0 specifies the SDRAM initialization sequence timing.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R -- R/W 26 -- 0 R 10 25 -- 0 R 9 DPC[2:0] -- R/W -- R/W -- R/W 24 -- 0 R 8 23 -- 0 R 7 22 -- 0 R 6 21 -- 0 R 5 20 -- 0 R 4 19 -- 0 R 3 18 -- 0 R 2 17 -- 0 R 1 16 -- 0 R 0
DARFC[3:0] -- R/W -- R/W -- R/W -- R/W
DARFI[3:0] -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 11
10 to 8
DPC[2:0]
Undefined
R/W
Initialization Precharge Cycle Count Setting These bits specify the number of precharge cycles in the SDRAM initialization sequence. 000: 3 cycles 001: 4 cycles : 111: 10 cycles
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Section 9 Bus State Controller (BSC)
Bit 7 to 4
Bit Name DARFC [3:0]
Initial Value Undefined
R/W R/W
Description Initialization Auto-Refresh Count These bits specify the number of times auto-refresh is to be performed in the SDRAM initialization sequence. 0000: Setting prohibited 0001: 1 time : 1111: 15 times
3 to 0
DARFI[3:0] Undefined
R/W
Initialization Auto-Refresh Interval These bits specify the interval at which auto-refresh commands are issued in the SDRAM initialization sequence. 0000: 3 cycles 0001: 4 cycles 0010: 5 cycles : 1111: 18 cycles
Note: Make settings that satisfy the specifications of the connected SDRAM before starting the initialization sequence.
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Section 9 Bus State Controller (BSC)
9.4.10
SDRAM Initialization Register 1 (SDIR1)
SDIR1 controls activation of the SDRAM initialization sequence.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16
DIN IST
0 R/W 0
DIN IRQ
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 17
16
DINIST
0
R/W
Initialization Status When set to 1, this bit indicates that an SDRAM initialization sequence is in progress for channel SDRAM0 or SDRAM1. 0: Initialization sequence not progress 1: Initialization sequence in progress
15 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
DINIRQ
0
R/W
Common Initialization Sequence Start Setting this bit to 1 causes the SDRAM initialization sequence to start and automatically sets the initialization status bit (DINIST) to 1. The initialization status bit (DINIST) is cleared automatically after the initialization sequence ends. The value written to the DINIRQ bit is not retained. 0: Invalid 1: Initialization sequence start
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Section 9 Bus State Controller (BSC)
9.4.11
SDRAM Power-Down Control Register (SDPWDCNT)
SDPWDCNT controls transition to and recovery from power-down mode.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0
DPWD
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
DPWD
0
R/W
SDRAM Common Power-Down Enable This bit controls transition to and recovery from powerdown mode for all channels simultaneously. Setting DPWD to 1 causes all channels to transition to powerdown mode. Clearing DPWD to 0 causes all channels to recover from power-down mode. If an auto-refresh is in progress, the transition to power-down mode is delayed until the auto-refresh completes. 0: Power-down disabled 1: Power-down enabled
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Section 9 Bus State Controller (BSC)
9.4.12
SDRAM Deep-Power-Down Control Register (SDDPWDCNT)
SDDPWDCNT controls transition to and recovery from deep-power-down mode.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0
DDPD
0 R/W
Bit 31 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
DDPD
0
R/W
SDRAM Common Deep-Power-Down Enable This bit controls transition to and recovery from deeppower-down mode for all channels simultaneously. Setting DDPD to 1 causes all SDRAM channels to transition to deep-power-down mode. Clearing DDPD to 0 causes all SDRAM channels to recover from deeppower-down mode. If an auto-refresh is in progress, the transition to deep-power-down mode is delayed until the auto-refresh completes. 0: Deep-power-down disabled 1: Deep-power-down enabled
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Section 9 Bus State Controller (BSC)
9.4.13
SDRAMm Address Register (SDmADR) (m = 0, 1)
SDmADR specifies the data bus width and the channel size of SDRAM.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R -- R/W 18 -- 0 R 2 17 -- 0 R 1 DSZ[2:0] -- R/W -- R/W 16 -- 0 R 0
DDBW[1:0] -- R/W -- R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 10
9, 8
DDBW[1:0] Undefined
R/W
SDRAM Data Bit Width Setting These bits specify the width of the SDRAM bus. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
DSZ[2:0]
Undefined
R/W
Channel Size Setting These bits specify the size of channels 0 and 1. If a size smaller than SDRAM area 0 or 1 is selected, ghost memory will result. When accessing 32-bit data in SDRAM with a 16-bit bus width, the 16 bits of the first half of the address (A1 = 0) are accessed first, and then the 16 bits of the second half of the address (A1 = 1) are accessed.
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Section 9 Bus State Controller (BSC)
9.4.14
SDRAMm Timing Register (SDmTR) (m = 0, 1)
SDmTR specifies the timing for read and write accesses to SDRAM.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 DPCG[2:0] -- R/W -- R/W -- R/W 25 -- 0 R 9 24 -- 0 R 8 DWR -- R/W 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R -- R/W 18 17 DRAS[2:0] -- R/W 2 -- R/W 1 DCL[2:0] -- R/W -- R/W -- R/W 0 16
DRCD[1:0] -- R/W -- R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 19
18 to 16 DRAS[2:0] Undefined
R/W
Row Active Interval Setting These bits specify the minimum interval that must elapse between the SDRAM row activation command (ACT) and deactivation (PRA). 000: 1 cycle : 111: 8 cycles
15, 14
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
13, 12
DRCD[1:0] Undefined
R/W
Row Column Latency Setting These bits specify the SDRAM row column latency. 00: 1 cycles 01: 2 cycles 10: 3 cycles 11: 4 cycles
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Section 9 Bus State Controller (BSC)
Bit 11 to 9
Bit Name
Initial Value
R/W R/W
Description Row Precharge Interval Setting These bits specify the minimum number of cycles that must elapse between the SDRAM deactivation command (PRA) and the next valid command. 000: 1 cycles : 111: 8 cycles
DPCG[2:0] Undefined
8
DWR
0
R/W
Write Recovery Interval Setting This bit specifies the minimum interval that must elapse between the SDRAM write command (WRITE) and deactivation (PRA). 0: 1 cycles 1: 2 cycles
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
DCL[2:0]
Undefined
R/W
SDRAM Controller Column Latency Setting These bits specify the column latency of the SDRAM controller. This setting only affects the latency setting on the SDRAM controller side. To specify the column latency for externally connected SDRAM it is necessary to use the separate SDRAMm mode register (SDmMOD), which is described below. 000: Setting prohibited 001: 1 cycles 010: 2 cycles 011: 3 cycles 1xx: Setting prohibited
[Legend] x: Don't care
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Section 9 Bus State Controller (BSC)
9.4.15
SDRAMm Mode Register (SDmMOD) (m = 0, 1)
SDmMOD specifies the values to be written to the SDRAM mode register or extended mode register. Writing to this register causes a mode register set command or extended mode register set command to be issued automatically to SDRAM.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 30 -- 0 R 14 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 22 -- 0 R 6 21 -- 0 R 5 20 -- 0 R 4 19 -- 0 R 3 18 -- 0 R 2 17 -- 0 R 1 16 -- 0 R 0
DMR[14:0] -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Mode Register Setting Writing to these bits causes a mode register set command or extended mode register set command to be issued to SDRAM. The setting of the DMR bits is output as A16 to A2 signals. The distinction between the mode register set command and extended mode register set command is made on the bases of the SDRAM bank address. Write operation: A mode register set command is issued. DMR bit A16 to A2 signal b14 A16 b13 A15 ... ... b0 A2
31 to 15
14 to 0
DMR[14:0] Undefined
R/W
Notes: The following points should be kept in mind regarding SDRAMm mode register settings. 1. Make sure to set a burst length of 1 for SDRAM. Operation cannot be guaranteed with settings other than burst length 1. 2. The SDRAM column latency must match the setting of the SDRAM controller column latency setting bits (DCL) in SDRAMC. Operation cannot be guaranteed if the latency settings do not agree. 3. Check to make sure the status bits (DSRFST, DPWDST, DDPDST, and DMRSST) in the SDRAM status register (SDSTR) are all cleared to 0.
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Section 9 Bus State Controller (BSC)
9.4.16
SDRAM Status Register (SDSTR)
SDSTR consists of the status flags that indicate the status of operation during self-refresh, initialization sequences, power-down mode, deep-power-down mode, and mode register setting.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4
DSRF ST
19 -- 0 R 3
DINI ST
18 -- 0 R 2
17 -- 0 R 1
16 -- 0 R 0
DPWD DDPD DMRS ST ST ST
0 R
0 R
0 R
0 R
0 R
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4
DSRFST
0
R
Self-Refresh Transition/Recovery Status When set to 1, this bit indicates that a transition to or recovery from self-refresh operation is in progress for channel SDRAM0 or SDRAM1. 0: Transition/recovery not in progress 1: Transition/recovery in progress
3
DINIST
0
R
Initialization Status When set to 1, this bit indicates that an initialization sequence is in progress for channel SDRAM0 or SDRAM1. This bit has the same function as the DINIST bit in SDIR1. 0: Initialization sequence not in progress 1: Initialization sequence in progress
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Section 9 Bus State Controller (BSC)
Bit 2
Bit Name DPWDST
Initial Value 0
R/W R
Description Power-Down Transition/Recovery Status When set to 1, this bit indicates that a transition to or recovery from power-down mode is in progress for a channel from SDRAM0 to SDRAM3. 0: Initialization sequence not in progress 1: Initialization sequence in progress
1
DDPDST
0
R
Deep-Power-Down Transition/Recovery Status When set to 1, this bit indicates that a transition to or recovery from deep-power-down mode is in progress for channel SDRAM0 or SDRAM1. 0: Transition/recovery not in progress 1: Transition/recovery in progress
0
DMRSST
0
R
Mode Register Setting Status When set to 1, this bit indicates that mode register setting is in progress for channel SDRAM0 or SDRAM1. 0: Mode register setting not in progress 1: Mode register setting in progress
"Transition to or recovery from in progress" refers to the interval from the point at which the bits listed in table 9.5 are written to until the corresponding commands are issued.
Table 9.5
Function Self-refresh
List of Status Registers and Bits Requiring Checking
Register SDRFCNT0 SDIR1 SDPWDCNT SDDPDCNT SDmMOD Bits DSFENCm, DSFEN DINIRQCm, DINIRQ DPWDCm, DPWD DDPDCm, DDPD DMR
Initialization sequence Power-down Deep-power-down Mode register setting
Note: Execution of a self-refresh, a transition to or recovery from power-down or deep-powerdown mode, an initialization sequence, or mode register setting may only be performed when all status bits are cleared to 0. Do not rewrite the registers (bits) listed below when any of the status bits (DSRFST, DINIST, DPWDST, DDPDST, DMRSST) is set to 1.
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Section 9 Bus State Controller (BSC)
9.4.17
SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT)
SDCKSCNT enables or disables the clock stop control signal (internal signal in the chip) and specifies the number of assert cycles.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 0 R/W 0 R/W 0 R/W 23 -- 0 R 7 22 -- 0 R 6 21 -- 0 R 5 20 -- 0 R 4 19 -- 0 R 3 18 -- 0 R 2 17 -- 0 R 1 16
DCK SEN
0 R/W 0
DCKSC[7:0] 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 17
16
DCKSEN
0
R/W
Clock Stop Control Signal Enable This bit is used to enable or disable the clock stop control signal. When enabled, the clock stop control signal operates during transition to and from deeppower-down mode and stops the CKIO (high level). When disabled, the clock stop control signal stays low level. 0: Clock stop control signal disabled 1: Clock stop control signal enabled
15 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit 7 to 0
Bit Name DCKSC [7:0]
Initial Value H'0F
R/W R/W
Description Clock Stop Control Signal Assert Cycle Count Setting These bits specify the interval from the point at which the deep-power-down transition command is issued until the clock stop signal goes high level to stop the CKIO (high level), and the interval from the point at which the clock stop signal goes low level to start the CKIO operation until the recover command is issued. 00000000: 0 cycle : 00001111: 15 cycles : 11111111: 255 cycles
9.4.18
AC Characteristics Switching Register (ACSWR)
When writing to the external address space or making SDRAM settings in power-on reset exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in ACSWR to B'0011 beforehand. ACSWR is initialized to H'00000000 by a power-on reset and entry to deep standby mode, but is not initialized by a manual reset, entry to sleep mode, or entry to software standby mode.
Bit: 31 -- Initial value: 0 R/W: R/W Bit: 15 -- Initial value: 0 R/W: R/W 30 -- 0 R/W 14 -- 0 R/W 29 -- 0 R/W 13 -- 0 R/W 28 -- 0 R/W 12 -- 0 R/W 27 -- 0 R/W 11 -- 0 R/W 26 -- 0 R/W 10 -- 0 R/W 25 -- 0 R/W 9 -- 0 R/W 24 -- 0 R/W 8 -- 0 R/W 23 -- 0 R/W 7 -- 0 R/W 22 -- 0 R/W 6 -- 0 R/W 21 -- 0 R/W 5 -- 0 R/W 20 -- 0 R/W 4 -- 0 R/W 0 R/W 19 -- 0 R/W 3 18 -- 0 R/W 2 17 -- 0 R/W 1 16 -- 0 R/W 0
ACOSW[3:0] 0 R/W 0 R/W 0 R/W
Bit 31 to 4
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 9 Bus State Controller (BSC)
Bit 3 to 0
Bit Name
Initial Value
R/W R/W
Description AC Characteristics Switch These bits specify AC characteristics switching. 0000: Does not extend the delay time 0011: Switches characteristics and extends the delay time Other than above: Setting prohibited
ACOSW[3:0] 0000
9.5
9.5.1 (1)
Operation
CSC Interface Normal Access
Normal read/write operation is used for all bus access when page read/write access is disabled (PRENB = 0, PWENB = 0). Even when page read/write access is enabled (PRENB = 1, PWENB = 1), normal read/write operation is employed in cases where page access cannot be used. Figure 9.2 shows the basic operation of the external bus control signals in read operation, and figure 9.3 shows the basic operation of these signals in write operation.
Ts CKIO Read cycle wait A27 to A0 CS assert wait CSn RD assert wait RD WR D31 to D0 CS delay cycle during read Start enable point of next bus access Tw1 Tw2 Twn Tend Tn1 Tn2 (Trd) Tnm
Figure 9.2 Basic Bus Timing (Read Operation)
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Section 9 Bus State Controller (BSC)
Ts CKIO
Tw1 Tw2
Twn Tend Tn1
Tnm
Write cycle wait A27 to A0 CS assert wait CSn CS delay cycle during write
Start enable point of next bus access
RD WR
WR assert wait
Write data output wait D31 to D0
Write data output delay cycle
Figure 9.3 Basic Bus Timing (Write Operation) 1. Ts (Internal Bus Access Start) This is a bus access request cycle initiated by the internal bus master and with the external bus as the target. CSn is always high during this cycle. In the next cycle A27 to A0 and the write data change. 2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait) These are the cycles between internal bus access start and the wait end cycle. A duration of from 0 to 31 clocks may be selected. During this interval the CSn, RD, and WR control signals are asserted (low level) in accordance with the wait settings. The assert timing can be controlled using the CS assert wait, RD assert wait, WR assert wait, and write data output wait bits in CSn control registers 1 and 2. The number of wait cycles can be set to from 0 to 7 clocks, with the count starting from the cycle following internal bus access start (Ts). The number of clocks selected must be no greater than the number of read/write cycle wait cycles. 3. Tend (Wait End Cycle) This is the final cycle in a series of read cycle wait or write cycle wait cycles. The RD or WR signal is negated (high level) in the next cycle.
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Section 9 Bus State Controller (BSC)
4. Tn1 to Tnm (CS Delay Cycle) These are the cycles between the wait end cycle and when CSn is negated (high level). The negation timing can be controlled using write data output delay cycles. The number of cycles is counted beginning from the wait end cycle. In write access or if the number of CS delay cycles during a read is other than 0 or 1, the succeeding bus access can start from the cycle following the CS delay cycle end. If the number of CS delay cycles is 0 or 1 in read access, the succeeding bus access can start after the end of the read data sample cycle (see below). 5. Trd (Read Data Sample Cycle) This is the sample cycle for read data. (2) Page Access
Page read and write operation is employed for bus accesses for which page access can be used if page write access enable (PWENB = 1) and page read access enable (PRENB = 1) have been selected. Page access is used in the following cases. 1. CPU burst access (cache replacement) 2. When longword (32-bit) access to an 8-bit or 16-bit external data bus has been performed 3. When word (16-bit) access to an 8-bit external data bus has been performed Table 9.6 shows the way addresses are modified in cases 1 above. Table 9.6
Bus Master CPU Note: *
Address Modification during Burst Access
Burst Mode Increment Address Modification Incremented by single transfer byte count only.
Wrap boundary: Single transfer byte count x Burst transfer length
Figure 9.4 shows the basic operation of the external bus control signals in page read operation, and figure 9.5 shows the basic operation of these signals in write operation. Note that if the number of data bits accessed in a single burst is greater than the single page access bit boundary setting of the PBCNT bits in the mode register, a single burst access will trigger multiple page accesses. Regardless of whether the bust mode is increment or wraparound, page access stops temporarily (the CSn signal is negated) at the point when the address exceeds the page boundary, and page access operation starts again. If the number of data bits accessed in a single burst is smaller than the page boundary bit count, a single page access is sufficient to complete the burst transfer.
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Section 9 Bus State Controller (BSC)
Ts CKIO
Tw1
Twn Tend Tn1 Tn2 (Trd)
Twn Tend Tn1 Tn2 (Trd)
Tnm
Bus access (first time) Read cycle wait
Bus access (second and subsequent times) Page read cycle wait
CS delay cycle during read (end only)
Start enable point of next bus access
A27 to A0
A0
A1
CS assert wait CSn RD assert wait RD RD assert wait*
CS delay cycle during read
WR D31 to D0
Note: * RD assert wait operation during the second and subsequent bus accesses differs depending on the page read access mode setting value.
Figure 9.4 Basic Bus Timing (Page Read Operation)
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Section 9 Bus State Controller (BSC)
Ts CKIO
Tw1 Tw2
Twn Tend Tdw1 Tdwn Tpw1
Tpwn Tend Tdw1 Tdwn Tnm Tn1
Bus access (first time) Write cycle wait Write data output delay cycle
Bus access (second and subsequent times) Page write cycle wait A1
CS delay cycle during write (end only)
A27 to A0
A0 CS assert wait
CS delay cycle during write
CSn
RD WR assert wait WR Write data output wait D31 to D0 D0 Write data output Write data delay cycle output wait D1 Write data output delay cycle WR assert wait
Figure 9.5 Basic Bus Timing (Page Write Operation) 1. Ts (Internal Bus Access Start) This is a bus access request cycle initiated by the internal bus master and with the external bus as the target. CSn is always high during this cycle. In the next cycle A27 to A0 and the write data change. 2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait) For the first page access, the wait operation from internal bus access start to the wait end cycle is the same as in normal access. 3. Tend (First Wait End Cycle) This is the final cycle in the first series of read cycle wait or write cycle wait cycles. In write access, the second and subsequent page accesses start from the next cycle, unless a write data output delay cycle has been specified (with a value other than 0). The RD or WR signal is negated (high level) in the next cycle if the RD assert wait or WD assert wait setting is other than 0. If the RD assert wait or WD assert wait setting is 0, the RD or WR signal continues to be asserted (low level). The CSn signal is not negated and continues to be asserted (low level). In page read access, the succeeding bus access starts without waiting for the read data sample cycle (Trd).
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Section 9 Bus State Controller (BSC)
4. Tdw1 to Tdwn (Write Data Output Delay Cycle) In write access write data output delay cycles are inserted between the wait end cycle and the following page access if the write data output delay wait setting is other than 0. Assertion of the address and output data is extended for the duration of this interval. Also, the WR signal is negated (high level). 5. Tpw1 to Tpwn (Page Read Cycle Wait, Page Write Cycle Wait) In page access the page read cycle wait and page write cycle wait settings are used in place of the read cycle wait and write cycle wait settings for the second and subsequent bus cycles. The WR assert wait setting works the same as during the first bus cycle. The RD assert wait setting operates differently depending on the page read access mode (PRMOD) setting value. PRMOD = 0: RD assert wait setting operates identically to first bus cycle. PRMOD = 1: RD assert wait setting is invalid. Operation is the same as an RD assert wait setting of 0. 6. Tend/Tdw1 to Tdwn (Wait End Cycle/Write Data Output Delay Cycle) These operate the same as during the first access (3 and 4 above). 7. Tn1 to Tnm (CS Delay Cycle) These are the cycles between the final wait end cycle and when CSn is negated (high level). The number of CS delay cycles is counted beginning from the wait end cycle. 8. Trd (Final Read Data Sample Cycle) This is the final sample cycle for read data. (3) External Wait Function
The external wait signal (WAIT) can be used to extend the wait cycle duration beyond the value specified by the cycle wait (CSRWAIT, CSWWAIT) or page access cycle wait (CSPRWAIT, CSPWWAIT) settings in the CSn wait control register (CSWCNTn). If external wait enable (EWENB = 1) has been selected, wait cycles are inserted for as long as the WAIT signal remains low level. The WAIT signal is disabled if external wait disable (EWENB = 0) has been selected. Note that the wait cycles specified by the settings of the CSn wait control register (CSWCNTn) are inserted regardless of the state of the WAIT signal. (a) Normal Read/Write Operation
The WAIT signal is sampled all the time and its result is reflected two cycles later. Thus, when the WAIT signal is low two cycles before the end of the wait cycles, external cycles are inserted. After the WAIT signal has gone high, the wait cycles end two cycles later.
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Section 9 Bus State Controller (BSC)
(b)
Page Access Operation
The initial data read/write operation is the same as a normal read/write operation. That is, when the WAIT signal is low two cycles before the end of the wait cycles (Tend), external wait cycles are inserted. After the WAIT signal has gone high, the wait cycles end (Tend) two cycles later. In the second and subsequent read accesses, the page wait cycle is extended if the WAIT signal is low two cycles before the end of the page access wait cycle (Tend), and the page wait cycles end two cycles after the WAIT signal has gone high. Figure 9.6 shows an example of external wait timing for page read access using longword (32-bit) access to a 16-bit channel.
Ts CKIO (Tend) Tend (Tend) Tend
Cycle wait
External wait
Page cycle wait A1
External wait
A27 to A0
A0
WAIT CSn
Don't care
Don't care
Don't care
RD
WR D31 to D0
Figure 9.6 External Wait Timing Example (Page Read Access to 16-Bit Channel)
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Section 9 Bus State Controller (BSC)
(4) (a)
Access Type and Data Alignment 32-Bit Bus Channel
If a 32-bit bus is selected by the external bus width select bits in the CSn control register, A27 to A2 are enabled as address signals for longword units and A1 and A0 are disabled (fixed low level). Table 9.7 shows the data alignment corresponding to byte addresses for different data sizes. Pins WR3 to WR0 are enabled when byte strobe mode (WRMOD = 0) is selected. Pins BC3 to BC0 are not used. Only the WR3 pin is enabled when one-write strobe mode (WRMOD = 1) is selected. A low-level signal is output from the WR3 pin during write access, regardless of the data size. At this time pins WR2 to WR0 are disabled (fixed high level). The valid byte positions are indicated by pins BC3 to BC0. Table 9.7 Data Alignment (32-Bit Bus Channel)
Byte Address (Lower 2 Bits) [31:24] 0 1 2 3 Word 0 2 Longword 0 O x x x O x O DATA [23:16] x O x x O x O [15:8] x x O x x O O [7:0] x x x O x O O [3] L H H H L H L [2] H L H H L H L WR/BC [1] H H L H H L L [0] H H H L H L L
Data Size Byte
Note: The valid bits in the data bus for each data size are indicated by circles (O). Crosses (x) indicate bus data bits that are undefined.
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Section 9 Bus State Controller (BSC)
(b)
16-Bit Bus Channel
If a 16-bit bus is selected by the external bus width select bits in the CSn control register, A27 to A1 are enabled as address signals for word units and A0 is disabled (fixed low level). Table 9.8 shows the data alignment corresponding to byte addresses for different data sizes. Pins WR1 and WR0 are enabled when byte strobe mode (WRMOD = 0) is selected. Pins WR3 and WR2 are disabled. Pins BC3 to BC0 are not used. Only the WR1 pin is enabled when one-write strobe mode (WRMOD = 1) is selected. A low-level signal is output from the WR1 pin during write access, regardless of the data size. At this time the WR0 pin is disabled (fixed high level). The valid byte positions are indicated by pins BC1 and BC0. Table 9.8 Data Alignment (16-Bit Bus Channel)
Byte Address (Lower 2 Bits) [31:24] 0 1 2 3 Word 0 2 Longword 0 (1st) 2 (2nd) x x x x x x x x DATA [23:16] x x x x x x x x [15:8] O x O x O O O O [7:0] x O x O O O O O [3] * * * * * * * * [2] * * * * * * * * WR/BC [1] L H L H L L L L [0] H L H L L L L L
Data Size Byte
Note: The valid bits in the data bus for each data size are indicated by circles (O). Crosses (x) indicate bus data bits that are undefined. Asterisks (*) indicate write/byte control bits that are disabled (fixed high level).
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Section 9 Bus State Controller (BSC)
(c)
8-Bit Bus Channel
If an 8-bit bus is selected by the external bus width select bits in the CSn control register, A27 to A0 are enabled as address signals for byte units. Table 9.9 shows the data alignment corresponding to byte addresses for different data sizes. With an 8-bit bus channel only the WR0 pin is enabled, regardless of the strobe mode setting. A low-level signal is output to WR0 during write access. BC0 constantly outputs low level. Pins WR3 to WR1 and pins BC3 to BC1 are not used. Table 9.9 Data Alignment (8-Bit Bus Channel)
Byte Address (Lower 2 Bits) [31:24] 0 1 2 3 Word 0 (1st) 1 (2nd) 2 (1st) 3 (2nd) Longword 0 (1st) 1 (2nd) 2 (3rd) 3 (4th) x x x x x x x x x x x x DATA [23:16] x x x x x x x x x x x x [15:8] x x x x x x x x x x x x [7:0] O O O O O O O O O O O O [3] * * * * * * * * * * * * [2] * * * * * * * * * * * * WR/BC [1] * * * * * * * * * * * * [0] L L L L L L L L L L L L
Data Size Byte
Note: The valid bits in the data bus for each data size are indicated by circles (O). Crosses (x) indicate bus data bits that are undefined. Asterisks (*) indicate write/byte control bits that are disabled (fixed high level).
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Section 9 Bus State Controller (BSC)
9.5.2
SDRAM Interface
A description is provided here of the SDRAM controller (SDRAMC) operation enable and SDRAM bus width settings as well as operations involving SDRAM (read, write, auto-refresh, self-refresh, initialization sequence, and mode register settings). (1) SDRAM Access Enable/Disable and SDRAM Bus Width Settings
Enabling and disabling SDRAM access is performed by making settings in the individual SDRAMCm control registers to enable or prohibit SDRAMC operation. SDRAM bus width settings are also performed by means of the SDRAMCm control registers. Even if the SDRAMC control register is set to disable SDRAMC operation, refresh operation will still take place if self-refresh or auto-refresh operation is set as enabled. (2) SDRAM Commands
SDRAMC controls the SDRAM by issuing commands each bus cycle. These commands are defined by combinations of RAS, CAS, WE, CKE, CS, etc. Table 9.10 lists the commands issued by SDRAMC.
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Section 9 Bus State Controller (BSC)
Table 9.10 SDRAMC Commands
Command DSL ACT RD WR PRA RFA MRS EMRS RFS RFX DPD DPDX Deselect Initialize row and bank Read Write Precharge all banks Auto-refresh Mode register set Extended mode register set Self-refresh entry Self-refresh exit Deep-power-down Deep-power-down exit SDCS H L L L L L L L L H L X SDRAS SDCAS SDWE X L H H L L L L L X H X X H L L H L L L L X H X X H H L L H L L H X L X SDCKE BA1 X H H H H H H H HL LH HL LH X V V V X X L H X X X X BA0 X V V V X X L L X X X X
[Legend] H: High level, L: Low level, V: Valid, X: Don't care
(3)
SDRAMC Register Setting Conditions
Rewriting of SDRAMC registers should only be performed when all of the conditions listed in table 9.11 are satisfied. Table 9.11 Register Rewrite Conditions
Function/Operation Self-refresh Register SDRFCNT0 Conditions * * * * Auto-refresh Initialization sequence SDRFCNT1 SDIR0 SDIR1 * * * * SDRAM access disabled (set in SDRAMCm* ) Auto-refresh enabled (DRFEN = 1) Power-down disabled (DPWD/DPWDCI = 0) Deep-power-down disabled (DDPD/DDPDCI = 0) Self-refresh disabled (DSFEN/DSFENCI = 0) Power-down disabled (DPWD/DPWDCI = 0) Before start of initialization sequence After reset or after recovery from deep-powerdown
1
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Section 9 Bus State Controller (BSC)
Function/Operation Power-down
Register SDPWDCNT
Conditions * * * * SDRAM access disabled (set in SDRAMCm* ) Auto-refresh enabled (DRFEN = 1) Self-refresh disabled (DSFEN/DSFENCI = 0) Deep-power-down disabled (DDPD/DDPDCI = 0) SDRAM access disabled (set in SDRAMCm* ) Self-refresh disabled (DSFEN/DSFENCI = 0) Auto-refresh disabled (DRFEN = 0) Power-down disabled (DPWD/DPWDCI = 0) Auto-refresh disabled (DRFEN = 0) SDRAM access disabled (set in SDRAMCm* ) Self-refresh disabled (DSFEN/DSFENCI = 0) Power-down disabled (DPWD/DPWDCI = 0) Deep-power-down disabled (DDPD/DDPDCI = 0) Self-refresh in progress (DSFEN/DSFENCI = 1) or Self-refresh disabled (DSFEN/DSFENCI = 0) Auto-refresh disabled (DRFEN = 0) SDRAM access disabled (set in SDRAMCm* ) SDRAM access disabled (set in SDRAMCm* ) Self-refresh disabled (DSFEN/DSFENCI = 0) Power-down disabled (DPWD/DPWDCI = 0) Deep-power-down disabled (DDPD/DDPDCI = 0) Deep-power-down disabled (DDPD/DDPDCI = 0)
1 1 1 1 1
Deep-power-down
SDDPDCNT
* * * *
Address register settings
SD0ADR, SD1ADR
* * * * *
Timing register settings
SD0TR, SD1TR
* * * *
Mode register settings
SD0MOD, SD1MOD*
2
* * * *
Clock stop control signal settings
SDCKSCNT
*
Notes: 1. After writing 0 to EXENB, check to confirm that the EXENB bit has been cleared to 0. 2. Do not fail to confirm that all status bits in the SDRAM status register (SDSTR) have been cleared to 0 before rewriting this bit.
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Section 9 Bus State Controller (BSC)
(4)
Self-Refresh
Transition to and from self-refresh mode is controlled by means of settings to SDRAM refresh control register 0 (SDRFCNT0). Transition to and from self-refresh mode takes place simultaneously for all channels. An auto-refresh cycle operation takes place immediately before transition to self-refresh mode. While in self-refresh mode the CKE signal is low level. Immediately after recovery from selfrefresh mode an auto-refresh cycle is triggered. Figure 9.7 shows the timing of transition to self-refresh mode, and figure 9.8 shows the timing of recovery from self-refresh mode.
Auto-refresh cycle CKIO RFA DSL DREFW DSL: Deselect command RFA: Auto-refresh command RFS: Self-refresh entry command DSL RFS Self-refresh mode (CKE = L)
SDRAM command
Figure 9.7 Example of Timing of Transition to Self-Refresh Mode (DREFW Bit Set Value: 0010)
Self-refresh mode (CKE = L) CKIO REX DSL DREFW DSL: Deselect command RFA: Auto-refresh command RFX: Self-refresh exit command DSL RFA DSL DREFW DSL Self-refresh clearing interval Auto-refresh cycle
SDRAM command
Figure 9.8 Example of Timing of Recovery from Self-Refresh Mode (DREFW Bit Set Value: 0010)
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Section 9 Bus State Controller (BSC)
(5)
Auto-Refresh
An auto-refresh cycle starts when the auto-refresh operation enable bit (DRFEN) in SDRAM refresh control register 1 (SDRFCNT1) is set to 1. After that refresh requests are issued at fixed intervals, activating auto-refresh cycles. However, the activation of auto-refresh cycles may sometimes be delayed because refresh requests are not accepted during read or write accesses. A refresh request is issued immediately if the auto-refresh operation enable bit (DRFEN) in SDRAM refresh control register 1 (SDRFCNT1) is set to 1 while auto-refresh is enabled. The refresh counter is halted in self-refresh or deep-power-down mode. After recovery from selfrefresh or deep-power-down mode an auto-refresh cycle is activated, after which the counter value is reset and the counter begins operating again Make auto-refresh settings in SDRAM refresh control register 1 (SDRFCNT1). Note that refresh cycles affect all SDRAM channels. Figure 9.9 shows an auto-refresh cycle timing example.
Auto-refresh cycle CKIO RFA DSL DREFW DSL: Deselect command RFA: Auto-refresh command DSL
SDRAM command
Figure 9.9 Auto-Refresh Cycle Timing Example (DREFW Bit Set Value: 0010)
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Section 9 Bus State Controller (BSC)
(6)
Initialization Sequencer
SDRAMC is provided with a sequencer for issuing the commands for SDRAM initialization. The initialization sequence should always be initiated a single time only following a reset (all channels) and following recovery from deep-power-down mode (individual channels). In such cases operation cannot be guaranteed if the initialization sequence is not performed, or if it is performed more than once. The SDRAM initialization sequence issues the precharge-all-banks command followed by n (n = 1 to 15) auto-refresh commands, in that order. Make timing settings for the initialization sequencer to SDRAM initialization register 0 (SDIR0). Initialization sequences are initiated using SDRAM initialization register 1 (SDIR1). Note that an initialization sequence for all channels is initiated using the DINIRQ bit. Figure 9.10 shows a timing example for the initialization sequence. Setting DARFC to specify two or more times causes multiple initialization auto-refresh cycles to be performed.
Initialization precharge cycle CKIO PRA DSL DSL DPC DSL: Deselect command RFA: Auto-refresh command PRA: Precharge-all-banks command DSL RFA DSL DSL DSL Initialization auto-refresh cycle
SDRAM command
DARFI DINST bit value changes to 0
Figure 9.10 Initialization Sequence Timing Example (DPC Bit Set Value: 001, DARFI Bit Set Value: 0001, DARFC Bit Set Value: 001)
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Section 9 Bus State Controller (BSC)
(7)
Power-Down Mode
SDRAMC supports an SDRAM power-down mode. In power-down mode the SDCKE signal from SDRAMC goes low level. While in power-down mode auto-refresh operations are performed at the interval specified by the auto-refresh request interval setting (DRFC) bits in SDRAM refresh control register 1 (SDRFCNT1). The SDCKE signal only goes high when an auto-refresh command is issued. Transition to and recovery from power-down mode are performed using the SDRAM power-down control register (SDPWDCNT). Setting the DPWD bit to 1 causes SDRAMC to transition to power-down mode. Clearing the DPWD bit to 0 causes SDRAMC to recover from power-down mode. The SDCKE signal from SDRAMC goes high level when recovery from power-down mode occurs.
SDRAMC power-down mode CKIO
SDCKE
Figure 9.11 SDRAMC Power-Down Mode
SDRAMC power-down mode CKIO SDCKE SDRAM command RFA Auto-refresh command
Figure 9.12 Auto-Refresh Operation in SDRAMC Power-Down Mode
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Section 9 Bus State Controller (BSC)
(8)
Deep-Power-Down Mode
SDRAMC supports an SDRAM deep-power-down mode. In deep-power-down mode SDRAMC issues a deep-power-down command and drives the SDCKE signal low level. Transition to and recovery from deep-power-down mode are performed using the SDRAM deeppower-down control register (SDDPDCNT). Setting the DDPD bit to 1 causes SDRAMC to put all channels into deep-power-down mode. Clearing the DDPD bit to 0 causes SDRAMC to recover from deep-power-down mode. During recovery from deep-power-down mode, SDRAMC issues a deep-power-down exit command and drives the SDCKE signal high level. Following recovery from deep-power-down exit, wait for the duration designated for the SDRAM being used and then execute an initialization sequence.
SDRAMC deep-power-down mode CKIO
SDCKE SDRAM command DPD Deep-power-down command DPDX Deep-power-down exit command
Figure 9.13 SDRAMC Deep-Power-Down Mode
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Section 9 Bus State Controller (BSC)
(9)
Read/Write Access
The following two types of read/write access are supported. * Multiple read/multiple write * Single read/single write Multiple read/multiple write occurs in the following cases. 1. 2. 3. 4. CPU burst access (cache replace) Access with longword (32-bit) to the SDRAM data bus having 8-bit or 16-bit width Access with word (16-bit) to the SDRAM data bus having 8-bit width Multiple data transfer in DMA pipeline transfer
The access timing can be set independently for each channel using the SDRAMI timing register (SDITR). Access timing examples are described below. (a) Multiple Read/Multiple Write Access
Figure 9.14 shows a timing example for multiple read of 4 units of data, and figure 9.15 for multiple write of 4 units of data. The number of DMA transfers performed will vary depending on factors such as the number of transfers and the transfer data size per operand and the SDRAM bus width. Read commands or write commands may or may not be issued consecutively in response to an access request from the bus master. When read commands or write commands are not issued consecutively, a deselect command is issued between them. Furthermore, deactivation and activation are performed automatically when the SDRAM row address changes during a DMA transfer operation. Figure 9.16 shows a timing example for multiple read of 4 units of data, and figure 9.17 for multiple write of 4 units of data, when read/write commands are not issued consecutively. Figure 9.18 shows a timing example for multiple write with a row address change. The access timing is modified by means of settings in the SDRAMm timing register (SDmTR).
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Section 9 Bus State Controller (BSC)
Multiple read CKIO SDRAM command ACT RD RD RD d0 ACT: Row and bank activation command RD: Read command PRA: Precharge-all command RD d1 PRA d2 d3
Data bus
Figure 9.14 Multiple Read Timing Example (Multiple Read of 4 Data Units, Shortest Timing Settings) Consecutive Read Commands Issued
Multiple write CKIO SDRAM command Data bus ACT WR d0 WR d1 WR d2 WR d3 PRA
ACT: Row and bank activation command WR: Write command PRA: Precharge-all command
Figure 9.15 Multiple Write Timing Example (Multiple Write of 4 Data Units, Shortest Timing Settings) Consecutive Write Commands Issued
Multiple read CKIO SDRAM command ACT RD DSL RD d0 DSL RD d1 DSL RD d2 PRA d3
Data bus
ACT: RD: PRA: DSL:
Row and bank activation command Read command Precharge-all command Deselect command
Figure 9.16 Multiple Read Timing Example (Multiple Read of 4 Data Units, Shortest Timing Settings) Non-Consecutive Read Commands Issued
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Section 9 Bus State Controller (BSC)
Multiple write CKIO SDRAM command ACT WR d0 DSL WR d1 DSL WR d2 DSL WR d3 PRA
Data bus ACT: WR: PRA: DSL:
Row and bank activation command Write command Precharge-all command Deselect command
Figure 9.17 Multiple Write Timing Example (Multiple Write of 4 Data Units, Shortest Timing Settings) Non-Consecutive Write Commands Issued
Multiple write CKIO SDRAM command ACT WR d0 WR d1 WR d2 PRA ACT WR d3 PRA
Data bus
Row address A ACT: Row and bank activation command WR: Write command PRA: Precharge-all command
Row address B
Figure 9.18 Multiple Write Timing Example (Multiple Write of 4 Data Units, Shortest Timing Settings) Access Spanning Rows
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Section 9 Bus State Controller (BSC)
(b)
Single Read/Single Write Access
Figure 9.19 shows a timing example for single read operation and figure 9.20 for single write operation. The access timing is modified by means of settings in the SDRAMm timing register (SDmTR).
Single read CKIO SDRAM command ACT RD PRA d0 ACT: Row and bank activation command RD: Read command PRA: Precharge-all command
Data bus
Figure 9.19 Single Read Timing Example (Shortest Timing Settings)
Single write CKIO SDRAM command Data bus ACT WR d0 ACT: Row and bank activation command WR: Write command PRA: Precharge-all command PRA
Figure 9.20 Single Write Timing Example (Shortest Timing Settings)
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Section 9 Bus State Controller (BSC)
(c)
Byte Access Control by DQM
Figures 9.21 and 9.22 show timing examples for byte accesses to the SDRAM with a 16-bit bus width. In the SDRAM access, the DQM signal is asserted when data is masked.
CKIO
SDRAM command
ACT
WR
PRA
DQM1 DQM0 Data bus [15:8] d0 Low level High-Z
Data bus [7:0]
Figure 9.21 Byte Write Timing to SDRAM with 16-Bit Bus Width (Example)
CKIO
SDRAM command
ACT
RD
DSL
PRA
DQM1 DQM0
Low level
Data bus [15:8]
d0 High-Z
Data bus [7:0]
Figure 9.22 Byte Read Timing from SDRAM with 16-Bit Bus Width (Example)
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Section 9 Bus State Controller (BSC)
(10) Mode Register Setting Writing to the SDRAMm mode register (SDmMOD) causes mode register set commands and extended mode register set commands to be issued to the various channels. Settings to the SDRAMm mode register (SDmMOD) should be made individually for each channel. Figure 9.23 shows the operation timing for mode register setting.
Mode register setting cycle CKIO SDRAM command MRS DSL DSL EMRS DSL DSL Extended mode register setting cycle
3 cycles (fixed) DSL: Deselect command MRS: Mode register set command EMRS: Extended mode register set command
3 cycles (fixed)
Figure 9.23 Operation Timing for Mode Register Setting (11) Clock Stop Control Signal SDRAMC outputs a clock stop control signal (CLKSTOP). CLKSTOP can be enabled or disabled using the DCKSEN bit in the SDRAM clock stop control signal setting register (SDCKSCNT). The CLKSTOP signal remains low level when the clock stop control signal is disabled. When clock stop control signal is enabled, the CLKSTOP and CKIO signals operate in conjunction with transition to and recovery from deep-power-down mode. During a transition to deep-power-down mode, the CLKSTOP signal goes high after the deeppower-down entry command is issued. During a recovery from deep-power-down mode, the CLKSTOP signal goes low and a deep-power-down exit command is issued when the clearing of the DDPD bit to 0 is accepted by SDRAMC and the CKIO starts operation. DCKSC, the period between the change of CLKSTOP along with CKIO and the issuance of deep power-down entry or exit command, can be set by the SDRAM clock stop control signal setting register.
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Section 9 Bus State Controller (BSC)
Figures 9.24 and 9.25 show the operation timing of the clock stop control signal.
Deep-power-down mode CKIO SDRAM command SDCKE CLKSTOP (internal signal) DCKSC DDPDST bit value changes to 0 DPD: Deep-power-down entry command DPD
Figure 9.24 Clock Stop Control Signal Operation Timing (Transition to Deep-Power-Down Mode)
Deep-power-down mode CKIO SDRAM command SDCKE CLKSTOP (internal signal) DCKSC DDPD bit cleared to 0 DDPDST bit value changes to 1 DPDX: Deep-power-down exit command DDPDST bit value changes to 0
DPDX
Figure 9.25 Clock Stop Control Signal Operation Timing (Recovery from Deep-Power-Down Mode)
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Section 9 Bus State Controller (BSC)
(12) SDRAMC Setting Examples The SDRAMC setting procedure, timing register setting examples, and the procedure for transitioning to and recovering from self-refresh mode, power-down mode, and deep-power-down mode are described below. (a) SDRAMC Setting Procedure
Figure 9.26 shows the SDRAMC setting procedure. Note that the specifications of the power-up sequence, etc., may vary depending on the SDRAM used. Study the SDRAM specifications carefully before making system settings.
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Section 9 Bus State Controller (BSC)
Reset
Specify all SDRAM control pins as port outputs with the PFC setting of PORTC to output high level
Channel m settings (1) Confirm that all status bits in SDSTR have been cleared to 0 (2) Make settings to SDmMOD mode register (3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR (4) Set DSZ bits in SDmADR
Perform settings for all channels to be used
Enable access SDRAMCm control register operation enable setting
Dummy-read SDRAM area of all channels to be used
Disable access SDRAMCm control register operation disable setting
Specify SDRAM control pins (except DQM pin*) as SDRAM with the PFC setting of PORTC
Initialization sequence (1) Set DPC, DARFC, and DARFI bits in SDIR0 (2) Set DINIRQ bit in SDIR1 to 1 (3) Wait for DINIST bit in SDIR1 to be cleared to 0
Channel m settings (1) Confirm that all status bits in SDSTR have been cleared to 0 (2) Make settings to SDmMOD mode register (3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR (4) Set DSZ bits in SDmADR
Perform settings for all channels to be used
Start auto-refresh Set DRFEN bit in SDRFCNT1 to 1
Specify DQM pin as DQM* with the PFC setting of PORTC
Enable access SDRAMCm control register operation enable setting
SDRAM access enabled Note : * Driving the DQM pin high before the initialization sequence is recommended for some SDRAM modules. In this case, the setting may be necessary.
Figure 9.26 SDRAMC Setting Procedure
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Section 9 Bus State Controller (BSC)
(b)
Procedure for Transition to and Recovery from Self-Refresh Mode
Figure 9.27 shows the procedure for transitioning to and recovering from self-refresh mode.
Access enabled status (DRFEN = 1, EXENB = 1)
Initialization sequence (1) Halt any DMA access to SDRAM area (2) Halt access to all SDRAMC channels (EXENB = 0) by means of program assigned to other than SDRAM area (3) Confirm that EXENB has been cleared to 0
Start self-refresh (1) Confirm that all status bits in SDSTR have been cleared to 0 (2) Set DSFEN bit to 1 by means of program assigned to other than SDRAM area
Self-refresh mode
End self-refresh (1) Confirm that all status bits in SDSTR have been cleared to 0 (2) Clear DSFEN bit to 0 by means of program assigned to other than SDRAM area
Enable access Enable access to SDRAMC (EXENB = 1) by means of program assigned to other than SDRAM area
Access enabled status (DRFEN = 1, EXENB = 1)
Figure 9.27 Procedure for Transition to and Recovery from Self-Refresh Mode Note: Before transitioning to or recovering from self-refresh mode it is necessary to halt SDRAM access to the affected channels. Consequently, it is not possible to transition to or recover from self-refresh mode while programs or DMA operations that access SDRAM are in progress. Pay attention to the following points when writing programs. * Before transitioning to self-refresh mode, halt any DMA channel transfers that access the SDRAM area of the affected channels. * Make sure that programs run while transitioning to self-refresh mode, while in selfrefresh mode, or while recovering from self-refresh mode do not access operands or fetch (or pre-fetch) instructions stored in the SDRAM area.
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Section 9 Bus State Controller (BSC)
(c)
Procedure for Transition to and Recovery from Deep-Power-Down Mode
Figure 9.28 shows the procedure for transitioning to deep-power-down mode.
Access enabled status EXENB = 1 in SDRAMC control register
Halt access (1) Halt any DMA access to corresponding channels (2) Halt access to corresponding channels (EXENB = 0) by means of program assigned to other than to corresponding channel area (3) Confirm that EXENB has been cleared to 0
End auto-refresh Clear DRFEN bit in SDRFCNT1 to 0
Start deep-power-down mode (1) Confirm that all status bits in SDSTR have been cleared to 0 (2) Set deep-power-down enable bit to 1 by means of program assigned to other than to corresponding channel area
Deep-power-down mode
Figure 9.28 Procedure for Transition to Deep-Power-Down Mode
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Section 9 Bus State Controller (BSC)
Figure 9.29 shows the procedure for recovering from deep-power-down mode.
Deep-power-down mode
End deep-power-down mode (1) Confirm that all status bits in SDSTR have been cleared to 0 (2) Clear deep-power-down enable bit to 0 by means of program assigned to other than to corresponding channel area
Standby Use a timer, etc., to wait for the same duration as the standby time specified in the power-on sequence (determined by specifications of SDRAM used)
Initialization sequence (1) Set initialization sequence start bit (DINIRQm) to 1 by means of program assigned to other than to corresponding channel area (2) Wait for initialization sequence start bit (DINISTm) to be cleared to 0
Mode register setting (1) Perform mode register setting (2) Perform extended mode register setting
Start auto-refresh Set DRFEN bit in SDRFCNT1 to 1
Access enabled status (EXENB = 1)
Figure 9.29 Procedure for Recovery from Deep-Power-Down Mode Note: Before transitioning to or recovering from deep-power-down mode it is necessary to halt SDRAM access to the affected channels. Consequently, it is not possible to transition to or recover from deep-power-down mode while programs or DMA operations that access SDRAM are in progress. Pay attention to the following points when writing programs. * Before transitioning to deep-power-down mode, halt any DMA channel transfers that access the SDRAM area of the affected channels. * Make sure that programs run while transitioning to deep-power-down mode, while in deep-power-down mode, or while recovering from deep-power-down mode do not access operands or fetch (or pre-fetch) instructions stored in the SDRAM area.
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Section 9 Bus State Controller (BSC)
(d)
Timing Register Set Values and Access Timing
The correspondence between the SDRAMm timing register (SDmTR) set values and the read and write access timing is described below. * Multiple Read Timing Setting Examples Figures 9.30 to 9.32 show the correspondence between the timing of multiple read operations involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table 9.12 shows the SDRAMm timing register (SDmTR) set values for each figure. Table 9.12 SDITR Set Value Correspondence Table (Multiple Read Timing)
Figure Figure 9.30 Figure 9.31 Figure 9.32 DRAS 010 000 000 DRCD 00 01 01 DPCG 001 001 001 DCL 010 010 011
Multiple read CKIO SDRAM command ACT RD RD RD d0 DRCD (ACT-RD) DCL (RD-d) RD d1 PRA d2 DSL d3
Data bus
DPCG (PRA-next)
DRAS (ACT-PRA) ACT: Row and bank activation command RD: Read command PRA: Precharge-all command
Figure 9.30 Multiple Read Timing Example 1
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Section 9 Bus State Controller (BSC)
Multiple read CKIO SDRAM command ACT DSL RD RD RD d0 DRCD (ACR-RD) DRAS (ACT-PRA) ACT: Row and bank activation command RD: Read command PRA: Precharge-all command DCL (RD-d) RD d1 PRA d2 DSL d3
Data bus
DPCG (PRA-next)
Figure 9.31 Multiple Read Timing Example 2
Multiple read CKIO SDRAM command Data bus DRCD (ACT-RD) DRAS (ACT-PRA) ACT: Row and bank activation command RD: Read command PRA: Precharge-all command DCL (RD-d) DPCG (PRA-next) ACT DSL RD RD RD RD d0 PRA d1 DSL d2 DSL d3
Figure 9.32 Multiple Read Timing Example 3
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Section 9 Bus State Controller (BSC)
* Multiple Write Timing Setting Examples Figures 9.33 to 9.35 show the correspondence between the timing of multiple write operations involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table 9.13 shows the SDRAMm timing register (SDmTR) set values for each figure. Table 9.13 SDITR Set Value Correspondence Table (Multiple Write Timing)
Figure Figure 9.33 Figure 9.34 Figure 9.35 DRAS 010 000 000 DRCD 00 01 01 DPCG 001 001 001 DWR 0 0 1
Multiple write CKIO SDRAM command ACT WR d0 DRCD (ACT-WR) DRAS (ACT-PRA) ACT: Row and bank activation command WR: Write command PRA: Precharge-all command WR d1 WR d2 WR d3 DWR DPCG (WR-PRA) (PRA-next) PRA DSL
Data bus
Figure 9.33 Multiple Write Timing Example 1
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Section 9 Bus State Controller (BSC)
Multiple write CKIO SDRAM command ACT DSL WR d0 DRCD (ACR-WR) DRAS (ACT-PRA) ACT: Row and bank activation command WR: Write command PRA: Precharge-all command WR d1 WR d2 WR d3 DWR (WR-PRA) DPCG (PRA-next) PRA DSL
Data bus
Figure 9.34 Multiple Write Timing Example 2
Multiple write CKIO SDRAM command ACT DSL WR d0 DRCD (ACT-WR) DRAS (ACT-PRA) ACT: Row and bank activation command WR: Write command PRA: Precharge-all command WR d1 WR d2 WR d3 DWR (WR-PRA) DPCG (PRA-next) DSL PRA DSL
Data bus
Figure 9.35 Multiple Write Timing Example 3
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Section 9 Bus State Controller (BSC)
* Single Read Timing Setting Examples Figures 9.36 to 9.38 show the correspondence between the timing of single read operations and the set values of the SDRAMm timing register (SDmTR). Table 9.14 shows the SDRAMm timing register (SDmTR) set values for each figure. Table 9.14 SDITR Set Value Correspondence Table (Single Read Timing)
Figure Figure 9.36 Figure 9.37 Figure 9.38 DRAS 010 000 000 DRCD 00 01 01 DPCG 001 001 001 DCL 010 010 011
Single read CKIO SDRAM command ACT RD DSL PRA d DRCD (ACT-RD) DCL (RD-d) DPCG (PRA-next) DSL
Data bus
DRAS (ACT-PRA) ACT: Row and bank activation command RD: Read command PRA: Precharge-all command
Figure 9.36 Single Read Timing Example 1
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Section 9 Bus State Controller (BSC)
Single read CKIO SDRAM command ACT DSL RD PRA DSL d DRCD (ACT-RD) DRAS (ACT-PRA) ACT: RD: DSL: PRA: DCL (RD-d) DPCG (PRA-next)
Data bus
Row and bank activation command Read command Deselect command Precharge-all command
Note: If the interval set in DRAS ends before RD, PRA is issued in the table size after RD.
Figure 9.37 Single Read Timing Example 2
Single read CKIO SDRAM command ACT DSL RD PRA DSL d DRCD (ACT-RD) DRAS (ACT-PRA) DCL (RD-d) DPCG (PRA-next)
Data bus
ACT: Row and bank activation command RD: Read command PRA: Precharge-all command
Figure 9.38 Single Read Timing Example 3
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Section 9 Bus State Controller (BSC)
* Single Write Timing Setting Examples Figures 9.39 to 9.41 show the correspondence between the timing of single write operations and the set values of the SDRAMm timing register (SDmTR). Table 9.15 shows the SDRAMm timing register (SDmTR) set values for each figure. Table 9.15 SDITR Set Value Correspondence Table (Single Write Timing)
Figure Figure 9.39 Figure 9.40 Figure 9.41 DRAS 010 000 000 DRCD 00 01 01 DPCG 001 001 001 DWR 0 0 1
Single write CKIO SDRAM command Data bus ACT WR d DRCD DWR (ACT-WR) (WR-PRA) DRAS (ACT-PRA) ACT: WR: DSL: PRA: Row and bank activation command Write command Deselect command Precharge-all command DPCG (PRA-next) DSL PRA DSL
Note: If the interval set in DRAS is longer than the period from when the WR command is issued until the DWR interval elapses, the DRAS setting is used.
Figure 9.39 Single Write Timing Example 1
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Section 9 Bus State Controller (BSC)
Single write CKIO SDRAM command ACT DSL WR PRA DSL
Data bus DRCD (ACT-WR) DRAS (ACT-PRA) ACT: WR: DSL: PRA:
d DWR (WR-PRA) DPCG (PRA-next)
Row and bank activation command Write command Deselect command Precharge-all command
Note: If the interval set in DRAS is longer than the period from when the WR command is issued until the DRAS interval elapses, the DWR setting is used.
Figure 9.40 Single Write Timing Example 2
Single write CKIO SDRAM command ACT DSL WR d DRCD (ACT-WR) DRAS (ACT-PRA) ACT: WR: DSL: PRA: Row and bank activation command Write command Deselect command Precharge-all command DWR (WR-PRA) DPCG (PRA-next) DSL PRA DSL
Data bus
Figure 9.41 Single Write Timing Example 3
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Section 9 Bus State Controller (BSC)
(13) External Address/SDRAM Address Signal Multiplex (a) Address Multiplex
Either of addresses used for accessing external device or SDRAM is output through external address pins. The SDRAM address is shifted internally by changing the settings of DDBW and DSZ in SDmADR and BSIZE in SDCmCNT. The bank address is output on A16 and A15 and the address is output on A14 to A2. Table 9.16 External Address/SDRAM Address Pins
Pin Name A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 (/BA1) A15 (/BA0) Function External address External address External address External address External address External address External address External address External address External address External address External address/SDRAM bank address External address/SDRAM bank address Pin Name Function
A13 (/MA11) External address/SDRAM address A12 (/MA10) External address/SDRAM address A11 (/MA9) A10 (/MA8) A9 (/MA7) A8 (/MA6) A7 (/MA5) A6 (/MA4) A5 (/MA3) A4 (/MA2) A3 (/MA1) A2 (/MA0) A1 A0 External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address/SDRAM address External address External address
A14 (/MA12) External address/SDRAM address
(b)
Address Register Setting Value and Supported SDRAM Configuration
Tables 9.17 to 9.19 are the SDRAM configurations that to support for 8-, 16-, or 32-bit bus width. These tables are featured to ease the understanding of the relationships between the SDRAM to support and address multiplex. Addresses addr27 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. The table below shows how the settings of DSZ and DDBW determine which signals are output on the SDRAM-access pins.
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Section 9 Bus State Controller (BSC)
Table 9.17 Case for 8-Bit External Data Bus Width (BSIZE*1 = (1, 0))
SDRAM Type Number DSZ*
2
64 Mbits (x8) 1 001 (8 Mbytes)
128 Mbits (x8) 1 010 (16 Mbytes) 00 (8 bits) Column Address addr23* addr22* L
5 5
256 Mbits (x8) 1 011 (32 Mbytes) 00 (8 bits) Row Address addr24* addr23* addr22* addr21*
5
512 Mbits (x8) 1 100 (64 Mbytes) 00 (8 bits) Row Address addr25* addr24*
5
DDBW*
3
00 (8 bits) Row Address
4
This LSI address A16 (/BA1)* A15 (/BA0)*
Column Row Address Address addr22* addr21* L
5
Column Address addr24* addr23* L L *
6 5
Column Address addr25* addr24* L addr10* *
6 5 5
addr22* addr21*
4
5
addr23* addr22* L addr21*
5
4
5
5
5
5
5
5
5
5
A14 (/MA12)* L A13 (/MA11)* addr20* A12 (/MA10)* addr19* A11 (/MA9)* A10 (/MA8)* A9 (/MA7)* A8 (/MA6)* A7 (/MA5)* A6 (/MA4)* A5 (/MA3)* A4 (/MA2)* A3 (/MA1)* A2 (/MA0)*
4 4 4 4 5
5
addr23* addr22* addr21*
5
5
L *
6
L *
6
5
5
5
addr20* addr19*
5
5
addr20*
5
5
5
addr18* addr17*
5
L addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1* addr0*
addr19* addr18* addr17* add16*
5
5
addr9* addr8* addr7* addr6*
addr20* addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1* addr0*
5
4
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
5
5
5
5
5
addr16* addr15* addr14* addr13* addr12* addr11* addr10* addr9*
5
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
4
5
5
5
5
addr15* addr14* addr13* addr12* addr11* addr10*
5
addr5* addr4* addr3* addr2* addr1* addr0*
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
addr0*
5
5
5
5
5
5
5
Notes: 1. 2. 3. 4.
The legend BSIZE represents the BSIZE bit in the SDRAMCm control register. The legend DSZ represents the DSZ bit in the SDRAMm address register. The legend DDBW represents the DDBW bit in the SDRAMm address register. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and SDRAM address respectively. 5. Addresses addr25 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. 6. When the RD, WR or PRA command is issued, this carries the pre-charge option signal.
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Section 9 Bus State Controller (BSC)
Table 9.18 Case for 16-Bit External Data Bus Width (BSIZE*1 = (0, 0)) (1)
SDRAM Type Number DSZ*
2 3
64 Mbits (x16) 1 001 (8 Mbytes) 01 (16 bits)
Row Address
4
64 Mbits (x8) 2 010 (16 Mbytes) 00 (8 bits)
Column Address addr23* addr22* L
5 5
128 Mbits (x16) 1 010 (16 Mbytes) 01 (16 bits)
Row Address addr23* addr22* L addr21*
5 5
128 Mbits (x8) 2 011 (32 Mbytes) 00 (8 bits)
Row Column Address Address addr24* addr23* L addr22* addr21*
5 5
DDBW*
This LSI address
Column Row Address Address addr22*
5
Column Address addr23* addr22* L L *
6 5
A16 (/BA1)* A15 (/BA0)*
addr22* addr21
4
5
addr23* addr22* L addr21*
5
addr24* addr23* L L *
6
5
4
addr21* L
5
5
5
5
5
5
5
5
A14 (/MA12)* L A13 (/MA11)* addr20* A12 (/MA10)* addr19* A11 (/MA9)* A10 (/MA8)* A9 (/MA7)* A8 (/MA6)* A7 (/MA5)* A6 (/MA4)* A5 (/MA3)* A4 (/MA2)* A3 (/MA1)* A2 (/MA0)*
4 4 4 4
L *
6
L *
6
5
addr20* addr19* addr18*
5
5
addr20* addr19*
5
5
5
addr18* addr17*
5
L L addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
L addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
L addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
addr20*
5
addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
5
4
5
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr16* addr15* addr14* addr13* addr12* addr11* addr10* addr9*
5
5
addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
addr1*
5
5
5
5
5
5
5
Notes: 1. 2. 3. 4.
The legend BSIZE represents the BSIZE bit in the SDRAMCm control register. The legend DSZ represents the DSZ bit in the SDRAMm address register. The legend DDBW represents the DDBW bit in the SDRAMm address register. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and SDRAM address respectively. 5. Addresses addr24 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. 6. When the RD, WR or PRA command is issued, this carries the pre-charge option signal.
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Section 9 Bus State Controller (BSC)
Table 9.18 Case for 16-Bit External Data Bus Width (BSIZE*1 = (0, 0)) (2)
SDRAM Type Number DSZ*
2
256 Mbits (x16) 1 011 (32 Mbytes)
256 Mbits (x8) 2 100 (64 Mbytes) 00 (8 bits) Column Address addr25* addr24* L L *
6 5
512 Mbits (x16) 1 100 (64 Mbytes) 01 (16 bits) Row Address addr25* addr24* addr23* addr22*
5
512 Mbits (x8) 2 101 (128 Mbytes) 00 (8 bits) Row Address addr26* addr25*
5
DDBW*
3
01 (16 bits) Row Address
4
This LSI address A16 (/BA1)* A15 (/BA0)*
Column Row Address Address addr24* addr23* L L *
6 5
Column Address addr25* addr24* L L *
6 5
Column Address addr26* addr25* L addr11* *
6 5 5
addr24* addr23*
4
5
addr25* addr24* addr23* addr22*
5
4
5
5
5
5
5
5
5
5
A14 (/MA12)* addr22* A13 (/MA11)* addr21* A12 (/MA10)* addr20* A11 (/MA9)* A10 (/MA8)* A9 (/MA7)* A8 (/MA6)* A7 (/MA5)* A6 (/MA4)* A5 (/MA3)* A4 (/MA2)* A3 (/MA1)* A2 (/MA0)*
4 4 4 4
5
5
5
addr24* addr23* addr22*
5
5
5
5
5
5
5
addr21* addr20*
5
5
addr21*
5
5
5
addr19* addr18*
5
L addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
addr20*
5
addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
addr21*
5
addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2* addr1*
5
5
4
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr20* addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12*
5
addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
Notes: 1. 2. 3. 4.
The legend BSIZE represents the BSIZE bit in the SDRAMCm control register. The legend DSZ represents the DSZ bit in the SDRAMm address register. The legend DDBW represents the DDBW bit in the SDRAMm address register. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and SDRAM address respectively. 5. Addresses addr26 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. 6. When the RD, WR or PRA command is issued, this carries the pre-charge option signal.
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Section 9 Bus State Controller (BSC)
Table 9.19 Case for 32-Bit External Data Bus Width (BSIZE*1 = (0, 1)) (1)
SDRAM Type Number DSZ*
2
64 Mbits (x32) 1 001 (8 Mbytes)
64 Mbits (x16) 2 010 (16 Mbytes) 01 (16 bits)
128 Mbits (x32) 1 010 (16 Mbytes) 10 (32 bits) Column Address addr23* addr22* L
5 5
64 Mbits (x8) 4 011 (32 Mbytes) 00 (8 bits) Row Address addr24* addr23* L addr22*
5 5
DDBW*
3
10 (32 bits) Row Address
4
This LSI address A16 (/BA1)* A15 (/BA0)*
Column Row Address Address addr22* addr21* L L
5
Column Row Address Address addr23* addr22* L
5
Column Address addr24* addr23* L L *
6 5
addr22* addr21*
4
5
addr23* addr22* L addr21*
5
addr23* addr22* L
5
4
5
5
5
5
5
5
5
5
A14 (/MA12)* A13 (/MA11)* A12 (/MA10)* A11 (/MA9)* A10 (/MA8)* A9 (/MA7)* A8 (/MA6)* A7 (/MA5)* A6 (/MA4)* A5 (/MA3)* A4 (/MA2)* A3 (/MA1)* A2 (/MA0)*
4 4
L L addr20*
5
4
5
L *
6
addr21* addr20*
L *
6
4
*
6
addr20* addr19* addr18*
5
5
5
addr21* addr20* addr19*
5
5
addr19* addr18*
5
L L addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
L L addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
L L addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
L addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5 5
4
5
5
5
5
addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
addr17* addr16* addr15* addr14* addr13* addr12* addr11* addr10*
5
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
Notes: 1. 2. 3. 4.
The legend BSIZE represents the BSIZE bit in the SDRAMCm control register. The legend DSZ represents the DSZ bit in the SDRAMm address register. The legend DDBW represents the DDBW bit in the SDRAMm address register. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and SDRAM address respectively. 5. Addresses addr24 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. 6. When the RD, WR or PRA command is issued, this carries the pre-charge option signal.
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Section 9 Bus State Controller (BSC)
Table 9.19 Case for 32-Bit External Data Bus Width (BSIZE*1 = (0, 1)) (2)
SDRAM Type Number DSZ*
2
128 Mbits (x16) 2 011 (32 Mbytes)
256 Mbits (x32) 1 011 (32 Mbytes) 10 (32 bits)
Column Address addr24* addr23* L
5 5
128 Mbits (x8) 4 100 (64 Mbytes) 00 (8 bits)
Row Address addr25* addr24* L addr23*
5 5
256 Mbits (x16) 2 100 (64 Mbytes) 01 (16 bits)
Row Address addr25* addr24*
5
DDBW*
3
01 (16 bits)
Row Address
4
This LSI address A16 (/BA1)* A15 (/BA0)*
Column Row Address Address addr24* addr23* L
5
Column Address addr25* addr24* L L *
6 5
Column Address addr25* addr24* L L *
6 5
addr24* addr23*
4
5
addr24* addr23* L addr22*
5
4
5
5
5
5
5
5
5
5
A14 (/MA12)* L A13 (/MA11)* addr22* A12 (/MA10)* addr21* A11 (/MA9)* A10 (/MA8)* A9 (/MA7)* A8 (/MA6)* A7 (/MA5)* A6 (/MA4)* A5 (/MA3)* A4 (/MA2)* A3 (/MA1)* A2 (/MA0)*
4 4 4 4 5
addr23* addr22* addr21*
5
5
L *
6
L *
6
5
5
addr21* addr20*
5
5
addr22* addr21*
5
5
5
addr20* addr19*
5
L addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
5
L addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
5
addr11* addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
addr20* addr19*
5
L addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5 5
4
5
addr19*
5
addr20*
5
5
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12*
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
Notes: 1. 2. 3. 4.
The legend BSIZE represents the BSIZE bit in the SDRAMCm control register. The legend DSZ represents the DSZ bit in the SDRAMm address register. The legend DDBW represents the DDBW bit in the SDRAMm address register. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and SDRAM address respectively. 5. Addresses addr25 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. 6. When the RD, WR or PRA command is issued, this carries the pre-charge option signal.
Rev. 2.00 Sep. 07, 2007 Page 285 of 1312 REJ09B0320-0200
Section 9 Bus State Controller (BSC)
Table 9.19 Case for 32-Bit External Data Bus Width (BSIZE*1 = (0, 1)) (3)
SDRAM Type Number DSZ*
2
512 Mbits (x32) 1 100 (64 Mbytes)
256 Mbits (x8) 4 101 (128 Mbytes) 00 (8 bits) Column Address addr26* addr25* L L *
6 5
512 Mbits (x16) 2 101 (128 Mbytes) 01 (16 bits) Row Address addr26* addr25* addr24* addr23*
5
512 Mbits (x8) 4 110 (256 Mbytes) 00 (8 bits) Row Address addr27* addr26*
5
DDBW*
3
10 (32 bits) Row Address
4
This LSI address A16 (/BA1)* A15 (/BA0)*
Column Row Address Address addr25* addr24* L L *
6 5
Column Address addr26* addr25* L L *
6 5
Column Address addr27* addr26* L addr12* *
6 5 5
addr25* addr24*
4
5
addr26* addr25* addr24* addr23*
5
4
5
5
5
5
5
5
5
5
A14 (/MA12)* addr23* A13 (/MA11)* addr22* A12 (/MA10)* addr21* A11 (/MA9)* A10 (/MA8)* A9 (/MA7)* A8 (/MA6)* A7 (/MA5)* A6 (/MA4)* A5 (/MA3)* A4 (/MA2)* A3 (/MA1)* A2 (/MA0)*
4 4 4 4
5
5
5
addr25* addr24* addr23*
5
5
5
5
5
5
5
addr22* addr21*
5
5
addr22*
5
5
5
addr20* addr19*
5
L addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
5
addr11* addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
addr21* addr20*
5
addr11* addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
addr22* addr21*
5
addr11* addr10* addr9* addr8* addr7* addr6* addr5* addr4* addr3* addr2*
5
5
4
5
addr20*
5
5
5
5
5
5
addr18* addr17* addr16* addr15* addr14* addr13* addr12* addr11*
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12*
5
addr19* addr18* addr17* addr16* addr15* addr14* addr13* addr12*
5
addr20* addr19* addr18* addr17* addr16* addr15* addr14* addr13*
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
Notes: 1. 2. 3. 4.
The legend BSIZE represents the BSIZE bit in the SDRAMCm control register. The legend DSZ represents the DSZ bit in the SDRAMm address register. The legend DDBW represents the DDBW bit in the SDRAMm address register. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and SDRAM address respectively. 5. Addresses addr27 to addr0 are the logical addresses used by the CPU and DMAC in access to the SDRAM. 6. When the RD, WR or PRA command is issued, this carries the pre-charge option signal.
Rev. 2.00 Sep. 07, 2007 Page 286 of 1312 REJ09B0320-0200
Section 9 Bus State Controller (BSC)
(c)
Example of SDRAM Connection
Figures 9.42 and 9.43 show examples of the connection of SDRAM with this LSI.
This LSI
A16 A15 A14 A13 to A2 A1, A0 SDCKE SDCLK SDCS SDRAS SDCAS SDWE D13 to D16 DQM3 DQM2 D15 to D0 DQM1 DQM0 64 M SDRAM (1 M x 16 bits x 4 banks) A13 (BA1) A12 (BA0) A11 to A0 CKE CLK CS RAS CAS WE I/O15 to I/O0 DQMU DQML A13 (BA1) A12 (BA0) A11 to A0 CKE CLK CS RAS CAS WE I/O15 to I/O0 DQMU DQML
Not in use Not in use
Figure 9.42 Example of Connecting a 32-Bit Data-Width SDRAM
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Section 9 Bus State Controller (BSC)
This LSI
A16 A15 A14 A13 to A2 A1, A0 SDCKE SDCLK SDCS SDRAS SDCAS SDWE D13 to D16 DQM3 DQM2 D15 to D0 DQM1 DQM0
64 M SDRAM (1 M x 16 bits x 4 banks) A13 (BA1) A12 (BA0) A11 to A0 CKE CLK CS RAS CAS WE I/O15 to I/O0 DQMU DQML
Not in use Not in use
Not in use Not in use Not in use
Figure 9.43 Example of Connecting a 16-Bit Data-Width SDRAM
9.6
9.6.1
Usage Note
Note on Power-on Reset Exception Handling and Deep Standby Mode Cancellation
When writing to the external address space or making SDRAM settings in power-on reset exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in ACSWR to B'0011 beforehand. 9.6.2 Write Buffer
In write access to normal or SDRAM space, the write data are stored once in the internal write buffer of the BSC, and only after that does actual writing to the device (external device) connected in the normal or SDRAM space proceed. Since writing from the write buffer to the external device is performed automatically, no processing by software is necessary. However, care must be taken on the following point. Write access from the CPU or DMAC appears complete at the point where the data are stored in the above write buffer. That is, at the point where the write access from the CPU or DMA controller has been completed, writing to the external device might not have been completed. To confirm the completion of writing to the external device, dummy read the normal or SDRAM space. Completion of the dummy-read operation guarantees the completion of writing to the external device in response to previous write
Rev. 2.00 Sep. 07, 2007 Page 288 of 1312 REJ09B0320-0200
Section 9 Bus State Controller (BSC)
access. The target address for the dummy read operation does not have to be in the same device as the target for write access. Furthermore, it does not have to be in the same space. 9.6.3 Note on Transition to Software Standby Mode or Deep Standby Mode
When a transition to software standby mode or deep standby mode is made after write access to the normal or SDRAM space, there is a possibility that data remains in the internal write buffer of the BSC. To confirm that no data remain in the write buffer, execute a dummy read of the external device in the same way as described above.
Rev. 2.00 Sep. 07, 2007 Page 289 of 1312 REJ09B0320-0200
Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 290 of 1312 REJ09B0320-0200
Section 10 Bus Monitor
Section 10 Bus Monitor
The bus monitor is a module that monitors bus errors on each bus. When an illegal address access or a bus timeout is detected, a bus error interrupt is generated and an access canceling signal is output for the bus timeout. (The bus timeout function is used for debugging.) Figure 10.1 shows a block diagram of the bus monitor.
Bus monitor
Bus monitor enable register
Bus interface
Peripheral bus
Bus monitor status register 1 Bus monitor status register 2 Bus error control register Bus error signal SH2A CPU core
Figure 10.1 Block Diagram of Bus Monitor
10.1
Register Descriptions
The bus monitor has the following registers. All registers are initialized by a power-on reset or in deep standby mode. Table 10.1 Register Configuration
Register Name Bus monitor enable register Bus monitor status register 1 Bus monitor status register 2 Bus error control register Abbreviation SYCBEEN SYCBESTS1 SYCBESTS2 SYCBESW R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FF400000 H'FF400004 H'FF400008 H'FF40000C Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
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Section 10 Bus Monitor
10.1.1
Bus Monitor Enable Register (SYCBEEN)
SYCBEEN clears the bus monitor status register and controls the detection function.
Bit: 31
STS CLR
30 -- 0 R 14 -- 0 R
29 -- 0 R 13 -- 0 R
28 -- 0 R 12 -- 0 R
27 -- 0 R 11 -- 0 R
26 -- 0 R 10 -- 0 R
25 -- 0 R 9 -- 0 R
24 -- 0 R 8 -- 0 R
23 -- 0 R 7 -- 0 R
22 -- 0 R 6 -- 0 R
21 -- 0 R 5 -- 0 R
20 -- 0 R 4 -- 0 R
19 -- 0 R 3 -- 0 R
18
17
16 -- 0 R 0 -- 0 R
TOEN IGAEN
Initial value: 0 R/W: R/W Bit: 15 -- Initial value: R/W: 0 R
0 R/W 2 -- 0 R
0 R/W 1 -- 0 R
Bit 31
Bit Name STSCLR
Initial Value 0
R/W R/W
Description Status Clear Writing 1 to this bit clears the bus monitor status register. Writing 0 or reading data has no effect. 0: Invalid 1: Bus monitor status register cleared
30 to 19
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
18
TOEN
0
R/W
Timeout Detection Enable This bit enables or disables the function that detects a bus timeout on each bus. 0: Bus timeout detection function disabled 1: Bus timeout detection function enabled
17
IGAEN
0
R/W
Illegal Address Access Detection Enable This bit enables or disables the function that detects an illegal address access on each bus. 0: Illegal address access detection function disabled 1: Illegal address access detection function enabled
16 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note: When a bus access is performed with the detection function disabled (TOEN = 0), the bus may freeze.
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Section 10 Bus Monitor
10.1.2
Bus Monitor Status Register 1 (SYCBESTS1)
SYCBESTS1 indicates the status of slave buses (peripheral bus (1)/peripheral bus (3)) regarding whether a timeout occurred, whether an illegal address access was made, or which bus master accessed the slave bus. Table 10.2 shows the correspondence between the bus spaces and the slave buses.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 PTO 0 R 29 -- 0 R 13 PER 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 24 -- 0 R 8 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 CTO 0 R 21 -- 0 R 5 CER 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 16 -- 0 R 0
PMST[1:0] 0 R 0 R
CMST[1:0] 0 R 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 15
14
PTO
0
R
Timeout This bit indicates that a timeout occurred on peripheral bus (1) when the first bus error occurred. 0: Timeout not generated 1: Timeout generated
13
PER
0
R
Illegal Address Access This bit indicates that an illegal address access was made on peripheral bus (1) when the first bus error occurred. 0: Illegal address access not made 1: Illegal address access made
12 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 293 of 1312 REJ09B0320-0200
Section 10 Bus Monitor
Bit 9, 8
Bit Name PMST[1:0]
Initial Value 00
R/W R
Description Bus Master These bits indicate the bus master that accessed peripheral bus (1) when the first bus error occurred. 00: CPU 01: DMAC (destination side) 10: Setting prohibited 11: DMAC (source side)
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
6
CTO
0
R
Timeout This bit indicates that a timeout occurred on peripheral bus (3) when the first bus error occurred. 0: Timeout not generated 1: Timeout generated
5
CER
0
R
Illegal Address Access This bit indicates that an illegal address access was made on peripheral bus (3) when the first bus error occurred. 0: Illegal address access not made 1: Illegal address access made
4 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
CMST[1:0]
00
R
Bus Master These bits indicate the bus master that accessed peripheral bus (3) when the first bus error occurred. 00: CPU 01: DMAC (destination side) 10: Setting prohibited 11: DMAC (source side)
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Section 10 Bus Monitor
Table 10.2 Bus Space and Slave Bus
Address H'0000 0000 to H'4FFF FFFF H'5000 0000 to H'E7FF FFFF H'E800 0000 to H'E800 FFFF H'E801 0000 to H'EFFF FFFF H'F000 0000 to H'F1FF FFFF H'F200 0000 to H'F5FF FFFF H'F600 0000 to H'FF3F FFFF H'FF40 0000 to H'FF5F FFFF H'FF60 0000 to H'FFF7 FFFF H'FFF8 0000 to H'FFF8 7FFF H'FFF8 8000 to H'FFFB FFFF H'FFFC 0000 to H'FFFF FFFF Bus Space External bus space Reserved On-chip peripheral module (3) Reserved Address array space in cache Reserved Reserved On-chip peripheral module (1) Reserved On-chip RAM Reserved On-chip peripheral module (2) Slave Bus External bus (Others*1) Peripheral bus (3) (Others*1) *2 *2 (Others*1) Peripheral bus (1) (Others*1) *2 *2 Peripheral bus (2)
Notes: 1. This means bus spaces in the slave bus space other than those for the external bus and peripheral buses (1), (2), and (3). 2. An illegal address access error does not occur.
10.1.3
Bus Monitor Status Register 2 (SYCBESTS2)
SYCBESTS2 indicates the status of slave buses (external bus/peripheral bus (2)/others) regarding whether a timeout occurred, whether an illegal address access was made, or which bus master accessed the slave bus.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 ETO 0 R 14 -- 0 R 29 EER 0 R 13 OER 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 24 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 SHER 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 16 -- 0 R 0
EMST[1:0] 0 R 9 0 R 8
OMST[1:0] 0 R 0 R
SHMST[1:0] 0 R 0 R
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Section 10 Bus Monitor
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30
ETO
0
R
Timeout This bit indicates that a timeout occurred on the external bus when the first bus error occurred. 0: Timeout not generated 1: Timeout generated
29
EER
0
R
Illegal Address Access This bit indicates that an illegal address access was made on the external bus when the first bus error occurred. 0: Illegal address access not made 1: Illegal address access made
28 to 26
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
25, 24
EMST[1:0]
00
R
Bus Master These bits indicate the bus master that accessed the external bus when the first bus error occurred. 00: CPU 01: DMAC (destination side) 10: Setting prohibited 11: DMAC (source side)
23 to 14
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
13
OER
0
R
Illegal Address Access These bits indicate the bus master that accessed other buses when the first bus error occurred. 0: Illegal address access not made 1: Illegal address access made
Rev. 2.00 Sep. 07, 2007 Page 296 of 1312 REJ09B0320-0200
Section 10 Bus Monitor
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
12 to 10
9, 8
OMST[1:0]
00
R/W
Bus Master These bits indicate the bus master that accessed other buses when the first bus error occurred. 00: CPU 01: DMAC (destination side) 10: Setting prohibited 11: DMAC (source side)
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5
SHER
0
R
Illegal Address Access This bit indicates that an illegal address access was made on peripheral bus (2) when the first bus error occurred. 0: Illegal address access not made 1: Illegal address access made
4 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
SHMST [1:0]
00
R
Bus Master These bits indicate the bus master that accessed peripheral bus (2) when the first bus error occurred. 00: CPU 01: DMAC (destination side) 10: Setting prohibited 11: DMAC (source side)
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Section 10 Bus Monitor
10.1.4
Bus Error Control Register (SYCBESW)
SYCBESW controls the notification of various types of bus errors to the CPU.
Bit: 31 30 29 -- 0 R 13 -- 0 R 28
11 CPEN
27 -- 0 R 11 -- 0 R
26 -- 0 R 10 -- 0 R
25 -- 0 R 9 -- 0 R
24 -- 0 R 8 -- 0 R
23 -- 0 R 7 -- 0 R
22 -- 0 R 6 -- 0 R
21 -- 0 R 5 -- 0 R
20 -- 0 R 4 -- 0 R
19 -- 0 R 3 -- 0 R
18 -- 0 R 2 -- 0 R
17 -- 0 R 1 -- 0 R
16 -- 0 R 0 -- 0 R
00 01 CPEN CPEN
Initial value: 0 R/W: R/W Bit: 15 -- Initial value: R/W: 0 R
0 R/W 14 -- 0 R
0 R/W 12 -- 0 R
Bit 31
Bit Name 00CPEN
Initial Value 0
R/W R/W
Description Bus Error Control (CPU CPU) This bit controls notification to the CPU when a bus error is caused by the CPU. 0: Not notified 1: Notified
30
01CPEN
0
R/W
Bus Error Control (DMAC Destination Side CPU) This bit controls notification to the CPU when a bus error is caused by the DMAC destination side. 0: Not notified 1: Notified
29
0
R
Reserved This bit is always read as 0. The write value should always be 0.
28
11CPEN
0
R/W
Bus Error Control (DMAC Source Side CPU) This bit controls notification to the CPU when a bus error is caused by the DMAC source side. 0: Not notified 1: Notified
27 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 10 Bus Monitor
10.2
Bus Monitor Function
The bus monitor function detects two types of bus error: illegal address access and bus timeout. Bus error detection is performed in one bus access. Even when data is transferred in multiple bus accesses such as burst transfer, a bus error can be detected in one bus access. 10.2.1 Operation when a Bus Error is Detected
When a bus error is detected, the status is saved in the bus monitor status register 1 (SYCBESTS1) and bus monitor status register 2 (SYCBESTS2) and the CPU is notified of the bus error is notified to the CPU. (1) Saving Status in Bus Monitor Status Register or Bus Monitor Status Register 2
When a bus error occurs, the status at the time (what type of error occurred and which bus was being accessed by which bus master) is saved in the bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2 (SYCBESTS2). Even if another bus error occurs after this, the value in the bus monitor status register (SYCBESTS) or bus monitor status register 2 (SYCBESTS2) is not updated. When multiple bus errors occur at the same time, multiple status bits may be set. The bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2 (SYCBESTS2) can be cleared by writing 1 to the status clear bit (STSCLR) in the bus monitor enable register (SYCBEEN) from the bus master. After being cleared, the status of a bus error, if generated, is saved in the bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2 (SYCBESTS2) again. When a clear operation and a bus error happen at the same time, the clear operation has priority and the bus error is ignored.
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Section 10 Bus Monitor
(2)
Error Notification to the CPU
The CPU is notified of a bus error through the OR condition of the timeout bits (PTO/CTO/ETO) and illegal address access bits (PER/CER/EER/OER/SHER) in the bus monitor status register 1 (SYCBESTS1) and bus monitor status register 2 (SYCBESTS2). The CPU is notified of a bus error interrupt according to the setting of the bus error control register (SYCBESW). When the bus monitor status register 1 (SYCBESTS1) and bus monitor status register 2 (SYCBESTS2) are cleared by the CPU, the bus error interrupt signal is also negated. (3) Termination of Bus Access
When a bus error is detected, the bus access is terminated. For details, see section 10.2.4, Combinations of Masters and Bus Errors. For the detailed operations when each type of error is detected, see section 10.2.2, Illegal Address Access Detection Function and section 10.2.3, Bus Timeout Detection Function. 10.2.2 Illegal Address Access Detection Function
The illegal address access detection function detects attempted accesses to illegal addresses. (1) Conditions of Illegal Address Access Error Generation
Illegal address access errors occur when the following illegal addresses are accessed. * External spaces for which the operation enable bit (EXENB) in the control register of the BSC is not set to "operation enabled" * Other address areas that are not mapped to any slave bus * Address areas that are mapped to the slave buses but do not correspond to slave devices Tables 10.3 to 10.5 show the address areas to which slave devices are not mapped within the spaces for peripheral buses (1), (2), and (3). Table 10.3 Address Areas without Slave Devices in the Space for Peripheral Bus (1)
FF401000 to FF41FFFF FF423000 to FF45FFFF FF464000 to FF5FFFFF
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Section 10 Bus Monitor
Table 10.4 Address Areas without Slave Devices in the Space for Peripheral Bus (2)
FFFC0000 to FFFDFFFF FFFE0020 to FFFE03FF FFFE0420 to FFFE07FF FFFE0900 to FFFE37FF FFFE3830 to FFFE387F FFFE3910 to FFFE3FFF FFFE4400 to FFFE53FF FFFE5410 to FFFE57FF FFFE5840 to FFFE67FF FFFE6804 to FFFE7FFF FFFE8100 to FFFE87FF FFFE8900 to FFFE8FFF FFFE9100 to FFFE97FF FFFE9900 to FFFE9FFF FFFEA100 to FFFEA7FF FFFEA900 to FFFEAFFF FFFEB100 to FFFEB7FF FFFEB900 to FFFECFFF FFFED010 to FFFED07F FFFED090 to FFFEDFFF FFFEE010 to FFFEE07F FFFEE090 to FFFEE0FF FFFEE110 to FFFEFFFF FFFF1408 to FFFF14FF FFFF1508 to FFFF15FF FFFF1608 to FFFF16FF FFFF1720 to FFFF17FF FFFF1820 to FFFF18FF FFFF1910 to FFFFFFFF
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Section 10 Bus Monitor
Table 10.5 Address Areas without Slave Devices in the Space for Peripheral Bus (3)
E8000050 to E80000FF E8000110 to E80001FF E8000206 to E800FFFF
10.2.3
Bus Timeout Detection Function
The bus timeout detection function detects bus accesses whose cycles are extended to 768 cycles or more. (1) Conditions of Bus Timeout Error Generation
Bus timeout errors occur in the following cases. This function should be used when debugging software. * A bus access is not completed on peripheral bus (1) * A bus access is not completed on peripheral bus (3) * The WAIT signal remains asserted during an external bus access (2) Operation When a Bus Timeout Error is Generated
The operation when a bus timeout error occurs is explained below. 1. The timeout counter starts counting from the next cycle after the start of a bus access. 2. If the bus access is not completed in 768 cycles, a bus timeout occurs and an access canceling signal is asserted for 256 cycles. Bus signals such as address, data, BC, read/write, and burst are held. The timeout error is recorded in the bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2 (SYCBESTS2). A bus error interrupt is generated and sent to the CPU. 3. The bus access is terminated. 4. The CPU processes the bus error. Locked buses are all released.
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Section 10 Bus Monitor
(3)
Bus Timeout Operation in Consecutive Accesses
For transfers where multiple bus accesses are made (such as burst transfer), the next bus access might not be terminated when a bus timeout occurs. In this case, a bus timeout may occur continuously. Even if a bus timeout occurs continuously, the timeout process of terminating a bus access is performed in the same way as the first time. However, the status is saved in the bus monitor status register 1 (SYSCESTS1) or bus monitor status register 2 (SYCBESTS2) only the first time. 10.2.4 Combinations of Masters and Bus Errors
The types of detectable bus error depend on the master and access mode. (1) CPU Transfer Modes and Types of Bus Error Generated
Table 10.6 shows the types of bus error that may be generated by accesses from the CPU. Table 10.6 CPU Access Types and Types of Bus Error Generated
Access Type Illegal address access* Bus timeout*1
1
Normal Access O*
2
Burst Access O*2*3 O*2*3
O*2
[Legend] O: A bus error is generated. : A bus error is not generated. Notes: 1. To enable bus error detection, the bus monitor enable register (SYCBEEN) should be set. 2. To notify the CPU of a bus error, the 00CPEN bit in the bus error control register (SYCBESW) should be set to 1. 3. The number of bus errors detected is the same as the number of accesses that resulted in an error.
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Section 10 Bus Monitor
(2)
DMAC Transfer Modes and Operations of Each Bus
Table 10.7 shows the DMAC transfer modes and the types of bus error that may be generated by accesses from the DMAC. Table 10.7 DMAC Transfer Modes and Types of Bus Error Generated
DMAC Transfer Mode Illegal address access* Bus timeout* Cycle Steal O O Pipeline O O
[Legend] O: A bus error is generated. : A bus error is not generated. Note: * To enable bus error detection, the bus monitor enable register (SYCBEEN) should be set.
10.3
10.3.1
Usage Note
Operation when the CPU is Not Notified of a Bus Error
Table 10.8 describes the operations when bus error notification to the CPU is disabled with the bus error detection enabled (by the setting of the bus monitor enable register (SYCBEEN)). Table 10.8 Operation When the Master is Not Notified of a Bus Error
Illegal address access Illegal address access errors equal in number to the predetermined number of transfers are generated and the access is terminated each time. Bus timeouts equal in number to the predetermined number of transfers are generated and the access is terminated each time.
Bus timeout
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Section 11 Direct Memory Access Controller (DMAC)
Section 11 Direct Memory Access Controller (DMAC)
The DMA controller (hereafter DMAC) is a module that handles high-speed data transfer without CPU intervention in response to requests from software, on-chip peripheral I/O modules, or external pins (external modules). The DMAC itself does not distinguish between requests from on-chip peripheral I/O or external pins (external modules). The DMA supports data transfer between memory units, memory and I/O modules, and I/O modules.
11.1
Features
* Channel number: Up to eight channels (with four channels capable of external requests) * Transfer requests: Requests from 38 sources including software trigger, on-chip peripheral I/O, and external pins (external modules) * Maximum transfer bytes: 64 Mbytes * Address space: 4 Gbytes * Transfer data sizes: Single data transfer: 8, 16, 32, 64, and 128 bits Single operand transfer: 1, 2, 4, 8, 16, 32, 64, and 128 data Non-stop transfer: Up to the byte count "0" * Transfer mode: Cycle-stealing transfer (dual-address transfer) Pipelined transfer (dual-address transfer) * Maximum transfer speed: Cycle-stealing transfer: Minimum of three clock cycles per unit data transfer Pipelined transfer: Minimum of one clock cycle per unit data transfer * Transfer conditions: Unit operand transfer: a single sequence of single operand data transfer in response to a DMA request Sequential operand transfer: single operand transfers are repeated until the byte count reaches "0" Non-stop transfer: data is continuously transferred until the byte count reaches "0" in response to a single DMA request * Channel priority: Channel 0 > channel 1 > > channel 6 > channel 7 (this priority order is fixed)
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Section 11 Direct Memory Access Controller (DMAC)
* Interrupt request Two types of interrupt requests (generated when the byte count reaches "0") * Interrupt request signals for each channel * Interrupt request signal common to all channels * Reload function (source address, destination address, byte count) settable * Rotate function settable * DMAC stop/restart/suspend function settable
Notes: Terminologies in this section are as follows: 1. Single data transfer: Transfer in one read cycle and one write cycle by the DMAC (in the case of dual address transfer) 2. Single operand transfer: Continuous data transfer by the DMAC on one channel (amount of data to be transferred is set in a register) 3. One DMA transfer: Transferring a number of data, from the start address to the end address set in the byte count register 4. Channel number: n = 0 to 7 5. Request source number: k = 1 to 37, m = 0 to 37 6. BIU: Bus Interface Unit (peripheral module). One of the following four kinds according to the source or destination of transfer. BIU_E: External space (normal space and SDRAM space) BIU_P: Peripheral bus (1) (see figure 1.1) BIU_SH: Peripheral bus (2) (see figure 1.1), on-chip RAM space BIU_C: Peripheral bus (3) (see figure 1.1)
Figure 11.1 is a block diagram of the DMAC
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Section 11 Direct Memory Access Controller (DMAC)
DMA request from outside (DREQ) or on-chip peripheral circuit DMA end DMA acknowledge DMA active DMA interrupt request DMA common interrupt request DMA request transfer
DMAC Core
DMAC control circuit
(Work register) CPU control signal Memory load/store control Source address register Destination address register Byte count register Mode register Data buffer DMAC control signal
CPU I/F
Memory I/F
Ch0 DMA setting data
Current register Reload register
:
Chn DMA setting data Ch0 DMA transfer data
:
Chn DMA transfer data
On-chip memory DMAC [Legend] DMA request transfer: CPU I/F: Memory I/F: On-chip memory: Work register: DMAC control circuit: Data buffer:
Arbitration of DMA requests and generation of request signal to DMAC core Read/write control of register access from CPU Memory access control from CPU and DMAC core Stores DMAC setting data and transfer data Register the DMAC core refers to (access from CPU prohibited) DMAC control circuit DMA data buffer
Figure 11.1 DMAC Block Diagram
11.2
Input/Output Pins
Table 11.1 Pin Configuration
Name DREQm (m = 0 to 3) DACKm (m = 0 to 3) DACTm (m = 0 to 3) DTENDm (m = 0 to 3) I/O Input Output Output Output Function External request for DMA transfer DMA acknowledgement of external request for DMA transfer (active low) DMA active in externally requested DMA transfer (active low) Completion of externally requested DMA transfer (active low)
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Section 11 Direct Memory Access Controller (DMAC)
11.3
Register Descriptions
The DMAC has the following registers. All registers are initialized by a power-on reset or in deep standby mode. Table 11.2 Register Configuration
Channel 0 Register Name DMA current source address register 0 DMA current destination address register 0 Abbreviation R/W DMCSADR0 DMCDADR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460000 H'FF460004 H'FF460008 H'FF46000C H'FF460200 H'FF460204 H'FF460208 Access Size 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32
DMA current byte count register 0 DMCBCT0 DMA mode register 0 DMA reload source address register 0 DMA reload destination address register 0 DMMOD0 DMRSADR0 DMRDADR0
DMA reload byte count register 0 DMRBCT0 DMA control register A0 DMA control register B0 1 DMA current source address register 1 DMA current destination address register 1 DMCNTA0 DMCNTB0 DMCSADR1 DMCDADR1
H'00000000 H'FF460400 H'00000000 H'FF460404 Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460010 H'FF460014 H'FF460018 H'FF46001C H'FF460210 H'FF460214 H'FF460218
DMA current byte count register 1 DMCBCT1 DMA mode register 1 DMA reload source address register 1 DMA reload destination address register 1 DMMOD1 DMRSADR1 DMRDADR1
DMA reload byte count register 1 DMRBCT1 DMA control register A1 DMA control register B1 DMCNTA1 DMCNTB1
H'00000000 H'FF460408 H'00000000 H'FF46040C
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Section 11 Direct Memory Access Controller (DMAC)
Channel 2
Register Name DMA current source address register 2 DMA current destination address register 2
Abbreviation R/W DMCSADR2 DMCDADR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Address Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460020 H'FF460024 H'FF460028 H'FF46002C H'FF460220 H'FF460224 H'FF460228
Access Size 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32
DMA current byte count register 2 DMCBCT2 DMA mode register 2 DMA reload source address register 2 DMA reload destination address register 2 DMMOD2 DMRSADR2 DMRDADR2
DMA reload byte count register 2 DMRBCT2 DMA control register A2 DMA control register B2 3 DMA current source address register 3 DMA current destination address register 3 DMCNTA2 DMCNTB2 DMCSADR3 DMCDADR3
H'00000000 H'FF460410 H'00000000 H'FF460414 Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460030 H'FF460034 H'FF460038 H'FF46003C H'FF460230 H'FF460234 H'FF460238
DMA current byte count register 3 DMCBCT3 DMA mode register 3 DMA reload source address register 3 DMA reload destination address register 3 DMMOD3 DMRSADR3 DMRDADR3
DMA reload byte count register 3 DMRBCT3 DMA control register A3 DMA control register B3 DMCNTA3 DMCNTB3
H'00000000 H'FF460418 H'00000000 H'FF46041C
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Section 11 Direct Memory Access Controller (DMAC)
Channel 4
Register Name DMA current source address register 4 DMA current destination address register 4
Abbreviation R/W DMCSADR4 DMCDADR4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Address Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460040 H'FF460044 H'FF460048 H'FF46004C H'FF460240 H'FF460244 H'FF460248
Access Size 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32
DMA current byte count register 4 DMCBCT4 DMA mode register 4 DMA reload source address register 4 DMA reload destination address register 4 DMMOD4 DMRSADR4 DMRDADR4
DMA reload byte count register 4 DMRBCT4 DMA control register A4 DMA control register B4 5 DMA current source address register 5 DMA current destination address register 5 DMCNTA4 DMCNTB4 DMCSADR5 DMCDADR5
H'00000000 H'FF460420 H'00000000 H'FF460424 Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460050 H'FF460054 H'FF460058 H'FF46005C H'FF460250 H'FF460254 H'FF460258
DMA current byte count register 5 DMCBCT5 DMA mode register 5 DMA reload source address register 5 DMA reload destination address register 5 DMMOD5 DMRSADR5 DMRDADR5
DMA reload byte count register 5 DMRBCT5 DMA control register A5 DMA control register B5 DMCNTA5 DMCNTB5
H'00000000 H'FF460428 H'00000000 H'FF46042C
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Section 11 Direct Memory Access Controller (DMAC)
Channel 6
Register Name DMA current source address register 6 DMA current destination address register 6
Abbreviation R/W DMCSADR6 DMCDADR6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RW R R/W R/W
Initial Value Address Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460060 H'FF460064 H'FF460068 H'FF46006C H'FF460260 H'FF460264 H'FF460268
Access Size 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32 32 32 32 32 32 32 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
DMA current byte count register 6 DMCBCT6 DMA mode register 6 DMA reload source address register 6 DMA reload destination address register 6 DMMOD6 DMRSADR6 DMRDADR6
DMA reload byte count register 6 DMRBCT6 DMA control register A6 DMA control register B6 7 DMA current source address register 7 DMA current destination address register 7 DMCNTA6 DMCNTB6 DMCSADR7 DMCDADR7
H'00000000 H'FF460430 H'00000000 H'FF460434 Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'FF460070 H'FF460074 H'FF460078 H'FF46007C H'FF460270 H'FF460274 H'FF460278
DMA current byte count register 7 DMCBCT7 DMA mode register 7 DMA reload source address register 7 DMA reload destination address register 7 DMMOD7 DMRSADR7 DMRDADR7
DMA reload byte count register 7 DMRBCT7 DMA control register A7 DMA control register B7 Common DMA activation control register DMA interrupt control register DMA common interrupt control register DMA interrupt status register DMA transfer end detection register DMA arbitration status register DMCNTA7 DMCNTB7 DMSCNT DMICNT DMICNTA DMISTS DMEDET DMASTS
H'00000000 H'FF460438 H'00000000 H'FF46043C H'00000000 H'FF460500 H'00000000 H'FF460508 H'00000000 H'FF46050C H'00000000 H'FF460510 H'00000000 H'FF460514 H'00000000 H'FF460518
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Section 11 Direct Memory Access Controller (DMAC)
11.3.1
DMA Current Source Address Register (DMCSADR)
DMCSADR is a register used to specify the start address of the transfer source. The value in this register is transferred to the working source-address register at the start of DMA transfer. The default behavior is for the contents of the working source-address register to be returned on completion of single operand transfer. However, the contents of the working source address register are not returned in two cases: when the rotate setting (SAMOD = 011) is made for the source address and when the source-address reload function is enabled. In the latter case, the contents of the DMA reload source address register (DMRSADRn) are returned to this register on completion of DMA transfer. This register must be set before transfer is initiated, regardless of whether the reload function is enabled or disabled.
Bit: 31 30 29 28 27 26 25 24 CSA Initial value: -- R/W: R/W Bit: 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 CSA Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CSA
Initial Value Undefined
R/W R/W
Description Holds source address bits A31 to A0
Notes: 1. Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. * When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". * When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0). 2. Only write to this register when single operand transfer is not in process on the corresponding channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when both conditions are not satisfied.
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Section 11 Direct Memory Access Controller (DMAC)
11.3.2
DMA Current Destination Address Register (DMCDADR)
DMCDADR is a register used to specify the start address of the transfer destination. The value in this register is transferred to the working destination-address register at the start of DMA transfer. The default behavior is for the contents of the working destination-address register to be returned on completion of each single operand transfer. However, the contents of the working destinationaddress register are not returned in two cases: when the rotate setting (SAMOD = 011) is made for the destination address and when the destination-address reload function is enabled. In the latter case, the contents of the DMA reload destination address register (DMRDADRn) are returned to this register on completion of DMA transfer. This register must be set before transfer is initiated, regardless of whether the reload function is enabled or disabled.
Bit: 31 30 29 28 27 26 25 24 CDA Initial value: -- R/W: R/W Bit: 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 CDA Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name CDA
Initial Value
R/W
Description Holds destination address bits A31 to A0
Undefined R/W
Notes: 1. Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. * When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". * When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0). 2. Only write to this register when single operand transfer is not in process on the corresponding channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when both conditions are not satisfied.
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Section 11 Direct Memory Access Controller (DMAC)
11.3.3
DMA Current Byte Count Register (DMCBCT)
DMCBCT is a register used to specify the number of bytes to be transferred by DMA. The value in this register is transferred to the working byte-count register at the start of DMA transfer, and is then decremented by the number of bytes transferred on each unit data transfer. Decrementation is thus by the following values. * When the transfer size is set to 8 bits (SZSEL = "000"): -1 * When the transfer size is set to 16 bits (SZSEL = "001"): -2 * When the transfer size is set to 32 bits (SZSEL = "010"): -4 When the value in the working byte count register reaches H'000 0000, DMA transfer ends (an end due to byte count "0"). The corresponding bit of the DMA transfer end detection register (DMEDET) is set to 1. If the byte count reload function is disabled, the contents of the working byte count register are returned to this register at the moment the channel for DMA transfer switches or DMA transfer ends. If the byte count reload function is enabled, the contents of the DMA reload byte counter register (DMRBCTn) are returned to this register. This register must be set before transfer is initiated, regardless of whether the reload function is enabled or disabled.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 30 -- 0 R 14 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 -- R/W 9 -- R/W 8 CBC Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 25 24 23 22 21 20 CBC -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 19 18 17 16
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 26
25 to 0
CBC
Undefined R/W
Number of bytes to be DMA-transferred.
Notes: 1. Note that a setting of H'000 0000 leads to transfer of the maximum number of bytes, i.e. 64 Mbytes.
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Section 11 Direct Memory Access Controller (DMAC)
2. Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. * When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". * When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0). 3. Only write to this register when single operand transfer is not in process on the corresponding channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when both conditions are not satisfied.
11.3.4
DMA Reload Source Address Register (DMRSADR)
DMRSADR is used to set an address for reloading to the DMA current source address register (DMCSADRn). To enable reloading, set the DMA source address reload function enable bit (SRLOD) in DMA control register A (DMCNTAn) for the channel to "1". In this case, set both the DMA current source address register (DMCSADRn) and DMA reload source address register (DMRSADRn).
Bit: 31 30 29 28 27 26 25 24 RSA Initial value: -- R/W: R/W Bit: 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 RSA Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name RSA
Initial Value
R/W
Description Holds source address bits A31 to A0 for reloading
Undefined R/W
Note: Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. * * When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.5
DMA Reload Destination Address Register (DMRDADR)
DMRDADR is a register used to set an address for reloading to the DMA current destination address register (DMCDADRn). To enable reloading, set the DMA destination address reload function enable bit (DRLOD) in DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current destination address register (DMCDADRn) and DMA reload destination address register (DMRDADRn).
Bit: 31 30 29 28 27 26 25 24 RDA Initial value: -- R/W: R/W Bit: 15 -- R/W 14 -- R/W 13 -- R/W 12 -- R/W 11 -- R/W 10 -- R/W 9 -- R/W 8 RDA Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name RDA
Initial Value
R/W
Description Holds destination address bits A31 to A0 for reloading
Undefined R/W
Note: Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. * * When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.6
DMA Reload Byte Count Register (DMRBCT)
DMRBCT is a register used to set the number for reloading to the DMA current byte count register (DMCBCTn). To enable reloading, set the DMA byte count reload function enable bit (BRLOD) in the DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current byte count register (DMCBTn) and DMA reload byte count address register (DMRBCTn).
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 30 -- 0 R 14 29 -- 0 R 13 28 -- 0 R 12 27 -- 0 R 11 26 -- 0 R 10 -- R/W 9 -- R/W 8 RBC Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W 7 -- R/W 6 25 24 23 22 21 20 RBC -- R/W 5 -- R/W 4 -- R/W 3 -- R/W 2 -- R/W 1 -- R/W 0 19 18 17 16
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 26
25 to 0
RBC
Undefined R/W
Number of bytes to be DMA-transferred after reloading
Note: Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. * * When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.7
DMA Mode Register (DMMOD)
DMMOD controls the amount of data, data size selection, address direction, and various types of signal outputs.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 29 -- 0 R 13 28 -- 0 R 12 -- R/W 11 -- 0 R 27 26 25 24 23 -- -- R/W 8 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 18 17 16
OPSEL[3:0] -- R/W 10 -- R/W 9
SZSEL[2:0] -- R/W 2 -- R/W 1 -- R/W 0
SAMOD[2:0] -- R/W -- R/W -- R/W
DAMOD[2:0] -- R/W -- R/W -- R/W
SACT DACT DTCM[1:0] -- R/W -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
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Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial Value
R/W
Description Number of Data Transfers in Single Operand Transfer Selection These bits are used to specify the number of single data transfers in single operand transfer. The amount of data specified by this bit is transferred continuously. Channel arbitration is not executed until this amount of data has been transferred (single operand transfer). These bits are invalid when non-stop transfer (DSEL = "11") is specified in the DMA transfer condition selection bits (DSEL) of DMA control register A (DMCNTAn). Note: Set the DMA current byte count register (DMCBCTn) so that DMCBCTn becomes H'000 0000 on transfer of the last data of the operand transfer. * When the transfer size is set to 8 bits (SZSEL = "000"): Integer multiple of the number of data transferred in each single operand transfer (x 1, x 2, x 3, and so on) * When the transfer size is set to 16 bits (SZSEL = "001"): one operand transfer data number multiplied by two (x 2, x 4, x 6, and so on) * When the transfer size is set to 32 bits (SZSEL = "010"): one operand transfer data number multiplied by four (x 4, x 8, x 12, and so on) Operation is not guaranteed when values other than the above are set. For details, see section 11.3.3, DMA Current Byte Count Register (DMCBCT) and section 11.3.6, DMA Reload Byte Count Register (DMRBCT).) 0000: 1 datum 0001: 2 data 0010: 4 data 0011: 8 data 0100: 16 data 0101: 32 data 0110: 64 data 0111: 128 data 1000 to 1111: Setting prohibited
27 to 24 OPSEL [3:0]
Undefined R/W
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Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
23 to 19
18 to 16 SZSEL[2:0] Undefined R/W
Transfer Data Size Selection These bits are used to specify the number of bits transferred in each single data transfer. The unit for transfer can be selected as byte (8 bit), word (16 bit), or longword (32 bit). For details, see section 11.9, Units of Transfer and Positioning of Bytes for Transfer. Set the transfer size so that it doesn't exceed the widths of the data buses supported by the source and destination for DMA transfer. The bus widths of the data buses are fixed by hardware. 000: Byte (8 bits) 001: Word (16 bits) 010: Longword (32 bits) 011 to 111: Setting prohibited
15
0
R
Reserved This bit is always read as 0. The write value should always be 0.
14 to 12 SAMOD [2:0]
Undefined R/W
Source Address Direction Control These bits are used to specify the direction of counting for the source address. 000: Fixed 001: Incrementation 010: Decrementation 011: Rotation 100 to 111: Setting prohibited
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 11 Direct Memory Access Controller (DMAC)
Bit 10 to 8
Bit Name DAMOD [2:0]
Initial Value
R/W
Description Destination Address Direction Control These bits are used to specify the direction of counting for the source address. 000: Fixed 001: Incrementation 010: Decrementation 011: Rotation 100 to 111: Setting prohibited
Undefined R/W
7 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3
SACT
Undefined R/W
DMA Active Signal Output for Source This bit is used to control the output of the DMA-active signal (DACT) for the source corresponding to the requesting source setting in the DCTG bits. When this bit is set to "0", output of the DACT signal is disabled and the signal is fixed high unless the level changes because of the DACT bit setting. When this bit is set to "1", output of the DACT signal is valid ("L") from the next cycle after the start of the DMAC read cycle. However, while output of the DACT signal is enabled when the DMA request source selection bits (DCTG) are set for software triggering, a valid DACT signal cannot be output when the requesting source is an onchip peripheral circuit (DCTG), regardless of the setting of the SACT bits. 0: Stops output of the DMA-active signal for the source 1: Selects output of the DMA-active signal for the source during read access
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Section 11 Direct Memory Access Controller (DMAC)
Bit 2
Bit Name DACT
Initial Value
R/W
Description DMA Active Signal Output for Destination This bit is used to control the output of the DMA-active signal (DACT) for the destination corresponding to the request source setting in the DCTG bits. When this bit is set to "0", output of the DACT signal is disabled and fixed high unless the level changes because of the SACT bit setting. When this bit is set to "1", output of the DACT signal is valid ("L") from the next cycle after the start of the DMAC read cycle. However, while output of the DACT signal is enabled when the DMA request source selection (DCTG) bits are set for software triggering, a valid DACT signal cannot be output when the requesting source is an onchip peripheral circuit (DCTG), regardless of the setting of the DACT bit. 0: Stops output of the DMA-active signal for the destination 1: Selects output of the DMA-active signal for the destination during write access
Undefined R/W
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Section 11 Direct Memory Access Controller (DMAC)
Bit 1, 0
Bit Name DTCM[1:0]
Initial Value
R/W
Description DMA End Signal Output Control These bits are used to control the output of the DMA end signal (DTEND) when the DMA transfer end condition is detected. When the bits are set to "00", DTEND signals on completion of DMA transfer are disabled and the DTEND line is fixed high. When these bits are set to "10", the DTEND signal goes low (is active) in the cycle after the read cycle immediately preceding completion of DMA transfer. When these bits are set to "10", the DTEND signal is active in the cycle after the write cycle immediately preceding completion of DMA transfer. When these bits are set to "11", the DTEND signal is active for the period of one clock cycle at the same time as the DMA transfer end interrupt (for details, see figure 11.9.) However, while output of the DTEND signal is enabled when the DMA request source selection bits (DCTG) are set for software triggering, a valid DTEND signal cannot be output when the requesting source is an onchip peripheral circuit (DCTG), regardless of the setting of the DTEND bits. 00: Stops output of the DTEND signal 01: The DTEND signal is output on the last read cycle 10: The DTEND signal is output on the last write cycle 11: The DTEND signal is output after DMA has been completed
Undefined R/W
Note: Only write to this register when the corresponding channel is not engaged in single operand transfer (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when both conditions are not satisfied. When SACT and DACT are set to 1, output of a low DACT signal from the cycle following a DMAC read or write cycle is enabled.
Table 11.3 shows the DMA source/destination address registers. For details on the rotation address "indexing" mode, see section 11.11, Rotate Function. Note that when performing pipelined transfer to or from external devices and modules that support burst access, make sure to set the direction bits to select address incrementation ("001") or rotation ("011").
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Section 11 Direct Memory Access Controller (DMAC)
Table 11.3 Increment/Decrement for DMA Source/Destination Address Registers
Address Indexing Mode SAMOD or DAMOD "001" (plus direction) +1 +2 +4 "010" (minus direction) -1 -2 -4 "011" (rotation) +1 +2 +4
Transfer data size selection bits "000" SZSEL (fixed) "000" (8 bits) "001" (16 bits) "010" (32 bits) 0 0 0
11.3.8
DMA Control Register A (DMCNTA)
DMCNTA handles the selections of the transfer mode and the condition of transfer, control of reload functions, and selection of DMA sources.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 28 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 25 24 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 0 R/W 0 R/W 21 -- 0 R 5 20 -- 0 R 4 19 -- 0 R 3 18 -- 0 R 2 17 16
MDSEL[1:0] 0 R/W 13 -- 0 R 0 R/W 12 -- 0 R
DSEL[1:0] 0 R/W 9 0 R/W 8
STRG[1:0] 0 R/W 1 0 R/W 0
BRLOD SRLOD DRLOD
DCTG[5:0] 0 R/W 0 R/W 0 R/W 0 R/W
0 R/W
0 R/W
0 R/W
Bit 31, 30
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 Direct Memory Access Controller (DMAC)
Bit 29, 28
Bit Name MDSEL [1:0]
Initial Value 00
R/W R/W
Description DMA Transfer Mode Selection These bits are used to specify the DMA transfer mode. Setting these bits to "00" selects cycle-stealing transfer mode. Setting these bits to "01" selects pipelined transfer mode. Do not set these bits to "10" or "11". Operation is not guaranteed if these settings are made. For details, see section 11.4.1, DMA Transfer Mode. 00: Cycle-stealing transfer 01: Pipelined transfer 10: Setting prohibited 11: Setting prohibited Note: Pipelined transfer through a single BIU is not possible. For details on the BIU, see section 11.1, Features.
27, 26
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
25, 24
DSEL[1:0]
00
R/W
DMA Transfer Condition Selection These bits are used to specify the conditions of DMA transfer. Setting these bits to "00" selects single operand transfer. Setting these bits to "01" selects sequential operand transfer. Setting these bits to "11" selects non-stop transfer. For details, see section 11.4.2, DMA Transfer Condition. Do not set these bits to "10". Operation is not guaranteed if this setting is made. 00: Unit operand transfer 01: Sequential operand transfer 10: Setting prohibited 11: Non-stop transfer
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Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
23 to 18
17, 16
STRG[1:0]
00
R/W
Input Sense Mode Selection These bits specify input sense modes for DMA request signals input to the DMAC. The requesting source is that selected from among the possible sources by the DMA request source selection bits (DCTG). Select rising edge sense by setting these bits to "00" if the software trigger (DCTG = "000000") and pins DREQ0 to DREQ3 are selected as the source for DMA requests. Select falling edge sense by setting the bits to "10" when operation is with IIC3, SCIF, SSI, RCANET, MTU2, ADC, or ROM-DEC (DCTG = "000101" to "100101"). Table 11.4 shows the relationships between DMA request sources and the possible input sense modes. 00: Rising edge 01: High level 10: Falling edge 11: Low level
15 to 11
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
10
BRLOD
0
R/W
DMA Byte Count Reload Function Enable This bit specifies whether to reload the byte counter or not when the DMA transfer end condition is detected. When this bit is cleared to "0", no reload is executed. When this bit is set to "1" and the DMA transfer end condition is detected, the DMA current byte counter register (DMCBCTn) is reloaded with the value in the DMA reload byte count register (DMRBCTn). 0: Byte count reload function disabled 1: Byte count reload function enabled
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Section 11 Direct Memory Access Controller (DMAC)
Bit 9
Bit Name SRLOD
Initial Value 0
R/W R/W
Description DMA Source Address Reload Function Enable This bit specifies whether or not the source address is reloaded when the DMA transfer end condition is detected. When this bit is cleared to "0", reloading is not executed. When this bit is set to "1" and the DMA transfer end condition is detected, the DMA current source address register (DMCSADRn) is reloaded with the value of the DMA reload source address register (DMRSADRn). 0: Source address reload function disabled 1: Source address reload function enabled
8
DRLOD
0
R/W
DMA Destination Address Reload Function Enable This bit specifies whether or not the destination address is reloaded when the DMA transfer end condition is detected. When this bit is cleared to "0", reloading is not reexecuted. When this bit is set to "1" and the DMA transfer end condition is detected, the DMA current destination address register (DMCDADRn) is reloaded with the value of the DMA reload destination address register (DMRDADRn). 0: Destination address reload function disabled 1: Destination address reload function enabled
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 Direct Memory Access Controller (DMAC)
Bit 5 to 0
Bit Name DCTG[5:0]
Initial Value 000000
R/W R/W
Description DMA Request Source Selection These bits specify the source of DMA requests. When selecting IIC3, SCIF, RCAN-ET, MTU2, or ADC as the source, set the DMA transfer request enable bits in DREQER0 to DREQER3 of the interrupt controller. For the settings of DREQER0-3, see section 6, Interrupt Controller (INTC). 000000: Software trigger 000001: DREQ0 pin 000010: DREQ1 pin 000011: DREQ2 pin 000100: DREQ3 pin 000101: IIC3 0ch RX 000110: IIC3 0ch TX 000111: IIC3 1ch RX 001000: IIC3 1ch TX 001001: IIC3 2ch RX 001010: IIC3 2ch TX 001011: SCIF 0ch RX 001100: SCIF 0ch TX 001101: SCIF 1ch RX 001110: SCIF 1ch TX 001111: SCIF 2ch RX 010000: SCIF 2ch TX 010001: SCIF 3ch RX 010010: SCIF 3ch TX 010011: SCIF 4ch RX 010100: SCIF 4ch TX 010101: SCIF 5ch RX 010110: SCIF 5ch TX 010111: SCIF 6ch RX
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Section 11 Direct Memory Access Controller (DMAC)
Bit 5 to 0
Bit Name DCTG[5:0]
Initial Value 000000
R/W R/W
Description 011000: SCIF 6ch TX 011001: SCIF 7ch RX 011010: SCIF 7ch TX 011011: SSI 0ch 011100: SSI 1ch 011101: RCAN-ET 0ch 011110: RCAN-ET 1ch 011111: MTU2 0ch 100000: MTU2 1ch 100001: MTU2 2ch 100010: MTU2 3ch 100011: MTU2 4ch 100100: ADC 100101: ROM-DEC 100110 to 111111: Setting prohibited
Note: Only write to bits of this register other than the reload function enable bits (BRLOD, SRLOD, and DRLOD) when a transfer operation is not in process on the corresponding channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when both conditions are not satisfied.
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Section 11 Direct Memory Access Controller (DMAC)
Table 11.4 Relationships between DMA Request Sources and Input Sense Mode
STRG Bit Settings DMA Request Source Software trigger DREQ0 pin DREQ1 pin DREQ2 pin DREQ3 pin IIC3 0ch RX IIC3 0ch TX IIC3 1ch RX IIC3 1ch TX IIC3 2ch RX IIC3 2ch TX SCIF 0ch RX SCIF 0ch TX SCIF 1ch RX SCIF 1ch TX SCIF 2ch RX SCIF 2ch TX SCIF 3ch RX SCIF 3ch TX SCIF 4ch RX SCIF 4ch TX SCIF 5ch RX SCIF 5ch TX SCIF 6ch RX SCIF 6ch TX SCIF 7ch RX SCIF 7ch TX 00: Rising Edge Sense x x x x x x x x x x x x x x x x x x x x x x 01: High Level Sense x x x x x x x x x x x x x x x x x x x x x x x 10: Falling Edge Sense x 11: Low Level DCTG Bit Sense Setting x x x x x x x x x x x x x x x x x x x x x x x 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010
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Section 11 Direct Memory Access Controller (DMAC)
STRG Bit Settings DMA Request Source SSI 0ch SSI 1ch RCAN-ET 0ch RCAN-ET 1ch MTU2 0ch MTU2 1ch MTU2 2ch MTU2 3ch MTU2 4ch ADC ROM-DEC 00: Rising Edge Sense x x x x x x x x x x x 01: High Level Sense x x x x x x x x x x x 10: Falling Edge Sense 11: Low Level DCTG Bit Sense Setting x x x x x x x x x x x 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101
[Legend] x: Setting prohibited : Can be set
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Section 11 Direct Memory Access Controller (DMAC)
11.3.9
DMA Control Register B (DMCNTB)
DMCNTB enables or disables DMA transfer, clears the DMA transfer enable bit, and also clears the internal state. In addition, this register can check the status of a DMA request.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 DEN 0 R/W 8 ECLR 0 R/W 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 DREQ 0 R/W 0
DSCLR
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 25
24
DEN
0
R/W
DMA Transfer Enable This bit is used to enable or disable DMA transfer on the corresponding channel. Clearing this bit to "0" disables DMA transfer. Setting this bit to "1" enables DMA transfer. For the activation of DMA transfer, see section 11.4.3, DMA Activation. Even when this bit is clear, the input of a DMA request to the DMAC can change the value of the DMA request bit (DREQ). When the DMA transfer enable clear bit (ECLR) is set to "1", this bit is automatically cleared to "0" on detection of the DMA transfer end condition. Clearing this bit to "0" during DNA transfer can be used to stop channel operation at the end of the current single operand transfer. For details, see section 11.6, Suspending, Restarting, and Stopping of DMA Transfer. 0: DMA transfer disabled 1: DMA transfer enabled
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Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
23 to 17
16
DREQ
0
R/W
DMA Request This bit is used to check whether a DMA request is currently present. Furthermore, when the software trigger is selected (DCTG = "000000") by the DMA request source selection bits (DCTG), DMA requests operate through this bit. The value of this bit changes according to the state of DMA request input to the DMAC regardless of the settings of the DMAC module activation bit (DMST) and DMA transfer enable bit (DEN). The conditions for setting and clearing the bit are determined by the DMA request source selection bits (DCTG) and input sense mode selection bits (STRG) as described below. (a) When software triggering is selected (DCTG = "000000") by the DMA request source selection bits (DCTG). * Condition for setting to "1" This bit is set to "1" when a "1" is written to it by software, generating the DMA request. * Condition for clearing to "0" This bit is cleared to "0" by either of the below events. Software writing a "0" to the bit The start of the transfer operation corresponding to the bit setting
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Section 11 Direct Memory Access Controller (DMAC)
Bit 16
Bit Name DREQ
Initial Value 0
R/W R/W
Description (b) When a source other than the software trigger is selected (DCTG = "000000") by the DMA request source selection bits (DCTG) and a level sense has been selected * Condition for setting to "1" This bit is set to "1" when the DMA request input level matches that specified in the input sense selection bits (STRG), i.e. when a DMA request exists. * Condition for clearing to "0" This bit is cleared to "0" when the level specified by the input sense selection bits (STRG) and the level on the DMA request input do not match, i.e. when there is no DMA request. The DMA request is not retained if it disappears before being accepted; that is, the DMA request bit (DREQ) is cleared to "0". To use the DREQ bit with a level sense, continue the DMA request level until the request has been accepted. Note: When a requesting source other than the software trigger is selected, do not write "1" to the DMA request bit (DREQ). If "1" is written to this bit, operation is not guaranteed.
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Section 11 Direct Memory Access Controller (DMAC)
Bit 16
Bit Name DREQ
Initial Value 0
R/W R/W
Description (c) When a source other than the software trigger is selected (DCTG = "000000") by the DMA request source selection bits (DCTG) and an edge sense has been selected * Condition for setting to "1" The DREQ bit is set to "1" when the edge specified by the input sense selection bits (STRG) is encountered, i.e. when a DMA request exists. Once this bit has been set to "1", regardless of the subsequent state of the DMA request signal, the DMA request bit (DREQ) remains set until a condition for clearing to "0" has been satisfied. * Condition for clearing to "0" This bit is cleared to "0" by either of the events listed below. Software writing a "0" to this bit The start of operand transfer corresponding to the bit Notes: 1. In a case where a source other than software triggering is selected, do not write "1" to the DMA request bit (DREQ). If "1" is written to this bit, operation is not guaranteed. 2. After setting the DMA request source selection bits (DCTG) and the input sense mode selection bits (STRG) in DMA control register A (DMCNTAn), be sure to clear the DMA request bit (DREQ) for the channel to "0" and enable DMA transfer (DMST = "1" and DEN = "1"). 0: No DMA request 1: DMA requested
15 to 9
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 Direct Memory Access Controller (DMAC)
Bit 8
Bit Name ECLR
Initial Value 0
R/W R/W
Description DMA Transfer Enable Clear This bit specifies whether or not to clear the DMA transfer enable bit (DEN) to "0" when the DMA transfer end condition is detected. When this bit is cleared to "0", the DMA transfer enable bit (DEN) is not cleared to "0" even when the DMA transfer end condition is detected. When this bit is set to "1", the DMA transfer enable bit (DEN) is cleared to "0" when the DMA transfer end condition is detected. Note: When a value is written to the DMA transfer enable clear bit for a channel handling single operand transfer, operation is not guaranteed.
0: Detection of the DMA transfer end condition does not clear the DMA transfer enable bit to 0 1: Detection of the DMA transfer end condition clears the DMA transfer enable bit to 0 7 to 1 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 Direct Memory Access Controller (DMAC)
Bit 0
Bit Name DSCLR
Initial Value 0
R/W R/W
Description DMA Internal State Clear Writing a "1" to this bit stops DMA transfer in the middle of a sequence of DMA transfer, suspending the remainder of the transfer and initializing the internal state of the DMAC. Writing a "1" to this bit only clears the transfer state of the DMAC internal circuit. The other registers are not initialized. Writing "0" is invalid and a "1" written to this bit is not retained. This bit is always read as "0". Note: This bit must only be written to when the corresponding channel is not in the midst of single operand transfer (DASTS in the channel corresponding to the DMA arbitration status register (DMASTS) is "0") and DMA transfer has been disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B (DMCNTBn) is set to "0"). Operation is not guaranteed when this bit is written to while these conditions do not apply. When reading: Always read as "0" When writing: 0: Invalid 1: Initializes the DMAC's internal state
Note: When the software trigger is selected as the DMA request source, the DMA request bit (DREQ) can be set to "1" regardless of the settings of the DMA transfer enable bit (DEN) and DMAC module activation bit (DMST) and whether or not a transfer operation is currently in progress. However, even if the software trigger is selected as the DMA request source, only clear the DMA request bit (DREQ) to "0" or write to the DMAC internal state clearing bit (DSCLR) when a transfer operation is not in process on the corresponding channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer has been disabled (DMST in the DMA activation control register (DMSCNT) or DEN in the DMA control register B (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when these conditions are not satisfied.
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Section 11 Direct Memory Access Controller (DMAC)
11.3.10 DMA Activation Control Register (DMSCNT) DMSCNT controls the operation of the DMAC.
Bit: 31 -- Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 30 -- 0 R 14 -- 0 R 29 -- 0 R 13 -- 0 R 28 -- 0 R 12 -- 0 R 27 -- 0 R 11 -- 0 R 26 -- 0 R 10 -- 0 R 25 -- 0 R 9 -- 0 R 24 -- 0 R 8 -- 0 R 23 -- 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 DMST 0 R/W 0 -- 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 17
16
DMST
0
R/W
DMAC Module Activation This bit is used to stop or activate the DMAC module. When this bit is cleared to "0", the DMAC module stops. When this bit is set to "1", the DMAC module is operational. For details, see section 11.4.3, DMA Activation, and section 11.6, Suspending, Restarting, and Stopping of DMA Transfer. 0: DMAC halted 1: DMAC operating
15 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 11 Direct Memory Access Controller (DMAC)
11.3.11 DMA Interrupt Control Register (DMICNT) DMICNT controls DMA interrupts for the respective channels.
Bit: 31 30 29 28 27 26 25 24 23 -- 0 R/W 10 -- 0 R 0 R/W 9 -- 0 R 0 R/W 8 -- 0 R 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0 -- 0 R
DINTM Initial value: 0 R/W: R/W Bit: 15 -- Initial value: R/W: 0 R 0 R/W 14 -- 0 R 0 R/W 13 -- 0 R 0 R/W 12 -- 0 R 0 R/W 11 -- 0 R
Bit
Bit Name
Initial Value All 0
R/W R/W
Description DMA Interrupt Control These bits are used to control whether DMA transfer end interrupts for the respective channels should be generated for the interrupt controller. When a bit is cleared to "0", interrupt requests for the corresponding channel are not generated. When these bits are set to "1", DMA transfer end interrupts for the corresponding channel are generated for the interrupt controller. For details, see section 11.5.2, DMA Interrupt Requests. 0: Interrupt disabled 1: Interrupt enabled
31 to 24 DINTM
23 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel 1. ...24: channel 7).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.12 DMA Common Interrupt Control Register (DMICNTA) DMICNTA determines which channels contribute to the output of a common interrupt request signal.
Bit: 31 30 29 28 27 26 25 24 23 -- 0 R/W 10 -- 0 R 0 R/W 9 -- 0 R 0 R/W 8 -- 0 R 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0 -- 0 R
DINTA Initial value: 0 R/W: R/W Bit: 15 -- Initial value: R/W: 0 R 0 R/W 14 -- 0 R 0 R/W 13 -- 0 R 0 R/W 12 -- 0 R 0 R/W 11 -- 0 R
Bit
Bit Name
Initial Value All 0
R/W R/W
Description DMA Common Interrupt Request Signal Control These bits are used to determine which channels contribute to the output of a common interrupt request signal. Channels for which the DINTA bit is set to "1" contribute to the output of a common interrupt request signal. Channels for which the DINTA bit is cleared to "0" do not contribute to the output of a common interrupt request signal. Only the states of channels for which the corresponding DINTA bit is set to "1" are reflected in the DMA interrupt status register (DMISTS) when a common interrupt request signal has been generated. For details, see section 11.5.2, DMA Interrupt Requests. 0: The channel does not contribute to the output of a common interrupt requests 1: The channel contributes to the output of a common interrupt request
31 to 24 DINTA
23 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note: Bits 31 to 24 correspond to channel 0 to 7, respectively (31: channel 0, 30: channel 1, ..., 24: channel 7).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.13 DMA Interrupt Status Register (DMISTS) DMISTS consists of the DMA interrupt request status bits.
Bit: 31 30 29 28 27 26 25 24 23 -- 0 R 10 -- 0 R 0 R 9 -- 0 R 0 R 8 -- 0 R 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0 -- 0 R
DISTS Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 0 R 14 -- 0 R 0 R 13 -- 0 R 0 R 12 -- 0 R 0 R 11 -- 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description DMA Interrupt Request Status These bits are used to verify the sources of common interrupt requests for the interrupt controller. * Condition for setting to "1" When the DMA common interrupt request signal control bit (DINTA) for a channel is set to "1" and the DMA transfer end condition is detected, the corresponding bit is set to "1". The setting of the DMA interrupt control bit (DINTM) does not affect this setting. * Condition for clearing to "0" A DISTS bit is cleared to "0" by clearing the corresponding DMA transfer end condition detection bit (DEDET) in the DMA transfer end detection register (DMEDET). For details, see section 11.5.2, DMA Interrupt Requests. 0: No interrupt request 1: An interrupt request exists
31 to 24 DISTS
23 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Notes: 1. This register is read-only. 2. Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel 1, ..., 24: channel 7).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.14 DMA Transfer End Detection Register (DMEDET) DMEDET verifies the status of DMA transfer end detection for each channel. Writing 0 to the DEDET bit is invalid and 1 written to the bit is not retained.
Bit: 31 30 29 28 27 26 25 24 23 -- 0 R/W 10 -- 0 R 0 R/W 9 -- 0 R 0 R/W 8 -- 0 R 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0 -- 0 R
DEDET Initial value: 0 R/W: R/W Bit: 15 -- Initial value: R/W: 0 R 0 R/W 14 -- 0 R 0 R/W 13 -- 0 R 0 R/W 12 -- 0 R 0 R/W 11 -- 0 R
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Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial Value All 0
R/W R/W
Description Values read: DMA Transfer End Condition Detection Values written: DMA Transfer End Condition Detection, DMA Interrupt Request Status Clear These bits are used to verify the status of DMA transfer end condition detection for each channel. Reading this register does not automatically clear the bits. Once a bit has been set to "1", the value is retained in the register as long as the bit is not cleared by software or a reset. * Condition for setting to "1" When the DMA transfer end condition is detected, these bits are set to "1". * Condition for clearing to "0" These bits are cleared to "0" by writing a "1" to the bits to be cleared. Write "0" to bits that are not to be cleared. While a bit is clear, it cannot be set to "1" by a write operation. When the DMA transfer end interrupt is in use and an interrupt request generated for a given channel starts to be handled, write a "1" to the corresponding DMA transfer end condition detection (DEDET) bit. When the DMA transfer end condition detection (DEDET) bits are cleared to "0", the DMA interrupt request status bit (DISTS) is also cleared. Values read: 0: DMA transfer end condition not detected 1: DMA transfer end condition detected Values written: 0: Invalid 1: Clears DMA transfer end condition detection and DMA interrupt request status
31 to 24 DEDET
23 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel 1, ..., 24: channel 7).
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Section 11 Direct Memory Access Controller (DMAC)
11.3.15 DMA Arbitration Status Register (DMASTS) DMASTS verifies the status of DMA transfer on each channel. Writing 0 to the DASTS bit is invalid and 1 written to the bit is not retained.
Bit: 31 30 29 28 27 26 25 24 23 -- 0 R 10 -- 0 R 0 R 9 -- 0 R 0 R 8 -- 0 R 0 R 7 -- 0 R 22 -- 0 R 6 -- 0 R 21 -- 0 R 5 -- 0 R 20 -- 0 R 4 -- 0 R 19 -- 0 R 3 -- 0 R 18 -- 0 R 2 -- 0 R 17 -- 0 R 1 -- 0 R 16 -- 0 R 0 -- 0 R
DASTS Initial value: R/W: Bit: 0 R 15 -- Initial value: R/W: 0 R 0 R 14 -- 0 R 0 R 13 -- 0 R 0 R 12 -- 0 R 0 R 11 -- 0 R
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Section 11 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial Value All 0
R/W R
Description When read: DMA Arbitration Status When written: DMA Arbitration Status Clear These bits are used to verify the status of DMA transfer on each channel. * * * Condition for setting to "1" The bit for a channel in which operand transfer (non-stop transfer) has started is set to "1". Condition for clearing to "0" These bits are cleared to "0" by either of the following events. Correct completion of single operand transfer (non-stop transfer). A "1" is written to the bit. These bits are not cleared to "0" when DMAC operation is forcibly ended by the external DMA transfer forcible end signal. Write "1" to these bits to clear them. Note: In DMA transfer to external devices, the DMA arbitration status bit (DASTS) can be cleared before the end of external bus access (once the last data-write operation has started).
31 to 24 DASTS
When read: 0: Operand transfer not in progress 1: Operand transfer in progress When written: 0: Invalid 1: Clears DMA arbitration status 23 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel 1, ..., 24: channel 7)
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Section 11 Direct Memory Access Controller (DMAC)
11.4
11.4.1
Operation
DMA Transfer Mode
There are two DMA transfer modes cycle-stealing mode and pipelined mode. These modes are selectable through the setting of the DMA transfer mode select bits (MDSEL) in DMA Control Register A (DMCNTAn). Figure 11.2 gives examples of how bus mastership alternates between the DMAC and CPU in various DMA transfer modes. (1) Cycle-stealing Transfer Mode
Cycle-stealing transfer mode is selected when the DMA transfer mode select bits are set to "00". In cycle-stealing transfer mode, the DMAC leaves at least one cycle between the read and write access cycles of each single data transfer. During this interval, the CPU can access the same target BIU as the source or destination of its own operations. For details on the BIU, see section 11.1, Features. (2) Pipelined Transfer Mode
Pipelined transfer mode is selected when the DMA transfer mode select bits are set to "01". In pipelined transfer mode, DMAC activates the bus for read or write access, or both, on consecutive cycles. Therefore, the CPU cannot access the target BIU as a source or destination during single operand transfer. Pipelined transfer through a single BIU is not possible either.
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Section 11 Direct Memory Access Controller (DMAC)
Cycle steal transfer mode (transfer between different BIU) System clock Single operand transfer Single operand transfer
Read
Read Write Write
Read Write
Read Write
DMAC
CPU
(1)
(2)
(1)
(2)
(1)
(2)
(1)
(2)
(1) CPU access to other than BIU on DMAC read side is possible (2) CPU access to other than BIU on DMAC write side is possible Cycle steal transfer mode (transfer in the same BIU) System clock Single operand transfer Single operand transfer
Read
Read Write Write
Read Write
Read Write
DMAC
CPU
(3)
(3)
(3)
(3)
(3)
(3)
(3) CPU access to other than BIU on DMAC read/write side is possible Pipeline transfer mode (transfer between different BIU) System clock Single operand transfer Single operand transfer
Read Read Read Read
Read Read Read Read Write Write Write Write
DMAC
Write Write Write Write
CPU
(4)
(5)
(6)
(4)
(5)
(6)
(4) CPU access to other than BIU on DMAC read side is possible (5) CPU access to other than BIU on DMAC read/write side is possible (6) CPU access to other than BIU on DMAC write side is possible
Figure 11.2 Examples of the Alternation of Bus Mastership between the DMAC and CPU in Various DMA Transfer Modes
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Section 11 Direct Memory Access Controller (DMAC)
11.4.2
DMA Transfer Condition
There are three methods of DMA transfer the unit transfer operation, sequential operand transfer, and non-stop transfer. These are selectable through the setting of the DMA transfer condition selection bits (DSEL) in DMA Control Register A (DMCNTAn). Each of the conditions is explained below. Table 11.5 and figure 11.3 are a list and chart of the DMA transfer conditions. (1) Unit Operand Transfer
Setting the DMA transfer condition selection bits (DSEL) to 00 selects this mode. A single DMA request initiates continuous transfer of the number of bytes selected by the OPSEL bits in the DMA mode register. If the byte counter does not reach 0 in single operand transfer, the DMA transfer is completed by repeating unit transfer operations until the byte counter does reach 0. (2) Sequential Operand Transfer
Setting the DMA transfer condition selection bits (DSEL) to 01 selects this mode. A single DMA request initiates transfer in units of the number of bytes selected by the OPSEL bits in the DMA mode register (i.e., unit transfer operations) until the DMA transfer is complete (i.e., until the byte counter reaches zero). Channel arbitration is performed on completion of each unit transfer operation. Transfer on the channel for the sequential operand transfer automatically resumes unless there is a DMA request from a higher-priority channel. (3) Non-Stop Transfer
Setting the DMA transfer condition selection bits (DSEL) to 11 selects this mode. A single DMA request initiates DMA transfer that continues until the transfer is complete (i.e., until the byte counter reaches zero). There are no gaps for channel arbitration, so even DMA requests from highpriority channels will not be accepted.
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Section 11 Direct Memory Access Controller (DMAC)
Table 11.5 List of DMA Transfer Conditions
DMA Transfer Condition Select Bits (DSEL) DSEL = "00"
DMA Transfer Condition Unit operand transfer * The number of bytes selected for transfer in single operand transfer (by the OPSEL bits) is transferred in response to one DMA request. Channel arbitration is performed on completion of each single operand transfer. Transfer in response to a DMA request proceeds in unit transfer operations until the byte counter reaches "0". Channel arbitration is performed on completion of each single operand transfer. Transfer in response to a DMA request proceeds continuously until the byte counter reaches "0" by one DMA request. Once transfer has started, channel arbitration is not done until it is complete.
Remarks
* DSEL = "01"
Sequential operand transfer *
* DSEL = "11"
Non-stop transfer *
OPSEL bit is disabled
*
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Section 11 Direct Memory Access Controller (DMAC)
Unit operand transfer DMA request Interrupt DTEND Byte count Transfer data Operand 1 Operand 2 Operand 3
Channel arbitration Sequential operand transfer DMA request Interrupt DTEND
Channel arbitration
Byte count Transfer data Operand 1 Operand 2 Operand 3
Channel arbitration Non-stop transfer DMA request Interrupt DTEND Transfer data
Channel arbitration
Byte count
Figure 11.3 DMA Transfer Conditions Relations between the mode and conditions of DMA transfer are shown in table 11.6.
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Section 11 Direct Memory Access Controller (DMAC)
Table 11.6 Relations between the mode and conditions of DMA transfer.
DMA transfer mode condition Unit operand transfer DSEL = "00" Transfer mode Cycle-stealing transfer MDSEL = "00" Pipelined transfer MDSEL = "01" OK (between any two BIUs) OK (between any two BIUs) Sequential operand transfer Non-stop transfer DSEL = "01" OK (between any two BIUs) OK (between any two BIUs) DSEL = "11" OK (between any two BIUs) Mainly OK* (between any two BIUs other than BIU_E)
Note:
*
The restriction means that non-stop transfer to the external SDRAM in pipelined transfer mode cannot be set up.
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Section 11 Direct Memory Access Controller (DMAC)
11.4.3 (1)
DMA Activation
Initial Settings of the DMAC
Initial settings must be made in each of the relevant registers before the DMA transfer enable bit is set (DEN = "1"). These settings cannot be changed once transfer has started. An example of DMAC registers that require initial settings is given below. 1. DMA mode register (DMMODn) 2. DMA control register A (DMCNTAn) 3. DMA control register B (DMCNTBn) 4. DMA current source address register (DMCSADRn) 5. DMA reload source address register (DMRSADRn) when the reload function is used 6. DMA current destination address register (DMCDADRn) 7. DMA reload destination address register (DMRDADRn) when the reload function is used 8. DMA current byte count register (DMCBCTn) 9. DMA reload byte count register (DMRBCTn) when the reload function is used 10. DMA interrupt control register (DMICNT) when an interrupt is used 11. DMA common interrupt control register (DMICNTA) when an interrupt is used 12. DMA transfer enable bit (DEN) 13. DMA activation control register (DMSCNT) (2) DMA Activation
DMA transfer for a channel is enabled by setting the DMA transfer enable bit (DEN) in DMA control register B for the channel and the DMAC module activation bit (DMST) in the DMAC activation register (DMSCNT) to "1". When multiple DMA transfer requests are present, there is no complex mechanism for the determination of channel priority. The DMA request that corresponds to the highest priority channel is simply accepted and DMA transfer on that channel starts. Whether a DMA request on a given channel is or is not present can be verified by testing the value of the DMA request bit (DREQ) in DMA control register B (DMCNTBn) for that channel. When a DMA request is accepted and DMA transfer starts, the DMA arbitration status bit (DASTS) for the corresponding channel in the DMA arbitration status register (DMASTS) is set to "1".
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Section 11 Direct Memory Access Controller (DMAC)
11.5
11.5.1
Completion of DMA Transfer and Interrupts
Completion of DMA Transfer
When the value H'0000 0000 is transferred from the working byte count register to the DMA current byte count register (DMCBCTn) (all data has been transferred), the DMA transfer end condition is fulfilled and one DMA transfer is complete. The operations following detection of the DMA transfer end condition are as follows. * DMA transfer end condition The DMA transfer end condition detection bit (DEDET) for the corresponding channel in the DMA transfer end detection register (DMEDET) is set to "1". * Interrupt request generation An interrupt request is generated for the interrupt controller according to the settings of the DMA interrupt control register (DMICNT) and the DMA common interrupt control register (DMICNTA). * Output of DMA end signal The DMA end signal (DTENDm) is output according the setting of the DMA end signal output control bit (DTCM) in the DMA mode register (DMMODn) for the channel. * Clearing the DMA transfer enable bit (DEN) If the DMA transfer enable clear bit (ECLR) in DMA control register B (DMCNTBn) is set to "1", the DEN bit in the DMA control register B (DMCNTBn) is cleared to "0", suspending any subsequent DMA transfer for the channel. If the DMA transfer enable clear bit (ECLR) is clear ("0"), the DEN bit is not cleared. * Reloading the source address register If the DMA source address reload function enable bit (SRLOD) in the DMA control register A (DMCNTAn) is set to "1", the DMA current source address register (DMCSADRn) is reloaded with the value in the DMA reload source address register (DMRSADRn).
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Section 11 Direct Memory Access Controller (DMAC)
* Reloading the destination address register If the DMA destination address reload function enable bit (DRLOD) in DMA control register A (DMCNTAn) is set to "1", the DMA current destination address register (DMCDADRn) is reloaded with the value in the DMA reload destination address register (DMRDADRn). * Reloading the byte count register If the DMA byte count reload function enable bit (BRLOD) in the DMA control register A (DMCNTAn) is set to "1", the DMA current byte count register (DMCBCTn) is reloaded with the value in the DMA reload byte count register (DMRBCTn). Note: 11.5.2 If reloading is not to be executed, set ECLR = "1" to ensure that the DEN bit is cleared. DMA Interrupt Requests
The DMAC generates two types of interrupt request signal for the interrupt controller. One consists of the interrupt request signals for the individual channels (DMINT_N) and the other is the common interrupt request signal in which the interrupt request signals from all channels are pooled to produce a common interrupt request signal (DMINTA_N). Figure 11.4 is a block diagram showing how the per-channel and common interrupt requests are generated. When a DMA transfer ends and the DMA interrupt control bit (DINTM) for the corresponding channel in the DMA interrupt control register (DMICNT) is set to "1", interrupt requests for the corresponding channel are generated. Only those channels for which the DMA common interrupt request signal control bit (DINTA) in the DMA common interrupt control register (DMICNTA) is set to "1" contribute to the output of common interrupt request. Once generated, an interrupt request is cleared to "0" by writing a "1" to the corresponding DMA transfer end condition detection bit (DEDET).
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Section 11 Direct Memory Access Controller (DMAC)
DMA interrupt control register
ch0 ch1 ch2
chn ch0 ch1 ch2 chn
DMA transfer end detection register
DMINT0_N DMINT1_N DMINT2_N DMINTn_N
To interrupt controller (INTC)
DMA interrupt control register
ch0 ch1 ch2 chn
DMA interrupt status register
DMINTA_N
Figure 11.4 Block Diagram Showing Generation of the Per-Channel and Common Interrupt Request Signals
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Section 11 Direct Memory Access Controller (DMAC)
11.5.3
DMA End Signal Output
The form in which the DMA end signal (DTENDm) is output differs with the setting of the DMA end signal output control bit (DTCM) in the DMA mode register (DMMODn) for the corresponding channel. * When DTCM is set to "00", output of the DTEND signal is not valid so the signal remains fixed at the "H" level when and after the DMA transfer ends. * When DTCM is set to "01", the DTEND signal becomes active (low) one cycle after the start of the read cycle immediately before the end of DMA transfer (the read cycle for the last data transfer). * When DTCM is set to "10", the DTEND signal becomes active for one cycle after the write cycle immediately before the end of DMA transfer (the write cycle for the last data transfer). * When DTCM is set to "11", the DTEND signal becomes active for one clock cycle at the same time as the DMA transfer end interrupt is generated. Output of the DTEND signal is not valid in the case of DMA requests from external peripheral circuits, so the signal remains fixed to "H" regardless of the setting of this bit. Charts of the timing of DMA end signal output are given in figure 11.5. Note: The BSC is provided with a write buffer. Writing data to this buffer while writing to the external devices stops bus access in the chip. Because of this, in DMA transfer to or from external devices, the DTEND signal become disabled ("H") before the end of external bus access. In this case the DTEND signal is not synchronized with the external bus access.
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Section 11 Direct Memory Access Controller (DMAC)
Cycle-stealing transfer mode One DMA transfer Single operand transfer (read 1 wait)
CKIO DMA (S) DMA (D) DACK DTEND (00) DTEND (01) DTEND (10) DTEND (11) DMINT_N
High RD1 WR1 RD2 WR2 RD1 WR1 RD2 WR2
Single operand transfer (read 1 wait)
DTCM setting Pipelined transfer mode One DMA transfer Single operand transfer (read 0 wait)
CKIO DMA (S) DMA (D) DACK DTEND (00) DTEND (01) DTEND (10) DTEND (11) DMINT_N
High RD1 RD2 RD3 RD4 WR1 WR2 WR3 WR4 RD1 RD2 RD3 RD4
Last read Last write End of of one DMA of one DMA one DMA transfer transfer transfer
Single operand transfer (read 0 wait)
WR1 WR2 WR3 WR4
DTCM setting [Legend] DMA (S): Internal access cycle on DMAC source side DMA (D): Internal access cycle on DMAC destination side
Last read Last write End of of one DMA of one DMA one DMA transfer transfer transfer
Figure 11.5 Timing of DMA End Signal Output
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Section 11 Direct Memory Access Controller (DMAC)
11.6
11.6.1
Suspending, Restarting, and Stopping of DMA Transfer
Suspending and Restarting DMA Transfer
Transfer on all channels of the DMAC can be suspended by clearing the DMST bit in the DMA activation control register (DMSCNT) to "0". Transfer on a specific channel can also be suspended by clearing the DMA transfer enable bit (DEN) in DMA control register B (DMCNTBn) for that channel. If the DMST bit or the corresponding DEN bit is cleared to "0" while single operand transfer or sequential operand transfer is in progress, transfer is suspended on completion of the current single operand transfer regardless of the transfer mode (whether transfer is in cycle-stealing or pipelined mode). When transfer in the non-stop transfer condition is in progress, DMA transfer is not suspended and continues to completion (until the byte counter reaches "0") even if the DMST bit or corresponding DEN bit is cleared to "0". To restart DMA transfer on a channel for which transfer has been suspended, set (to "1") whichever of DMST and the corresponding DEN bit has been cleared. 11.6.2 Stopping DMA Transfer on Any Channel
To stop transfer on any channel, suspend transfer on that channel and then initialize the interior state of the DMAC for that channel by setting the DMAC internal state clear bit (DSCLR) in the corresponding DMA control register B (DMCNTBn). In this case, only the transfer state of the DMAC internal circuits is initialized; the registers retain their values.
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Section 11 Direct Memory Access Controller (DMAC)
11.7
11.7.1
DMA Requests
Sources of DMA Requests
The 38 sources of DMA requests include the software trigger and various DMA request signal inputs. The DMA request source for each channel is specified by the DMA request source select bits (DTCG) in the corresponding DMA control register A (DMCNTAn). 11.7.2 Synchronous Circuits for DMA Request Signals
For each channel of the DMAC, a synchronous circuit is incorporated to manage DMA requests, which are asynchronously input. As a result, a blank period of a few clock cycles appears between activation of the DMA request and actual reflection of the request in the DMA request bits (DREQ) of DMA control register B (DMCNTBn). Figure 11.6 shows an example of timing between the input of a DMA request and the DMA request bit.
Edge sense setting (falling edge sense) System clock
DMA request input DMA request bit
DMA request bit is on input of the valid edge Level sense setting (low level sense) System clock DMA request input DMA request bit DMA request bit is set when the active level has been sampled at the end of two clock periods.
DMA request bit is maintained regardless of changes in the level of the DMA request input
[Legend] : Sampling point for DMA request
DMA request bit is cleared one cycle after sampling of the inactive level.
Figure 11.6 Example of Timing between DMA Request Input and DMA Request Bit
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Section 11 Direct Memory Access Controller (DMAC)
11.7.3
Sense Mode for DMA Requests
When pins DREQ0 to DREQ3 (DCTG = "000001" to "000100") are specified by the DMA request source selection bits (DTCG), either level sense or edge sense might be required. Make the appropriate setting ("01" or "11" for level sense and "00" or "10" for edge sense) in the input sense selection bits (STRG) of DMA control register A (DMCNTAn). When the software trigger (DCTG = "000000") is selected as a DMA request source, set these bits to "00" to select the rising-edge sense. When IIC3, SCIF, SSI, RCAN-ET, MTU2, or ADC (DCTG = "000101" to "100101") is selected, set the bits to "10" to select the falling-edge sense. Table 11.4 shows the relationships between the DMA request sources and input sense mode. Below are further details on level- and edge-sense operation. (1) Level Sense
When a level sense is specified (STRG = "01" or "11"), one level of the DMA request signal indicates the DMA request. Since DMA requests detected in this way are not retained in the DMAC, maintain the requesting level until acceptance of the DMA request has been confirmed. Figure 11.7 is an example of DMA request reception processing when a level sense has been selected.
Start of single operand transfer System clock Read
Maintain DMA request level until DMA acknowledge output is activated to indicate acceptance of the request
DMA state
Write
DMA request input (low level sense)
DMA acknowledge output DMA request bit [Legend] : Sampling point for DMA request
Figure 11.7 Example of DMA Request Reception Processing for a Level Sense When a level sense has been selected, DMA request bit for the channel is masked over the period from the start of the last write access of single operand transfer until four clock pulses (system
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Section 11 Direct Memory Access Controller (DMAC)
clock) after the end of the single operand transfer. This provides a margin in which continued requests for DMA transfer on the same channel are rejected. Figure 11.8 shows the period over which DMA request bit is masked when a level sense has been selected.
Single operand transfer Start of channel arbitration System clock DMA state DMA request input (low level sense)
Read
Write
DMA acknowledge output DMA request bit
[Legend] : Sampling point for DMA requests
(Period of masking for the DMA request bit) The period of the unit transfer operation in this example is short; non-recognition of the DMA request during the masking period prevents a DMA request that is cleared too late from affecting the next channel-arbitration period.
Figure 11.8 Period over which DMA Request Bit is Masked when a Level Sense is Selected Therefore, for a channel on which level sense has been selected, even when the DMA request signal level is maintained (requesting further DMA transfer) well after the DMA request has been accepted and handled, DMA requests on other channels, if they exist, are accepted. This is because the DMA request on the channel on which level sense has been selected is not considered to exist during the DMA request bit masking period. In the case of sequential operand transfer, masking is only applied from the end of operand transfer, i.e. when the byte count is 0. The DMA request is not masked while the byte count is non-zero, so channel arbitration is executed without masking of the DMA request during the actual unit transfer operation. In the case of non-stop transfer, masking is only enabled from the end of the transfer operation, i.e. when the byte count is 0.
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Section 11 Direct Memory Access Controller (DMAC)
If the DMA transfer is not done sequentially, the DMA request must be canceled within three cycles after the end of single operand transfer. (2) Edge sense
When an edge sense is specified (STRG = "00" or "10"), the rising or falling edge of the DMA request signal indicates a DMA request. When the selected edge is detected, the DMA request bit (DREQ) in the DMA control register B (DMCNTBn) is set to "1". After that, the value in the DMA request bit (DREQ) is retained regardless of shifts in the level of the DMA request signal. After the DMA request has been accepted and the DAM acknowledge signal output, the DMA request bit (DREQ) is automatically cleared to "0". Since DMA requests are internally retained for a channel in edge sense mode, further occurrences of the selected edge of the DMA request signal are ignored since the DMA request bit (DREQ) has already been set back to "1". Figure 11.9 is an example of DMA request reception processing when an edge sense is selected.
Start of single operand transfer System clock
DMA state
Read
Write
Read
DMA request input (falling edge sense)
DMA acknowledge output DMA request bit
The DMA request bit is set on detection of the selected edge. The DMA request is thus maintained despite further changes in the level of the DMA request signal.
The DMA request bit is set on detection of the selected edge. The DMA request is thus maintained despite further changes in the level of the DMA request signal.
When the DMA request is accepted, the DMA acknowledge signal is activated and the DMA request bit is cleared.
[Legend] : Sampling point for DMA requests
Figure 11.9 Example of DMA Request Reception Processing when an Edge Sense is Selected
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Section 11 Direct Memory Access Controller (DMAC)
11.8
11.8.1
Determining DMA Channel Priority
Channel Priority Order
Channel priority is allocated in descending order from channel 0; that is priority follows the below relation, where P indicates priority. Pchannel 0 > Pchannel 1 > Pchannel 3 ... Pchannel 6 > Pchannel 7. This order is fixed. 11.8.2 Operation during Multiple DMA Requests
The DMAC determines the priority every time single operand transfer is performed. When a DMA request with a higher priority is generated during transfer for one channel, the transfer for the higher-priority channel only starts after the end of the current operand transfer. Figure 11.10 shows overall operation when multiple DMA requests are generated. The thick lines in the figure indicate the periods over which the DMA request signals are at the low level. Here channels 0, 2 and 3 are set to a level sense and channel 1 is set to an edge sense. 1. Since the channel 2 request is masked, it is regarded as non-existent. Thus, transfer on channel 3 starts up. 2. Since channel 0 has the highest priority, transfer on this channel starts up. 3. Since channel 2 has the higher priority of the requests at this point, transfer on this channel restarts. 4. Transfer on channel 3 is restarted as there are no other requests at this point. 5. When the DMA requests are simultaneously generated for channels 0, 1, and 3, transfer on channel 0 starts up because it has the highest priority. 6. After the transfer on channel 0 is complete, transfer on channel 1 starts up because it has the second highest priority. 7. A further DMA request (the selected edge) is received on channel 1 while DMA transfer is in progress. Transfer on channel 1 is thus restarted after completion of the current round of transfer on channel 1. No masking period applies in the case of edge sensing. 8. On completion of the transfer on channel 1, transfer on channel 3 starts up since there are no other requests. 9. No transfer starts up immediately after the end of the unit transfer operation on channel, since channel 3 requests are masked and there are no other requests. Transfer on channel 3 only restarts after the end of the masking period.
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Section 11 Direct Memory Access Controller (DMAC)
DMA request (ch 0) DMA request (ch 1) DMA request (ch 2) DMA request (ch 3) DMA receive channel
ch2DMA (1) ch3DMA (2) ch0DMA (3) ch2DMA (4) ch3DMA (5) ch0DMA (6) ch1DMA ch1DMA ch3DMA (8) (9) ch3DMA Masked period
Masked period
Masked period
(7)
Notes: 1. Channels 0, 2 and 3 are set to level sensing. 2. Channel 1 is set to edge sensing. 3. Thick lines indicate periods where the corresponding DREQ bits are set.
Figure 11.10 Overall Operation during Multiple DMA Requests 11.8.3 Output of the DMA Acknowledge and DNA Active Signals
The settings of the DMA active signal output control bits for the source and destination (SACT or DACT) in the corresponding DMA mode register control the output of the DMA active signal (DACT) for a channel. When SACT is set to 1, the DACT signal is activated in response to read access. When DACT is set to 1, the DACT signal is activated in response to write access. When both SACT and DACT are set to 1, the DACT signal is activated in response to read and write access. However, DACT signals are not activated for DMA requests from external peripheral circuits, regardless of the setting of this bit. The DMA acknowledge signal (DACK) is output throughout each single operand transfer. Figure 11.11 is the timing chart for DMA acknowledge and DMA active signal output. Note: The BSC is provided with a write buffer. Writing data to this buffer while writing to the external devices stops bus access in the chip. Because of this, in DMA transfer to or from external devices, the DACT or DACK signal become disabled ("H") before the end of external bus access. In this case, these signals are not synchronized with the external bus access.
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Section 11 Direct Memory Access Controller (DMAC)
Cycle-stealing transfer mode
Single operand transfer (read 0 wait)
CKIO DMA (S) DMA (D) RD1 WR1 RD2 WR2
DACT (SACT = 0, DACT = 0)
High
DACT (SACT = 1, DACT = 0)
DACT (SACT = 0, DACT = 1)
DACT (SACT = 1, DACT = 1)
DACK
Pipeline transfer mode CKIO DMA (S) DMA (D) RD1
Single operand transfer (read 0 wait)
RD2
RD3 WR1
RD3 WR2 WR3 WR3
DACT (SACT = 0, DACT = 0)
High
DACT (SACT = 1, DACT = 0)
DACT (SACT = 0, DACT = 1)
DAC T (SACT = 1, DACT = 1)
DACK [Legend] DMA (S): Internal cycles of source-side access by the DMAC DMA (D): Internal cycles of destination-side access by the DMAC
Figure 11.11 Timing of DMA Acknowledge and DNA Active Signal Output
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Section 11 Direct Memory Access Controller (DMAC)
11.9
Units of Transfer and Positioning of Bytes for Transfer
The number of bits (transfer data size) for a single data transfer can be selected from among the byte (8 bits), word (16 bits), and the longword (32 bits). Figure 11.12 is an example of DMA data-byte control for a 32-bit wide bus. This transfer data size cannot exceed either of the data bus bit widths supported by the source and destination for DMA transfer. The data bus widths are fixed by the hardware.
8-bit transfer Source side State of address bits H'FF00 4000 H'FF00 4001 H'FF00 4002 H'FF00 4003
DMAC internal 32-bit data buffers D0 to D31 D0 toD31
Destination side H'0040 0203 H'0040 0204 H'0040 0205 H'0040 0206 State of address bits
16-bit transfer Source side State of address bits H'FF00 8002 H'FF00 8004
DMAC internal 32-bit data buffers D0 to D31 D0 to D31 Destination side H'FF60 0806 H'FF60 0808 State of address bits
: Byte/bytes being handled
Figure 11.12 Example of DMA Data-Byte Control for 32-bit Bus Width
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Section 11 Direct Memory Access Controller (DMAC)
11.10
Reload Function
Reloading can be set up for each transfer parameter (source address, destination address, or byte count) of a channel through the setting of the individual reload function enable bits in the corresponding DMA control register A (DMCNTAn). When the DMA transfer end condition is detected, DMA transfer parameters specified for reloading are automatically reloaded. (1) Reload and Current Registers
If reloading is not in use, only place the data in the current register. When reloading is in use, place data in both the reload and current registers. Do not write to the current register during single operand transfer. If data is written to the register during continuous operation, further operation is not guaranteed. Although the reload register can be set during single operand transfer, ensure that this is not the last single operand transfer of a DMA transfer. If the setting is executed after that point, the new setting may not be reloaded on completion of the DMA transfer. (2) Continuous Transfer to Dispersed areas
The reload function enables continuous transfer to dispersed areas. Writing to the DMA reload source/destination address register (DMRSADRn/ DMRDADRn) or the DMA reload byte count register (DMRBCTn) before the completion of transfer provides a way of preparing the parameters for the next transfer without affecting the current DMA transfer (current registers). This enables the use of a single channel for the continuous transfer of multiple transfer blocks consisting of different numbers of bytes to and from different transfer areas over a single channel. Figure 11.13 shows an example of the transfer of blocks between dispersed areas with the aid of the reload function.
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Section 11 Direct Memory Access Controller (DMAC)
Blocks allocated to dispersed locations Address Start < DMAC register state > Destination address register Undefined AAAA Byte count register Undefined An Reload Current
Software processing
AAAA
(1) Block A setting
Block A byte number An
BBBB AAAA
Bn An
Reload Current
(2) Block B setting
(3) Reload function enable bit set Start of DMAC transfer End BBBB BBBB Start
Block B transfer setting: automatic load
(4) DMA transfer enable set Reload
Bn
BBBB
Bn
Current
Block B byte number Bn
Interrupt on block A transfer end End
CCCC BBBB
Cn Bn
Reload Current
(5) Block C setting
CCCC
Block C transfer setting: automatic load
Cn
Reload
CCCC Block C byte number Cn
Start End
CCCC
Cn
Current
(6) Reload function enable bit set
Block A, B, C transfer end
Figure 11.13 Example of Transferring Blocks between Dispersed Areas by Using the Reload Function.
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Section 11 Direct Memory Access Controller (DMAC)
11.11
Rotate Function
When rotation is selected as the address "indexing" mode, the address is incremented. On completion of single operand transfer, the value in a working source or working destination address register for which rotation has been selected returns to the value of the source or destination address register (DMCSADRn or DMCDADRn) for the corresponding channel. Figure 11.14 is an example of transfer using the rotate function (source: rotation, destination: incrementation).
Number of bytes for transfer: 96 bytes Number of transfers in single operand transfer: 8 bytes
Current destination address setting value
Block 1 8 data (32 bytes) Block 2 8 data (32 bytes) Block 3 8 data (32 bytes)
Data transferred in single operand transfer Data transferred in single operand transfer Data transferred in single operand transfer Total data transferred
Current source address setting value
Source data for transfer 8 data (32 bytes)
Interrupt request DMA end
Data transfer
Operand transfer
Operand transfer
Operand transfer
Figure 11.14 Example of Transfer Using the Rotate Function (Source: Rotate, Destination: Increment)
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Section 11 Direct Memory Access Controller (DMAC)
11.12
Transfer Speed
Transfer speeds are calculated as shown below. (1) * * * * Conditions for Calculation DMA transfer mode: cycle-stealing transfer mode/pipelined transfer mode Transfer unit (one data size): properly aligned 32-bit data Operating clock: 60 MHz Number of cycles for access to external devices: four cycles for reading; and two cycles for writing. Formulae Used in Calculation
(2)
* Cycle-stealing transfer mode
(data size in unit data transfer) / (number of read cycles + number of write cycles + one idle cycle) x operating clock
* Pipelined transfer mode
(data size in unit data transfer) / (whichever is larger of number of read or write cycles) x operating clock
Note: During transfer in the pipelined transfer mode, most read and write cycles overlap. An example of the calculation of transfer speed is given below. (a) Transfer between On-chip RAM
Maximum speed of transfer between on-chip RAM (0 wait) and on-chip RAM (0 wait). * Cycle-stealing transfer mode
4 bytes / (1 read cycle + 1 write cycle + 1 idle cycle) x 60 MHz = 79.8 Mbytes/sec
* Pipelined transfer mode Pipelined transfer through a single BIU is not possible. See section 11.4.1 (2), Pipelined Transfer Mode.
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Section 11 Direct Memory Access Controller (DMAC)
(b)
Transfer to External Devices
Maximum transfer speed from an on-chip CPU block as the source (0 wait) to an external device (2 write cycles). * Cycle-stealing transfer mode
4 bytes / (1 read cycle + 2 write cycles + 1 idle cycle) x 60 MHz = 60 Mbytes/sec
* Pipelined transfer mode
4 bytes / (2 write cycles)x 60 MHz = 120 Mbytes/sec
Maximum transfer speed from an external device (4 read cycles) to an on-chip CPU block source (0 wait) * Cycle-stealing transfer mode
4 bytes / (4 read cycles + 1 write cycle + 1 idle cycle) x 60 MHz = 39.6 Mbytes/sec
* Pipelined transfer mode
4 bytes / (4 read cycles)x 60 MHz = 60 Mbytes/sec
Maximum transfer speed from an external device (4 read cycles) to an external device (2 write cycles) * Cycle-stealing transfer mode
4 bytes / (4 read cycles + 2 write cycles + 1 idle cycle) x 60 MHz = 34.2 Mbytes/sec
* Pipelined transfer mode No pipelined transfer is possible between the external devices. Note: Access to external devices is controlled by the settings of the BSC control registers. For details, see section 9, Bus State Controller (BSC).
11.13
Usage Note
11.13.1 Note on Making a Transition To Software Standby Mode or Deep Standby Mode If the SLEEP instruction is executed to make a transition to software standby mode or deep standby mode during transfer by the DMAC, the DMAC stops its operation without waiting for the completion of the transfer. Thus, the DMA transfer is not guaranteed. Therefore, when making a transition to software standby mode or deep standby mode, wait for the completion of the DMA transfer or stop the DMA transfer to execute the SLEEP instruction.
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Section 11 Direct Memory Access Controller (DMAC)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels.
12.1
Features
* Up to 16 pulse input/output lines and three pulse input lines * Selection of eight counter input clocks for each channel (four clocks for channel 5) * The following operations can be set for channels 0 to 4: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 12-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0, 3, and 4 * Phase counting mode settable independently for each of channels 1 and 2 * Cascade connection operation * Fast access via internal 16-bit bus * 28 interrupt sources * Automatic transfer of register data * A/D converter start trigger can be generated * Module standby mode can be settable * A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible. * AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible. * Dead time compensation counter available in channel 5 * In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.1 MTU2 Functions
Item Count clock Channel 0 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRE_0 TGRC_0 TGRD_0 TGRF_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture Channel 1 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TGRA_1 TGRB_1 -- Channel 2 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 -- Channel 3 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOC3A TIOC3B TIOC3C TIOC3D TGR compare match or input capture -- Channel 4 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D TGR compare match or input capture -- Channel 5 P/1 P/4 P/16 P/64
General registers
TGRU_5 TGRV_5 TGRW_5 --
General registers/ buffer registers I/O pins
TIOC1A TIOC1B
TIOC2A TIOC2B
Input pins TIC5U TIC5V TIC5W TGR compare match or input capture -- -- -- -- -- -- -- -- --
Counter clear function
TGR compare match or input capture -- -- --
TGR compare match or input capture -- -- --
Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset PWM mode AC synchronous motor drive mode -- --
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Item Phase counting mode Buffer operation Dead time compensation counter function DMAC activation
Channel 0 -- --
Channel 1 -- --
Channel 2 -- --
Channel 3 -- --
Channel 4 -- --
Channel 5 -- --
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture
TGR compare match or input capture and TCNT overflow or underflow TGRA_4 compare match or input capture TCNT_4 underflow (trough) in complementary PWM mode
TGR compare match or input capture
A/D converter start TGRA_0 trigger compare match or input capture TGRE_0 compare match
TGRA_1 compare match or input capture
TGRA_2 compare match or input capture
TGRA_3 compare match or input capture
--
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Item Interrupt sources
Channel 0 7 sources *
Channel 1 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow
Channel 2 4 sources *
Channel 3 5 sources
Channel 4 5 sources
Channel 5 3 sources Compare match or input capture 5U Compare match or input capture 5V Compare match or input capture 5W
Compare * match or input capture 0A
Compare * match or input capture 2A
Compare * match or input capture 3A Compare * match or input capture 3B
Compare * match or input capture 4A Compare * match or input capture 4B Compare * match or input capture 4C Compare match or input capture 4D
*
Compare * match or input capture 0B
*
Compare * match or input capture 2B
*
Compare * match or input capture 0C *
*
Overflow Underflow
*
Compare * match or input capture 3C
Underflow *
*
Compare match or input capture 0D
*
Compare * match or input capture 3D
* * *
Compare match 0E Compare match 0F Overflow
*
Overflow
*
Overflow or underflow
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Item
Channel 0
Channel 1 --
Channel 2 --
Channel 3 --
Channel 4 * A/D converter start request at a match between TADCOR A_4 and TCNT_4 * A/D converter start request at a match between TADCOR B_4 and TCNT_4
Channel 5 --
A/D converter start -- request delaying function
Interrupt skipping function
--
--
--
*
Skips TGRA_3 compare match interrupts
*
Skips TCIV_4 interrupts
--
[Legend] : Possible --: Not possible
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 12.1 shows a block diagram of the MTU2.
TIORH TIORL
TMDR
Channel 3
TSR
Control logic for channels 3 and 4
TOCR
TGCR
Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D
Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4
TIORH TIORL
TMDR
Channel 4
TSR
TIER
TCR
TGRC TDDR
TGRC
TIER
TCR
TCNTS
TCDR
TOER
TCBR
TGRD
TGRA
TGRB
TCNT
TGRD
TGRA
TGRB
TCNT
Channel 2
Control logic for channels 0 to 2
TIOR
TIORH TIORL
TMDR
Channel 0
TSR
Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B
TMDR
Channel 1
TSR
TIER
TCR
Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 External clock: TCLKA TCLKB TCLKC TCLKD
Module data bus
Input pins Channel 5: TIC5U TIC5V TIC5W
Channel 5
TCNTW
TCNTU
TCNTV
TGRW
TGRU
TGRV
TIOR
TIER
TCR
TSR
Channel 5: TGIU_5 TGIV_5 TGIW_5
Control logic
Common
TSYR
Peripheral bus
BUS I/F
TMDR
TSR
TSTR
A/D converter conversion start signal
TGRA
TGRB
TCNT
[Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register
Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2 TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: TGRU: TGRV: TGRW: Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer general register U Timer general register V Timer general register W
TGRA
TIOR
TIER
TCR
TGRB TGRC TGRD TGRB
TCNT
TGRA
TGRE
TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: Timer cycle data register TCBR: Timer cycle buffer register TDDR: Timer dead time data register
Figure 12.1 Block Diagram of MTU2
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TIER
TCR
TGRF
TCNT
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.2
Input/Output Pins
Table 12.2 Pin Configuration
Channel Pin Name I/O Function
Common TCLKA TCLKB TCLKC TCLKD 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 TIOC1A TIOC1B 2 TIOC2A TIOC2B 3 TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D 5 TIC5U TIC5V TIC5W
Input External clock A input pin (Channel 1 phase counting mode A phase input) Input External clock B input pin (Channel 1 phase counting mode B phase input) Input External clock C input pin (Channel 2 phase counting mode A phase input) Input External clock D input pin (Channel 2 phase counting mode B phase input) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin
Input TGRU_5 input capture input/external pulse input pin Input TGRV_5 input capture input/external pulse input pin Input TGRW_5 input capture input/external pulse input pin
Note: For the pin configuration in complementary PWM mode, see table 12.54 in section 12.4.8, Complementary PWM Mode.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3
Register Descriptions
The MTU2 has the following registers. For details on register addresses and register states during each process, refer to section 30, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 12.3 Register Configuration
Channel Register Name Abbreviation R/W Initial value Address Access Size
0
Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer general register E_0 Timer general register F_0 Timer interrupt enable register 2_0 Timer status register 2_0 Timer buffer operation transfer mode register_0
TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'00 H'00 H'00 H'00 H'00 H'C0
H'FFFE4300 H'FFFE4301 H'FFFE4302 H'FFFE4303 H'FFFE4304 H'FFFE4305
8, 16, 32 8 8, 16 8 8, 16, 32 8 16 16, 32
H'0000 H'FFFE4306 H'FFFF H'FFFE4308
H'FFFF H'FFFE430A 16 H'FFFF H'FFFE430C 16, 32 H'FFFF H'FFFE430E 16 H'FFFF H'FFFE4320 H'FFFF H'FFFE4322 H'00 H'C0 H'00 H'FFFE4324 H'FFFE4325 H'FFFE4326 16, 32 16 8, 16 8 8
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel
Register Name
Abbreviation R/W
Initial value
Address
Access Size
1
Timer control register_1 Timer mode register_1
TCR_1 TMDR_1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'00 H'00 H'00 H'00 H'C0
H'FFFE4380 H'FFFE4381 H'FFFE4382 H'FFFE4384 H'FFFE4385
8, 16 8 8 8, 16, 32 8 16 16, 32
Timer I/O control register_1 TIOR_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer input capture control register 2 Timer control register_2 Timer mode register_2 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2
H'0000 H'FFFE4386 H'FFFF H'FFFE4388
H'FFFF H'FFFE438A 16 H'00 H'00 H'00 H'00 H'00 H'C0 H'FFFE4390 H'FFFE4000 H'FFFE4001 H'FFFE4002 H'FFFE4004 H'FFFE4005 8 8, 16 8 8 8, 16, 32 8 16 16, 32
Timer I/O control register_2 TIOR_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2
H'0000 H'FFFE4006 H'FFFF H'FFFE4008
H'FFFF H'FFFE400A 16
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel
Register Name
Abbreviation R/W
Initial value
Address
Access Size
3
Timer control register_3 Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3 Timer status register_3 Timer buffer operation transfer mode register_3
TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 TSR_3 TBTM_3
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'00 H'00 H'00 H'00 H'00
H'FFFE4200 H'FFFE4202 H'FFFE4204 H'FFFE4205 H'FFFE4208
8, 16, 32 8, 16 8, 16, 32 8 8, 16 16, 32 16, 32
H'0000 H'FFFE4210 H'FFFF H'FFFE4218
H'FFFF H'FFFE421A 16 H'FFFF H'FFFE4224 H'FFFF H'FFFE4226 H'C0 H'00 16, 32 16
H'FFFE422C 8, 16 H'FFFE4238 8, 16
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel
Register Name
Abbreviation R/W
Initial value
Address
Access Size
4
Timer control register_4 Timer mode register_4 Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer general register C_4 Timer general register D_4 Timer status register_4 Timer buffer operation transfer mode register_4 Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4
TCR_4 TMDR_4 TIORH_4 TIORL_4 TIER_4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TSR_4 TBTM_4
TADCORA_4
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'00 H'00 H'00 H'00 H'00
H'FFFE4201 H'FFFE4203 H'FFFE4206 H'FFFE4207 H'FFFE4209
8 8 8, 16 8 8 16
H'0000 H'FFFE4212
H'FFFF H'FFFE421C 16, 32 H'FFFF H'FFFE421E 16 H'FFFF H'FFFE4228 16, 32
H'FFFF H'FFFE422A 16 H'C0 H'00 H'FFFE422D 8 H'FFFE4239 8 16, 32
H'FFFF H'FFFE4244
TADCORB_4
R/W
H'FFFF H'FFFE4246
16
TADCOBRA_4
R/W
H'FFFF H'FFFE4248
16, 32
TADCOBRB_4
R/W
H'FFFF H'FFFE424A
16
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel
Register Name
Abbreviation R/W
Initial value
Address
Access Size
5
Timer counter U_5 Timer general register U_5 Timer control register U_5 Timer I/O control register U_5 Timer counter V_5 Timer general register V_5 Timer control register V_5 Timer I/O control register V_5 Timer counter W_5
TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 TIORV_5 TCNTW_5
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
H'0000 H'FFFE4080 H'FFFF H'FFFE4082 H'00 H'00 H'FFFE4084 H'FFFE4086
16, 32 16 8 8 16, 32 16 8 8
H'0000 H'FFFE4090 H'FFFF H'FFFE4092 H'00 H'00 H'FFFE4094 H'FFFE4096
H'0000 H'FFFE40A0 16, 32 H'FFFF H'FFFE40A2 16 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'01 H'FFFE40A4 8 H'FFFE40A6 8 H'FFFE40B0 8 H'FFFE40B2 8 H'FFFE40B4 8 H'FFFE40B6 8 H'FFFE4280 H'FFFE4281 H'FFFE4282 H'FFFE4284 8, 16 8 8 8
Timer general register W_5 TGRW_5 Timer control register W_5 Timer I/O control register W_5 Timer status register_5 Timer interrupt enable register_5 Timer start register_5 Timer compare match clear register Common Timer start register TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5
TCNTCMPCLR
TSTR
Timer synchronous register TSYR Timer counter synchronous TCSYSTR start register Timer read/write enable register TRWER
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel
Register Name
Abbreviation R/W
Initial value
Address
Access Size
Common Timer output master enable TOER to 3 and register 4 Timer gate control register TGCR Timer output control register TOCR1 1 Timer output control register TOCR2 2 Timer cycle data register Timer dead time data register Timer subcounter Timer cycle buffer register Timer interrupt skipping set register Timer interrupt skipping counter Timer buffer transfer set register Timer dead time enable register Timer output level buffer register Timer A/D converter start request control register Timer waveform control register TCDR TDDR TCNTS TCBR TITCR TITCNT TBTER TDER TOLBR TADCR TWCR
R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W
H'C0 H'80 H'00 H'00
H'FFFE420A 8 H'FFFE420D 8 H'FFFE420E 8, 16 H'FFFE420F 8 16, 32 16 16, 32 16 8, 16 8 8 8 8 16 8
H'FFFF H'FFFE4214 H'FFFF H'FFFE4216 H'0000 H'FFFE4220 H'FFFF H'FFFE4222 H'00 H'00 H'00 H'01 H'00 H'FFFE4230 H'FFFE4231 H'FFFE4232 H'FFFE4234 H'FFFE4236
H'0000 H'FFFE4240 H'00 H'FFFE4260
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.1
Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped.
Bit: 7 6 CCLR[2:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 5 4 3 2 1 TPSC[2:0] 0 R/W 0 R/W 0 R/W 0
CKEG[1:0] 0 R/W 0 R/W
Bit 7 to 5
Bit Name CCLR[2:0]
Initial Value 000
R/W R/W
Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 12.4 and 12.5 for details.
4, 3
CKEG[1:0]
00
R/W
Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. When P/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges
2 to 0
TPSC[2:0]
000
R/W
Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 12.6 to 12.10 for details.
[Legend] x: Don't care
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.4 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Channel 0, 3, 4 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
1
0
0 1
1
0 1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Table 12.5 CCLR0 to CCLR2 (Channels 1 and 2)
Channel 1, 2 Bit 7 Bit 6 Reserved*2 CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.6 TPSC0 to TPSC2 (Channel 0)
Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Table 12.7 TPSC0 to TPSC2 (Channel 1)
Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT_2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.8 TPSC0 to TPSC2 (Channel 2)
Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 12.9 TPSC0 to TPSC2 (Channels 3 and 4)
Channel 3, 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 Internal clock: counts on P/256 Internal clock: counts on P/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.10 TPSC1 and TPSC0 (Channel 5)
Channel 5 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64
Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value should always be 0.
12.3.2
Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped.
Bit: 7 -- Initial value: R/W: 0 R 6 BFE 0 R/W 5 BFB 0 R/W 4 BFA 0 R/W 0 R/W 3 2 1 0
MD[3:0] 0 R/W 0 R/W 0 R/W
Bit 7
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6
BFE
0
R/W
Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. When TGRF is used as a buffer register, TGRF compare match is generated. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 5
Bit Name BFB
Initial Value 0
R/W R/W
Description Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated in other than complementary PWM mode. TGRD compare match is generated in complementary PWM mode. When compare match occurs during the tb period in complementary PWM mode, TGRD is set. Therefore, set the TGIED bit in the timer interrupt enable register_3/4 (TIER_3/4) to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W
Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated in other than complementary PWM mode. TGRC compare match is generated in complementary PWM mode. When compare match for channel 4 occurs during the tb period in complementary PWM mode, TGFC is set. Therefore, set the TGIEC bit in the timer interrupt enable register_4 (TIER_4) to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation
3 to 0
MD[3:0]
0000
R/W
Modes 0 to 3 These bits are used to set the timer operating mode. See table 12.11 for details.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.11 Setting of Operation Mode by Bits MD0 to MD3
Bit 3 MD3 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 0 X 0 1 1 0 1 Description Normal operation Setting prohibited PWM mode 1 PWM mode 2*1 Phase counting mode 1*2 Phase counting mode 2*2 Phase counting mode 3*2 Phase counting mode 4*2 Reset synchronous PWM mode*3 Setting prohibited Setting prohibited Setting prohibited Complementary PWM mode 1 (transmit at crest)*3 Complementary PWM mode 2 (transmit at trough)*3 Complementary PWM mode 2 (transmit at crest and trough)*3
[Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.3
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit: 7 6 5 4 3 2 1 0 IOB[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W IOA[3:0] 0 R/W 0 R/W 0 R/W
Bit 7 to 4
Bit Name IOB[3:0]
Initial Value 0000
R/W R/W
Description I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 12.12 Table 12.14 Table 12.15 Table 12.16 Table 12.18
3 to 0
IOA[3:0]
0000
R/W
I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 12.20 Table 12.22 Table 12.23 Table 12.24 Table 12.26
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* TIORL_0, TIORL_3, TIORL_4
Bit: 7 6 5 4 3 2 1 0 IOD[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W IOC[3:0] 0 R/W 0 R/W 0 R/W
Bit 7 to 4
Bit Name IOD[3:0]
Initial Value 0000
R/W R/W
Description I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 12.13 TIORL_3: Table 12.17 TIORL_4: Table 12.19
3 to 0
IOC[3:0]
0000
R/W
I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 12.21 TIORL_3: Table 12.25 TIORL_4: Table 12.27
* TIORU_5, TIORV_5, TIORW_5
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 0 R/W 0 R/W 4 3 2 IOC[4:0] 0 R/W 0 R/W 0 R/W 1 0
Bit 7 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4 to 0
IOC[4:0]
00000
R/W
I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 12.28.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.12 TIORH_0 (Channel 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_0 Function Output compare register TIOC0B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.13 TIORL_0 (Channel 0)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRD_0 Function Output compare register*2 TIOC0D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.14 TIOR_1 (Channel 1)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_1 Function Output compare register TIOC1B Pin Function Output retained Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.15 TIOR_2 (Channel 2)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_2 Function Output compare register TIOC2B Pin Function Output retained Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.16 TIORH_3 (Channel 3)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_3 Function Output compare register TIOC3B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.17 TIORL_3 (Channel 3)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRD_3 Function Output compare 2 register* TIOC3D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.18 TIORH_4 (Channel 4)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRB_4 Function Output compare register TIOC4B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.19 TIORL_4 (Channel 4)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRD_4 Function Output compare 2 register* TIOC4D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.20 TIORH_0 (Channel 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_0 Function Output compare register TIOC0A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.21 TIORL_0 (Channel 0)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRC_0 Function Output compare 2 register* TIOC0C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge 2 register* Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.22 TIOR_1 (Channel 1)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_1 Function Output compare register TIOC1A Pin Function Output retained Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.23 TIOR_2 (Channel 2)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_2 Function Output compare register TIOC2A Pin Function Output retained Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.24 TIORH_3 (Channel 3)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_3 Function Output compare register TIOC3A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.25 TIORL_3 (Channel 3)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRC_3 Function Output compare 2 register* TIOC3C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.26 TIORH_4 (Channel 4)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRA_4 Function Output compare register TIOC4A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.27 TIORL_4 (Channel 4)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X TGRC_4 Function Output compare 2 register* TIOC4C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges
[Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5)
Description TGRU_5, TGRV_5, and TGRW_5 TIC5U, TIC5V, and TIC5W Pin Function Function Compare Compare match match register Setting prohibited Setting prohibited Setting prohibited Setting prohibited Input capture register Setting prohibited Input capture at rising edge Input capture at falling edge Input capture at both edges Setting prohibited Setting prohibited Measurement of low pulse width of external input signal Capture at trough 1 0 Measurement of low pulse width of external input signal Capture at crest 1 Measurement of low pulse width of external input signal Capture at crest and trough 1 0 0 1 Setting prohibited Measurement of high pulse width of external input signal Capture at trough 1 0 Measurement of high pulse width of external input signal Capture at crest 1 Measurement of high pulse width of external input signal Capture at crest and trough
Bit 4 IOC4 0
Bit 3 IOC3 0
Bit 2 IOC2 0
Bit 1 IOC1 0
Bit 0 IOC0 0 1
1 1 1 1 0 X 0 X X 0
X X X 0 1
1
0 1
1 1 0
X 0
X 0 1
[Legend] X: Don't care
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.4
Timer Compare Match Clear Register (TCNTCMPCLR)
TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0
CMP CMP CMP CLR5U CLR5V CLR5W
0 R/W
0 R/W
0 R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
CMPCLR5U 0
R/W
TCNT Compare Clear 5U Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture
1
CMPCLR5V 0
R/W
TCNT Compare Clear 5V Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 0
Bit Name
Initial Value
R/W R/W
Description TCNT Compare Clear 5W Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture
CMPCLR5W 0
12.3.5
Timer Interrupt Enable Register (TIER)
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5. * TIER_0, TIER_1, TIER_2, TIER_3, TIER_4
Bit: 7 6 5 4 3 2 1 0
TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name TTGE
Initial Value 0
R/W R/W
Description A/D Converter Start Request Enable Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 6
Bit Name TTGE2
Initial Value 0
R/W R/W
Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled
5
TCIEU
0
R/W
Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 2
Bit Name TGIEC
Initial Value 0
R/W R/W
Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* TIER2_0
Bit: 7
TTGE2
6 -- 0 R
5 -- 0 R
4 -- 0 R
3 -- 0 R
2 -- 0 R
1
0
TGIEF TGIEE
Initial value: 0 R/W: R/W
0 R/W
0 R/W
Bit 7
Bit Name TTGE2
Initial Value 0
R/W R/W
Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled
6 to 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
TGIEF
0
R/W
TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled
0
TGIEE
0
R/W
TGR Interrupt Enable E Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* TIER_5
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 TGIE TGIE TGIE 5U 5V 5W 0 0 0 R/W R/W R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
TGIE5U
0
R/W
TGR Interrupt Enable 5U Enables or disables interrupt requests (TGIU_5) by compare match between TCNTU_5 and TGRU_5. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled
1
TGIE5V
0
R/W
TGR Interrupt Enable 5V Enables or disables interrupt requests (TGIV_5) by compare match between TCNTV_5 and TGRV_5. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled
0
TGIE5W
0
R/W
TGR Interrupt Enable 5W Enables or disables interrupt requests (TGIW_5) by compare match between TCNTW_5 and TGRW_5. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.6
Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5. * TSR_0, TSR_1, TSR_2, TSR_3, TSR_4
Bit: 7 TCFD Initial value: R/W: 1
R
6 -- 1
R
5
4
3
2
1
0
TCFU TCFV TGFD TGFC TGFB TGFA 0 0 0 0 0 0
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1R/(W)* 1
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit 7
Bit Name TCFD
Initial Value 1
R/W R
Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up
6
--
1
R
Reserved This bit is always read as 1. The write value should always be 1.
5
TCFU
0
R/(W)*1 Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) When 0 is written to TCFU after reading TCFU = 1*2
[Clearing condition] *
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 4
Bit Name TCFV
Initial Value 0
R/W
1
Description
R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] * When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. When 0 is written to TCFV after reading 2 TCFV = 1*
[Clearing condition] * 3 TGFD 0
R/(W)*1 Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When 0 is written to TGFD after reading 2 TGFD = 1*
[Clearing condition] *
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 2
Bit Name TGFC
Initial Value 0
R/W
1
Description
R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When 0 is written to TGFC after reading 2 TGFC = 1*
[Clearing condition] * 1 TGFB 0
R/(W)*1 Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When 0 is written to TGFB after reading 2 TGFB = 1*
[Clearing condition] *
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 0
Bit Name TGFA
Initial Value 0
R/W
1
Description
R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When DMAC is activated by TGIA interrupt When 0 is written to TGFA after reading TGFA = 1*2
[Clearing conditions] * *
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is held.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* TSR2_0
Bit: 7 -- Initial value: R/W: 1
R
6 -- 1
R
5 -- 0
R
4 -- 0
R
3 -- 0
R
2 -- 0
R
1
0
TGFF TGFE 0 0
R/(W)*1R/(W)* 1
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit 7, 6
Bit Name --
Initial Value All 1
R/W R
Description Reserved These bits are always read as 1. The write value should always be 1.
5 to 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
TGFF
0
R/(W)*1 Compare Match Flag F Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Setting condition] * When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register When 0 is written to TGFF after reading 2 TGFF = 1*
[Clearing condition] * 0 TGFE 0
R/(W)*1 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Setting condition] * When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register When 0 is written to TGFE after reading 2 TGFE = 1*
[Clearing condition] *
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is held.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* TSR_5
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 CMF CMF CMF U5 V5 W5 0 0 0 R/(W)*1R/(W)*1R/(W)*1
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
CMFU5
0
R/(W)*1 Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. [Setting conditions] * * When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register When TCNTU_5 value is transferred to TGRU_5 by input capture signal while TGRU_5 is functioning as input capture register When TCNTU_5 value is transferred to TGRU_5 while TGRU_5 is functioning as a register for measuring the pulse width of the external input 2 signal* . When 0 is written to CMFU5 after reading CMFU5 = 1
*
[Clearing condition] *
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 1
Bit Name CMFV5
Initial Value 0
R/W
1
Description
R/(W)* Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Setting conditions] * * When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register When TCNTV_5 value is transferred to TGRV_5 by input capture signal while TGRV_5 is functioning as input capture register When TCNTV_5 value is transferred to TGRV_5 while TGRV_5 is functioning as a register for measuring the pulse width of the external input 2 signal* . When 0 is written to CMFV5 after reading CMFV5 = 1
*
[Clearing condition] * 0 CMFW5 0
1
R/(W)* Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Setting conditions] * * When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register When TCNTW_5 value is transferred to TGRW_5 by input capture signal while TGRW_5 is functioning as input capture register When TCNTW_5 value is transferred to TGRW_5 while TGRW_5 is functioning as a register for measuring the pulse width of the external input 2 signal* . When 0 is written to CMFW5 after reading CMFW5 = 1
*
[Clearing condition] *
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Timing to transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5 (TIORU_5/V_5/W_5).
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.7
Timer Buffer Operation Transfer Mode Register (TBTM)
TBTM is an 8-bit readable/writable register that specifies the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0
TTSE TTSB TTSA 0 R/W 0 R/W 0 R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
TTSE
0
R/W
Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. For channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. Do not set this bit to 1 when channel 0 is to be used in a mode other than PWM mode. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared
1
TTSB
0
R/W
Timing Select B Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. Do not set this bit to 1 when the channel is to be used in a mode other than PWM mode. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 0
Bit Name TTSA
Initial Value 0
R/W R/W
Description Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. Do not set this bit to 1 when the channel is to be used in a mode other than PWM mode. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel
12.3.8
Timer Input Capture Control Register (TICCR)
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 2 1 0
I2BE I2AE I1BE I1AE 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3
I2BE
0
R/W
Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 2
Bit Name I2AE
Initial Value 0
R/W R/W
Description Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions
1
I1BE
0
R/W
Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions
0
I1AE
0
R/W
Input Capture Enable Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions
12.3.9
Timer A/D Converter Start Request Control Register (TADCR)
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4.
Bit: 15 14 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 6 5 4 3 2 1 0
BF[1:0] Initial value: 0 R/W: R/W Note: * 0 R/W
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
0 R/W
0* R/W
0 R/W
0* R/W
0* R/W
0* R/W
0* R/W
0* R/W
Do not set to 1 when complementary PWM mode is not selected.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 15, 14
Bit Name BF[1:0]
Initial Value 00
R/W R/W
Description TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 12.29.
13 to 8 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7
UT4AE
0
R/W
Up-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation
6
DT4AE
0*
R/W
Down-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation
5
UT4BE
0
R/W
Up-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 4
Bit Name DT4BE
Initial Value 0*
R/W R/W
Description Down-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation
3
ITA3AE
0*
R/W
TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping
2
ITA4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping
1
ITB3AE
0*
R/W
TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping
0
ITB4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping
Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.29 Setting of Transfer Timing by BF1 and BF0 Bits
Bit 7 BF1 0 0 1 1 Bit 6 BF0 0 1 0 1 Description Does not transfer data from the cycle set buffer register to the cycle set register. Transfers data from the cycle set buffer register to the cycle set 1 register at the crest of the TCNT_4 count.* Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.*2 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.*2
Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected.
12.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
12.3.12 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.13 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.14 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. * TSTR
Bit: 7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0 CST4 CST3 Initial value: 0 R/W: R/W 0 R/W CST2 CST1 CST0 0 R/W 0 R/W 0 R/W
Bit 7 6
Bit Name CST4 CST3
Initial Value 0 0
R/W R/W R/W
Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation
5 to 3
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 2 1 0
Bit Name CST2 CST1 CST0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation
* TSTR_5
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0
CSTU5 CSTV5 CSTW5
0 R/W
0 R/W
0 R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
CSTU5
0
R/W
Counter Start U5 Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation
1
CSTV5
0
R/W
Counter Start V5 Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation
0
CSTW5
0
R/W
Counter Start W5 Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.15 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit: 7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 1 0
SYNC4 SYNC3
SYNC2 SYNC1 SYNC0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6
Bit Name SYNC4 SYNC3
Initial Value 0 0
R/W R/W R/W
Description Timer Synchronous operation 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
5 to 3
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 2 1 0
Bit Name SYNC2 SYNC1 SYNC0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Timer Synchronous operation 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.16 Timer Counter Synchronous Start Register (TCSYSTR) TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 counters.
Bit: 7 6 5 4 3 2 -- 0 R 1 -- 0 R 0 -- 0 R
SCH0 SCH1 SCH2 SCH3 SCH4 Initial value: 0 0 0 0 0 R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)* Note: *
Only 1 can be written to set the register.
Bit 7
Bit Name SCH0
Initial Value 0
R/W
Description
R/(W)* Synchronous Start Controls synchronous start of TCNT_0 in the MTU2. 0: Does not specify synchronous start for TCNT_0 in the MTU2 1: Specifies synchronous start for TCNT_0 in the MTU2 [Clearing condition] * When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 = 1
6
SCH1
0
R/(W)* Synchronous Start Controls synchronous start of TCNT_1 in the MTU2. 0: Does not specify synchronous start for TCNT_1 in the MTU2 1: Specifies synchronous start for TCNT_1 in the MTU2 [Clearing condition] * When 1 is set to the CST1 bit of TSTR in MTU2 while SCH1 = 1
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 5
Bit Name SCH2
Initial Value 0
R/W
Description
R/(W)* Synchronous Start Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition] * When 1 is set to the CST2 bit of TSTR in MTU2 while SCH2 = 1
4
SCH3
0
R/(W)* Synchronous Start Controls synchronous start of TCNT_3 in the MTU2. 0: Does not specify synchronous start for TCNT_3 in the MTU2 1: Specifies synchronous start for TCNT_3 in the MTU2 [Clearing condition] * When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 = 1
3
SCH4
0
R/(W)* Synchronous Start Controls synchronous start of TCNT_4 in the MTU2. 0: Does not specify synchronous start for TCNT_4 in the MTU2 1: Specifies synchronous start for TCNT_4 in the MTU2 [Clearing condition] * When 1 is set to the CST4 bit of TSTR in MTU2 while SCH4 = 1
2 to 0
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Note:
*
Only 1 can be written to set the register.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.17 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 RWE 1 R/W
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
RWE
1
R/W
Read/Write Enable Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition] * When 0 is written to the RWE bit after reading RWE = 1
* Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT_4.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.18 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of channel 3 and channel 4 prior to setting TIOR of channel 3 and channel 4.
Bit: 7 -- Initial value: R/W: 1 R 6 -- 1 R 5 4 3 2 1 0
OE4D OE4C OE3D OE4B OE4A OE3B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7, 6
Bit Name --
Initial Value All 1
R/W R
Description Reserved These bits are always read as 1. The write value should always be 1.
5
OE4D
0
R/W
Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled
4
OE4C
0
R/W
Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled
3
OE3D
0
R/W
Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled
2
OE4B
0
R/W
Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled
1
OE4A
0
R/W
Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 0
Bit Name OE3B
Initial Value 0
R/W R/W
Description Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled
Note:
*
The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 12.3.19, Timer Output Control Register 1 (TOCR1), and section 12.3.20, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or resetsynchronized PWM mode. If these bits are set to 0, low level is output.
12.3.19 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output.
Bit: 7 -- Initial value: R/W: 0 R 6 PSYE 0 R/W 5 -- 0 R 4 -- 0 R 3 2 1 0
TOCL TOCS OLSN OLSP 0 0 R/(W)*1 R/W 0 R/W 0 R/W
Note: 1. This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit.
Bit 7
Bit Name --
Initial value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6
PSYE
0
R/W
PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled
5, 4
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 3
Bit Name TOCL
Initial Value 0
R/W
1
Description
2 R/(W)* TOC Register Write Protection*
This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled 2 TOCS 0 R/W TOC Select This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected 1 OLSN 0 R/W Output Level Select N*3 This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 12.30. 0 OLSP 0 R/W Output Level Select P*3 This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 12.31. Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be written to the bit. 2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 3. Clearing the TOCS bit to 0 makes this bit setting valid.
Table 12.30 Output Level Select Function
Bit 1 Function Compare Match Output OLSN 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.31 Output Level Select Function
Bit 0 Function Compare Match Output OLSP 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level
Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1 and OLSP = 1.
TCNT_3 and TCNT_4 values TGRA_3
TCNT_3 TCNT_4 TGRA_4
TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level
Time
Positive phase output
Reverse phase output
Figure 12.2 Complementary PWM Mode Output Level Example
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.20 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode.
Bit: 7 6 5 4 3 2 1 0
BF[1:0] Initial value: 0 R/W: R/W 0 R/W
OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7, 6
Bit Name BF[1:0]
Initial value 00
R/W R/W
Description TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 12.32.
5
OLS3N
0
R/W
Output Level Select 3N* This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode. See table 12.33.
4
OLS3P
0
R/W
Output Level Select 3P* This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode. See table 12.34.
3
OLS2N
0
R/W
Output Level Select 2N* This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode. See table 12.35.
2
OLS2P
0
R/W
Output Level Select 2P* This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode. See table 12.36.
1
OLS1N
0
R/W
Output Level Select 1N* This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode. See table 12.37.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 0
Bit Name OLS1P
Initial value 0
R/W R/W
Description Output Level Select 1P* This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode. See table 12.38.
Note:
*
Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid.
Table 12.32 Setting of Bits BF1 and BF0
Bit 7 BF1 0 0 Bit 6 BF0 0 1 Complementary PWM Mode Description Reset-Synchronized PWM Mode
Does not transfer data from the Does not transfer data from the buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2. Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared Setting prohibited
1
0
1
1
Setting prohibited
Table 12.33 TIOC4D Output Level Select Function
Bit 5 Function Compare Match Output OLS3N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.34 TIOC4B Output Level Select Function
Bit 4 Function Compare Match Output OLS3P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level
Table 12.35 TIOC4C Output Level Select Function
Bit 3 Function Compare Match Output OLS2N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.
Table 12.36 TIOC4A Output Level Select Function
Bit 2 Function Compare Match Output OLS2P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level
Table 12.37 TIOC3D Output Level Select Function
Bit 1 Function Compare Match Output OLS1N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.38 TIOC3B Output Level Select Function
Bit 0 Function Compare Match Output OLS1P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level
12.3.21 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0
OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7, 6
Bit Name --
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5 4 3 2 1 0
OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Specifies the buffer value to be transferred to the OLS3N bit in TOCR2. Specifies the buffer value to be transferred to the OLS3P bit in TOCR2. Specifies the buffer value to be transferred to the OLS2N bit in TOCR2. Specifies the buffer value to be transferred to the OLS2P bit in TOCR2. Specifies the buffer value to be transferred to the OLS1N bit in TOCR2. Specifies the buffer value to be transferred to the OLS1P bit in TOCR2.
Figure 12.3 shows an example of the PWM output level setting procedure in buffer operation.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Set bit TOCS
[1]
[1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
Set TOCR2
[2]
Set TOLBR
[3]
Figure 12.3 PWM Output Level Setting Procedure in Buffer Operation 12.3.22 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode.
Bit: 7 -- Initial value: R/W: 1 R 6 BDC 0 R/W 5 N 0 R/W 4 P 0 R/W 3 FB 0 R/W 2 WF 0 R/W 1 VF 0 R/W 0 UF 0 R/W
Bit 7
Bit Name --
Initial value 1
R/W R
Description Reserved This bit is always read as 1. The write value should always be 1.
6
BDC
0
R/W
Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 5
Bit Name N
Initial value 0
R/W R/W
Description Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output
4
P
0
R/W
Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output
3
FB
0
R/W
External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings).
2 1 0
WF VF UF
0 0 0
R/W R/W R/W
Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 12.39.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.39 Output level Select Function
Function Bit 2 WF 0 Bit 1 VF 0 Bit 0 UF 0 1 1 0 1 1 0 0 1 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B TIOC3D TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF
W Phase U Phase OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF
12.3.23 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.24 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
12.3.25 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.26 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
12.3.27 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR.
Bit: 7
T3AEN
6
5 3ACOR[2:0]
4
3
T4VEN
2
1 4VCOR[2:0]
0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name T3AEN
Initial value 0
R/W R/W
Description T3AEN Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled
6 to 4
3ACOR[2:0] 000
R/W
These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 12.40. T4VEN Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled
3
T4VEN
0
R/W
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 2 to 0
Bit Name
Initial value
R/W R/W
Description These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 12.41.
4VCOR[2:0] 000
Note:
*
When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TITCNT).
Table 12.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0
Bit 6 3ACOR2 0 0 0 0 1 1 1 1 Bit 5 3ACOR1 0 0 1 1 0 0 1 1 Bit 4 3ACOR0 0 1 0 1 0 1 0 1 Description Does not skip TGIA_3 interrupts. Sets the TGIA_3 interrupt skipping count to 1. Sets the TGIA_3 interrupt skipping count to 2. Sets the TGIA_3 interrupt skipping count to 3. Sets the TGIA_3 interrupt skipping count to 4. Sets the TGIA_3 interrupt skipping count to 5. Sets the TGIA_3 interrupt skipping count to 6. Sets the TGIA_3 interrupt skipping count to 7.
Table 12.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0
Bit 2 4VCOR2 0 0 0 0 1 1 1 1 Bit 1 4VCOR1 0 0 1 1 0 0 1 1 Bit 0 4VCOR0 0 1 0 1 0 1 0 1 Description Does not skip TCIV_4 interrupts. Sets the TCIV_4 interrupt skipping count to 1. Sets the TCIV_4 interrupt skipping count to 2. Sets the TCIV_4 interrupt skipping count to 3. Sets the TCIV_4 interrupt skipping count to 4. Sets the TCIV_4 interrupt skipping count to 5. Sets the TCIV_4 interrupt skipping count to 6. Sets the TCIV_4 interrupt skipping count to 7.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.28 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains the value even after TCNT_3 or TCNT_4 stops counting.
Bit: 7 -- Initial value: R/W: 0 R 0 R 6 5 3ACNT[2:0] 0 R 0 R 4 3 -- 0 R 0 R 2 1 4VCNT[2:0] 0 R 0 R 0
Bit 7 6 to 4
Bit Name -- 3ACNT[2:0]
Initial Value 0 000
R/W R R
Description Reserved This bit is always read as 0. TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions] * * * When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR When the T3AEN bit in TITCR is cleared to 0 When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0
3 2 to 0
-- 4VCNT[2:0]
0 000
R R
Reserved This bit is always read as 0. TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions] * * * When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR When the T4VEN bit in TITCR is cleared to 0 When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0
Note: Clear the T3AEN and T4VEN bits in TITCR to 0, to clear the value of TITCNT.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.29 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 0
BTE[1:0] 0 R/W 0 R/W
Bit 7 to 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1, 0
BTE[1:0]
00
R/W
These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 12.42.
Note:
*
Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.42 Setting of Bits BTE1 and BTE0
Bit 1 BTE1 0 0 1 1 Bit 0 BTE0 0 1 0 1 Description Enables transfer from the buffer registers to the temporary registers*1 and does not link the transfer with interrupt skipping operation. Disables transfer from the buffer registers to the temporary registers. Links transfer from the buffer registers to the temporary registers with interrupt skipping operation.*2 Setting prohibited
Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 12.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.30 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 TDER 1 R/(W)
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
TDER
1
R/(W)
Dead Time Enable Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition] * When 0 is written to TDER after reading TDER = 1
Note:
*
TDDR must be set to 1 or a larger value.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.31 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops.
Bit: 7 CCE Initial value: 0* R/W: R/(W) Note: * 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 WRE 0 R/(W)
Do not set to 1 when complementary PWM mode is not selected.
Bit 7
Bit Name CCE
Initial Value 0*
R/W R/(W)
Description Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition] * When 1 is written to CCE after reading CCE = 0
6 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit 0
Bit Name WRE
Initial Value 0
R/W R/(W)
Description Waveform Retain Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The output waveform is retained only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 12.40. 0: Outputs the initial value specified in TOCR 1: Retains the waveform output immediately before synchronous clearing [Setting condition] * When 1 is written to WRE after reading WRE = 0
Note:
*
Do not set to 1 when complementary PWM mode is not selected.
12.3.32 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4
12.4.1
Operation
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). (1) Counter Operation
When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure
Figure 12.4 shows an example of the count operation setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation [5] [5] Set the CST bit in TSTR to 1 to start the counter operation.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source Select output compare register Set period
[2]
[3]
[4]
Start count operation
[5]
Figure 12.4 Example of Counter Operation Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Free-Running Count Operation and Periodic Count Operation:
Immediately after a reset, the MTU2's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU2 requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 12.5 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 12.5 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the MTU2 requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 12.6 illustrates periodic counter operation.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT value TGR
Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software or DMAC activation TGF
Figure 12.6 Periodic Counter Operation (2) Waveform Output by Compare Match
The MTU2 can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match
Figure 12.7 shows an example of the setting procedure for waveform output by compare match
Output selection [1]
Select waveform output mode
[1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Set output timing
[2]
Start count operation
[3]

Figure 12.7 Example of Setting Procedure for Waveform Output by Compare Match
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Examples of Waveform Output Operation:
Figure 12.8 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB No change No change Time No change No change 1 output 0 output
Figure 12.8 Example of 0 Output/1 Output Operation Figure 12.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle output Toggle output
Figure 12.9 Example of Toggle Output Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Input Capture Function:
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. (a) Example of Input Capture Operation Setting Procedure
Figure 12.10 shows an example of the input capture operation setting procedure.
Input selection [1] [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation.
Select input capture input
Start count
[2]

Figure 12.10 Example of Input Capture Operation Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Example of Input Capture Operation:
Figure 12.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 12.11 Example of Input Capture Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.2
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. (1) Example of Synchronous Operation Setting Procedure:
Figure 12.12 shows an example of the synchronous operation setting procedure.
Synchronous operation selection
Set synchronous operation
[1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No
Start count
[5]
Start count
[5]

[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 12.12 Example of Synchronous Operation Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Example of Synchronous Operation
Figure 12.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 12.4.5, PWM Modes.
TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOC0A TIOC1A TIOC2A Time Synchronous clearing by TGRB_0 compare match
Figure 12.13 Example of Synchronous Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.3
Buffer Operation
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 12.43 shows the register combinations used in buffer operation. Table 12.43 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGRA_0 TGRB_0 TGRE_0 3 TGRA_3 TGRB_3 4 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRF_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 12.14.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 12.14 Compare Match Buffer Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 12.15.
Input capture signal Buffer register Timer general register
TCNT
Figure 12.15 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure
Figure 12.16 shows an example of the buffer operation setting procedure.
Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation.
Select TGR function
[1]
Set buffer operation
[2]
Start count
[3]

Figure 12.16 Example of Buffer Operation Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2) (a)
Examples of Buffer Operation When TGR is an output compare register
Figure 12.17 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. In this example, the TTSA bit in TBTM is cleared to 0. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 12.4.5, PWM Modes.
TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time
H'0450
H'0520
TIOCA
Figure 12.17 Example of Buffer Operation (1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
When TGR is an input capture register
Figure 12.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07 H'0532
H'09FB H'0F07
TGRC
Figure 12.18 Example of Buffer Operation (2)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation:
The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer timing is one of the following cases. * When TCNT overflows (H'FFFF to H'0000) * When H'0000 is written to TCNT during counting * When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note: TBTM must be modified only while TCNT stops. Figure 12.19 shows an operation example in which PWM mode 1 is designated for channel 0 and buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. The TTSA bit in TBTM_0 is set to 1.
TCNT_0 value
TGRB_0 H'0450 TGRA_0 H'0000 H'0200 Time H'0520
TGRC_0
H'0200
H'0450 Transfer
H'0520
TGRA_0
H'0200
H'0450
H'0520
TIOCA
Figure 12.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 12.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 12.44 Cascaded Combinations
Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 12.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection. Table 12.45 show the TICCR setting and input capture input pins. Table 12.45 TICCR Setting and Input Capture Input Pins
Target Input Capture Input capture from TCNT_1 to TGRA_1 Input capture from TCNT_1 to TGRB_1 Input capture from TCNT_2 to TGRA_2 Input capture from TCNT_2 to TGRB_2 TICCR Setting I2AE bit = 0 (initial value) I2AE bit = 1 I2BE bit = 0 (initial value) I2BE bit = 1 I1AE bit = 0 (initial value) I1AE bit = 1 I1BE bit = 0 (initial value) I1BE bit = 1 Input Capture Input Pins TIOC1A TIOC1A, TIOC2A TIOC1B TIOC1B, TIOC2B TIOC2A TIOC2A, TIOC1A TIOC2B TIOC2B, TIOC1B
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Example of Cascaded Operation Setting Procedure
Figure 12.20 shows an example of the setting procedure for cascaded operation.
Cascaded operation [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Set cascading
[1]
Start count
[2]

Figure 12.20 Cascaded Operation Setting Procedure (2) Cascaded Operation Example (a)
Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF
TCNT_1
0000
0001
0000
Figure 12.21 Cascaded Operation Example (a)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Cascaded Operation Example (b)
Figure 12.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.
TCNT_2 value
H'FFFF H'C256
H'6128 H'0000 Time
TCNT_1
H'0512
H'0513
H'0514
TIOC1A TIOC2A TGRA_1 H'0512 H'0513
TGRA_2
H'C256 As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.
Figure 12.22 Cascaded Operation Example (b)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Cascaded Operation Example (c)
Figure 12.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions.
TCNT_2 value H'FFFF H'C256 H'9192 H'6128 H'2064 H'0000
Time
TCNT_1
H'0512
H'0513
H'0514
TIOC1A TIOC2A TGRA_1 H'0512 H'0513 H'0514
TGRA_2
H'6128
H'2064
H'C256
H'9192
Figure 12.23 Cascaded Operation Example (c)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(5)
Cascaded Operation Example (d)
Figure 12.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1.
TCNT_0 value TGRA_0
Compare match between TCNT_0 and TGRA_0
H'0000 TCNT_2 value H'FFFF H'D000
Time
H'0000
Time
TCNT_1
H'0512
H'0513
TIOC1A TIOC2A TGRA_1 H'0513
TGRA_2
H'D000
Figure 12.24 Cascaded Operation Example (d)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 12.46.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.46 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A TIOC1A TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Example of PWM Mode Setting Procedure:
Figure 12.25 shows an example of the PWM mode setting procedure.
PWM mode [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] [6] Set the CST bit in TSTR to 1 to start the count operation.
Select counter clock
Select counter clearing source
[2]
Select waveform output level
[3]
Set TGR
[4]
Set PWM mode
[5]
Start count

Figure 12.25 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation
Figure 12.26 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT value TGRA
Counter cleared by TGRA compare match
TGRB H'0000 TIOCA Time
Figure 12.26 Example of PWM Mode Operation (1) Figure 12.27 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels.
Counter cleared by TGRB_1 compare match
TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000
Time TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
Figure 12.27 Example of PWM Mode Operation (2)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 12.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT value TGRB rewritten TGRA
TGRB H'0000
TGRB rewritten
TGRB rewritten Time
TIOCA
0% duty Output does not change when cycle register and duty register compare matches occur simultaneously
TCNT value TGRB rewritten TGRA
TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time
TIOCA
TCNT value TGRB rewritten TGRA
Output does not change when cycle register and duty register compare matches occur simultaneously
TGRB rewritten
TGRB H'0000 100% duty 0% duty
TGRB rewritten Time
TIOCA
Figure 12.28 Example of PWM Mode Operation (3)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 12.47 shows the correspondence between external clock pins and channels. Table 12.47 Phase Counting Mode Clock Input Pins
External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Example of Phase Counting Mode Setting Procedure
Figure 12.29 shows an example of the phase counting mode setting procedure.
Phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [2]
Select phase counting mode
[1]
Start count

Figure 12.29 Example of Phase Counting Mode Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1
Figure 12.30 shows an example of phase counting mode 1 operation, and table 12.48 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count
Time
Figure 12.30 Example of Phase Counting Mode 1 Operation Table 12.48 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Phase counting mode 2
Figure 12.31 shows an example of phase counting mode 2 operation, and table 12.49 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count
Time
Figure 12.31 Example of Phase Counting Mode 2 Operation Table 12.49 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(c)
Phase counting mode 3
Figure 12.32 shows an example of phase counting mode 3 operation, and table 12.50 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value
Up-count
Down-count
Time
Figure 12.32 Example of Phase Counting Mode 3 Operation Table 12.50 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(d)
Phase counting mode 4
Figure 12.33 shows an example of phase counting mode 4 operation, and table 12.51 summarizes the TCNT up/down-count conditions.
TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count
Up-count
Time
Figure 12.33 Example of Phase Counting Mode 4 Operation Table 12.51 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Phase Counting Mode Application Example:
Figure 12.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.
Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture)
TCNT_0 TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 + + -
Figure 12.34 Phase Counting Mode Application Example
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.7
Reset-Synchronized PWM Mode
In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT_3 functions as an upcounter. Table 12.52 shows the PWM output pins used. Table 12.53 shows the settings of the registers. Table 12.52 Output Pins for Reset-Synchronized PWM Mode
Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3)
Table 12.53 Register Settings for Reset-Synchronized PWM Mode
Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Procedure for Selecting the Reset-Synchronized PWM Mode
Figure 12.35 shows an example of procedure for selecting the reset synchronized PWM mode.
[1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. [1] [2] Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. [5] [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR2, see figure 12.3. [7] Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. Reset-synchronized PWM mode Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty.
Reset-synchronized PWM mode Stop counting
Select counter clock and counter clear source
[2]
Brushless DC motor control setting
[3] [4]
Set TCNT
Set TGR
PWM cycle output enabling, PWM output level setting
[6]
Set reset-synchronized PWM mode
[7]
Enable waveform output
[8]
PFC setting
[9]
Start count operation
[10]
Figure 12.35 Procedure for Selecting Reset-Synchronized PWM Mode
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Reset-Synchronized PWM Mode Operation
Figure 12.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 comparematch occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears.
TCNT_3 and TCNT_4 values
TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B
TIOC3D TIOC4A
TIOC4C TIOC4B
TIOC4D
Figure 12.36 Reset-Synchronized PWM Mode Operation Example (When TOCR's OLSN = 1 and OLSP = 1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.8
Complementary PWM Mode
In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval is also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 12.54 shows the PWM output pins used. Table 12.55 shows the settings of the registers used. Table 12.54 Output Pins for Complementary PWM Mode
Channel 3 Output Pin TIOC3A TIOC3B TIOC3C TIOC3D Description Toggle output synchronized with PWM period (or I/O port) PWM output pin 1 I/O port* PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) PWM output pin 2 PWM output pin 3 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available)
4
TIOC4A TIOC4B TIOC4C
TIOC4D
Note:
*
Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.55 Register Settings for Complementary PWM Mode
Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by TRWER setting* Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Always readable/writable Maskable by TRWER setting* Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Always readable/writable Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable
Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register).
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TGRA_3 comparematch interrupt
TCNT_4 underflow interrupt
TGRC_3
TCBR
TDDR
TGRA_3
TCDR
Comparator
Output controller
Match signal
PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6
TCNT_3
TCNTS
TCNT_4
Comparator
Match signal
TGRB_3
TGRA_4
TGRD_3
TGRC_4
TGRD_4
: Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read)
Figure 12.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
TGRB_4
Temp 1
Temp 2
Temp 3
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Example of Complementary PWM Mode Setting Procedure
An example of the complementary PWM mode setting procedure is shown in figure 12.38.
Complementary PWM mode
Stop count operation
[1]
[1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated.
Counter clock, counter clear source selection
[2]
Brushless DC motor control setting
[3]
TCNT setting
[4]
Inter-channel synchronization setting [5]
TGR setting
[6]
Enable/disable dead time generation [7]
Dead time, carrier cycle setting
[8]
PWM cycle output enabling, PWM output level setting
[9]
Complementary PWM mode setting
Enable waveform output
[8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier [11] cycle + 1 in TGRA_3 and TGRC_3. [10] [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 12.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation.
PFC setting
[12]
Start count operation
[13]

Figure 12.38 Example of Complementary PWM Mode Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Outline of Complementary PWM Mode Operation
In complementary PWM mode, 6-phase PWM output is possible. Figure 12.39 illustrates counter operation in complementary PWM mode, and figure 12.40 shows an example of complementary PWM mode operation. (a) Counter Operation
In complementary PWM mode, three counters--TCNT_3, TCNT_4, and TCNTS--perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000
TCNT_3 TCNT_4 TCNTS
TCNTS
Time
Figure 12.39 Complementary PWM Mode Counter Operation (b) Register Operation
In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 12.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.40 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 12.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters--TCNT_3, TCNT_4, and TCNTS-- and two registers--compare register and temporary register--are compared, and PWM output controlled accordingly.
Transfer from temporary register to compare register Transfer from temporary register to compare register
Tb2 TGRA_3
Ta
Tb1
Ta
Tb2
Ta
TCNTS TCDR TCNT_3 TGRA_4 TCNT_4
TGRC_4
TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4
H'6400
H'0080
H'6400
H'0080
H'6400
H'0080
Output waveform
Output waveform (Output waveform is active-low)
Figure 12.40 Example of Complementary PWM Mode Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(c)
Initialization
In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 12.56 Registers and Counters Requiring Initialization
Register/Counter TGRC_3 Set Value 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Dead time Td (1 when dead time generation is disabled by TDER) 1/2 PWM carrier cycle Initial PWM duty value for each phase H'0000
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(d)
PWM Output Level Setting
In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. (e) Dead Time Setting
In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. (f) Dead Time Suppressing
Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 12.41 shows an example of operation without dead time.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Transfer from temporary register to compare register
Transfer from temporary register to compare register
Ta TGRA_3 =TCDR + 1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4
Tb1
Ta
Tb2
Ta
TDDR=1 H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4
Data1
Data2
Data1
Data2
Data1
Data2
Output waveform
Output waveform Output waveform is active-low.
Figure 12.41 Example of Operation without Dead Time
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(g)
PWM Cycle Setting
In complementary PWM mode, the PWM pulse cycle is set in two registers--TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers:
With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 12.42 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register Data Updating, for the method of updating the data in each buffer register.
Counter value TGRC_3 update TGRA_3 update
TCNT_3 TGRA_3 TCNT_4
Time
Figure 12.42 Example of PWM Cycle Updating
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(h)
Register Data Updating
In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation.
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Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register
: Compare register : Buffer register Transfer from temporary register to compare register
Transfer from temporary register to compare register
Counter value
TGRA_3
TGRC_4 TGRA_4
H'0000 Time
BR data2 data1 data2 data3
data1
data2
data3
data4 data4 data3
data5 data5 data4
data6 data6 data6
Temp_R
data1
Figure 12.43 Example of Data Update in Complementary PWM Mode
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(i)
Initial Output in Complementary PWM Mode
In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 12.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 12.45.
Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values
TCNT_3 TCNT_4 TGRA_4
TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level
Complementary PWM mode (TMDR setting)
TCNT_3 and TCNT_4 count start (TSTR setting)
Figure 12.44 Example of Initial Output in Complementary PWM Mode (1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values
TCNT_3 TCNT_4
TDDR TGRA_4 Time Initial output Positive phase output Negative phase output Complementary PWM mode (TMDR setting) TCNT_3 and TCNT_4 count start (TSTR setting) Active level
Figure 12.45 Example of Initial Output in Complementary PWM Mode (2)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(j)
10. Complementary PWM Mode PWM Output Generation Method
In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 12.46 to 12.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a b c d (or c d a' b'), as shown in figure 12.46. If compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 12.47, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 12.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period TGRA_3 c TCDR d
T2 period
T1 period
a
b a' b'
TDDR
H'0000 Positive phase Negative phase
Figure 12.46 Example of Complementary PWM Mode Waveform Output (1)
T1 period TGRA_3 c TCDR a b d T2 period T1 period
a
b
TDDR
H'0000
Positive phase Negative phase
Figure 12.47 Example of Complementary PWM Mode Waveform Output (2)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period TGRA_3
T2 period
T1 period
TCDR a b
TDDR c a' H'0000 b' d
Positive phase Negative phase
Figure 12.48 Example of Complementary PWM Mode Waveform Output (3)
T1 period TGRA_3 c d T2 period T1 period
TCDR a b a' TDDR b'
H'0000
Positive phase Negative phase
Figure 12.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period TGRA_3
T2 period
T1 period
TCDR a b
a TDDR
b
H'0000 Positive phase Negative phase
c
d
Figure 12.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2)
T1 period TGRA_3 c d T2 period T1 period
TCDR
a
b
TDDR
H'0000
Positive phase Negative phase
Figure 12.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
TDDR
H'0000 c b' Positive phase Negative phase d a'
Figure 12.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4)
T1 period TGRA_3 c ad b T2 period T1 period
TCDR
TDDR
H'0000
Positive phase
Negative phase
Figure 12.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(k)
11. Complementary PWM Mode 0% and 100% Duty Output
In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 12.49 to 12.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. (l) 12. Toggle Output Synchronized with PWM Cycle
In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 12.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
TGRA_3
TCNT_3 TCNT_4
H'0000 Toggle output TIOC3A pin
Figure 12.54 Example of Toggle Output Waveform Synchronized with PWM Output
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(m) Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 12.55 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal.
TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A
TCNTS
TCNT_1
Synchronous counter clearing by channel 1 input capture A
Figure 12.55 Counter Clearing Synchronized with Another Channel
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(n)
Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 12.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 12.56) immediately after the counters start operation, initial value output is not suppressed. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing.
Counter start Tb interval
Tb interval
Tb interval
TGRA_3 TCDR TCNT_3
TGRB_3
TCNT_4
TDDR H'0000 Positive phase
Negative phase Output waveform is active-low
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) (11)
Figure 12.56 Timing for Synchronous Counter Clearing
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
* Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 12.57.
Output waveform control at synchronous counter clearing [1] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Output waveform control at synchronous counter clearing
Stop count operation
Set TWCR and complementary PWM mode
[2]
Start count operation
[3]
Figure 12.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode * Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 12.58 to 12.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 12.58 to 12.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 12.56, respectively.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Synchronous clearing
Bit WRE = 1 TGRA_3 TCDR
TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low.
Figure 12.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 12.56; Bit WRE of TWCR in MTU2 is 1)
Synchronous clearing
Bit WRE = 1 TGRA_3 TCDR
TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low.
Figure 12.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 12.56; Bit WRE of TWCR in MTU2 is 1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Synchronous clearing
Bit WRE = 1 TGRA_3 TCDR
TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low.
Figure 12.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 12.56; Bit WRE of TWCR is 1)
Synchronous clearing
Bit WRE = 1 TGRA_3 TCDR
TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase
Initial value output is suppressed.
Negative phase Output waveform is active-low.
Figure 12.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 12.56; Bit WRE of TWCR is 1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(o)
Counter Clearing by TGRA_3 Compare Match
In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 12.62 illustrates an operation example. Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest). 2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to SYNC4 bits in the timer synchronous register (TSYR) to 1). 3. Do not set the PWM duty value to H'0000. 4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1.
Counter cleared by TGRA_3 compare match TGRA_3 TCDR
TGRB_3
TDDR H'0000 Output waveform Output waveform Output waveform is active-high.
Figure 12.62 Example of Counter Clearing Operation by TGRA_3 Compare Match
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(p)
Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output
In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 12.63 to 12.66 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits.
External input
TIOC0A pin TIOC0B pin TIOC0C pin
6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin
TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high
Figure 12.63 Example of Output Phase Switching by External Input (1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
External input
TIOC0A pin TIOC0B pin TIOC0C pin
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high
Figure 12.64 Example of Output Phase Switching by External Input (2)
TGCR
UF bit VF bit WF bit
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high
Figure 12.65 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TGCR
UF bit VF bit WF bit
6-phase output
TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin
TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high
Figure 12.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) (q) A/D Converter Start Request Setting
In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Interrupt Skipping in Complementary PWM Mode:
Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER). For the linkage with buffer registers, refer to description (c), Buffer Transfer Control Linked with Interrupt Skipping, below. A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in coordination with interrupt skipping by making settings in the timer A/D converter request control register (TADCR). For the linkage with the A/D converter start request delaying function, refer to section 12.4.9, A/D Converter Start Request Delaying Function. The setting of the timer interrupt skipping setting register (TITCR) must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of registers TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. (a) Example of Interrupt Skipping Operation Setting Procedure
Figure 12.67 shows an example of the interrupt skipping operation setting procedure. Figure 12.68 shows the periods during which interrupt skipping count can be changed.
Interrupt skipping
[1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register (TITCR) to 0 to clear the skipping counter. [1] [2] Specify the interrupt skipping count within the range from 0 to 7 times in bits 3ACOR2 to 3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and enable interrupt skipping through bits T3AEN and T4VEN.
Clear interrupt skipping counter
Set skipping count and enable interrupt skipping
[2]
Note: The setting of TITCR must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of registers TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter.
Figure 12.67 Example of Interrupt Skipping Operation Setting Procedure
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4
Period during which changing skipping count can be performed
Period during which changing skipping count can be performed
Period during which changing skipping count can be performed
Period during which changing skipping count can be performed
Figure 12.68 Periods during which Interrupt Skipping Count can be Changed (b) Example of Interrupt Skipping Operation
Figure 12.69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR).
Interrupt skipping period TGIA_3 interrupt flag set signal
Interrupt skipping period
Skipping counter
00
01
02
03
00
01
02
03
TGFA_3 flag
Figure 12.69 Example of Interrupt Skipping Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(c)
Buffer Transfer Control Linked with Interrupt Skipping
In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER). Figure 12.70 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the temporary register. Figure 12.71 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer register outside the buffer transfer-enabled period. Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register (TITCR). Figure 12.72 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period. Note: This function must always be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never performed.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4 data1
Bit BTE0 in TBTER
Bit BTE1 in TBTER Buffer register Data1 (1) Temporary register Data* (2) General register Data* Buffer transfer is suppressed Data2 Data2 (3) Data2
[Legend]
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. Note: * When buffer transfer at the crest is selected.
Figure 12.70 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4
Buffer transferenabled period
Buffer register
Data*
Data1
Data2
Temporary register
Data*
Data2
General register Note: * Buffer transfer at the crest is selected. The skipping count is set to three. T3AEN is set to 1.
Data*
Data2
Figure 12.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0)
Skipping counter 3ACNT
0
1
2
3
0
1
2
3
0
Skipping counter 4VCNT Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1)
0
1
2
3
0
1
2
3
Note: * The skipping count is set to three.
Figure 12.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Complementary PWM Mode Output Protection Function
Complementary PWM mode output has the following protection functions. (a) Register and counter miswrite prevention function
With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following: * TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.9
A/D Converter Start Request Delaying Function
A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR. (a) Example of Procedure for Specifying A/D Converter Start Request Delaying Function
Figure 12.73 shows an example of procedure for specifying the A/D converter start request delaying function.
A/D converter start request delaying function
Set A/D converter start request cycle
[1]
[1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register. * Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE. * Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN).
* Set the timing of transfer from cycle set buffer register * Set linkage with interrupt skipping * Enable A/D converter start request delaying function
[2]
A/D converter start request delaying function Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected.
Figure 12.73 Example of Procedure for Specifying A/D Converter Start Request Delaying Function
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Basic Operation Example of A/D Converter Start Request Delaying Function
Figure 12.74 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting.
Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register
TADCORA_4 TCNT_4 TADCOBRA_4
A/D converter start request (TRG4AN)
(Complementary PWM mode)
Figure 12.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation (c) Buffer Transfer
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D converter start request control register (TADCR_4). (d) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR). Figure 12.75 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D converter start requests are linked with interrupt skipping.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 12.76 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter start requests are linked with interrupt skipping. Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0).
TCNT_4 TADCORA_4
TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter
00 00
01 01
02 02
00 00
01 01
TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * When the interrupt skipping count is set to two. (UT4AE/DT4AE = 1)
Figure 12.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_4 TADCORA_4
TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter
00 00
01 01
02 02
00 00
01 01
TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * When the interrupt skipping count is set to two. UT4AE = 1 DT4AE = 0
Figure 12.76 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.10 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in channel 5. (1) Example of External Pulse Width Measurement Setting Procedure
External pulse width measurement [1] [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Start count operation [3]
Select counter clock
Select pulse width measuring conditions
[2]
Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR.
Figure 12.77 Example of External Pulse Width Measurement Setting Procedure (2) Example of External Pulse Width Measurement
P
TIC5U
TCNT5_U
0000
0001 0002 0003 0004
0005
0006 0007 0008
0009
Figure 12.78 Example of External Pulse Width Measurement (Measuring High Pulse Width)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.11 Dead Time Compensation By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation.
Tdead Upper arm signal Lower arm signal Inverter output detection signal Tdelay Dead time delay signal
Figure 12.79 Delay in Dead Time in Complementary PWM Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
Example of Dead Time Compensation Setting Procedure
Figure 12.80 shows an example of dead time compensation setting procedure by using three counters in channel 5.
Complementary PWM mode External pulse width measurement Start count operation in channels 3 to 5
[1]
[1] Place channels 3 and 4 in complementary PWM mode. For details, refer to section 12.4.8, Complementary PWM Mode. [2] Specify the external pulse width measurement function for the target TIOR in channel 5. For details, refer to section 12.4.10, External Pulse Width Measurement. [3] Set bits CST3 and CST4 in TSTR and bits CST5U, CST5V, and CST5W in TSTR2 to 1 to start count operation. [4] When the capture condition specified in TIOR is satisfied, the TCNT_5 value is captured in TGR_5. [5] For U-phase dead time compensation, when an interrupt is generated at the crest (TGIA_3) or trough (TCIV_4) in complementary PWM mode, read the TGRU_5 value, calculate the difference in time in TGRB_3, and write the corrected value to TGRD_3 in the interrupt processing. For the V phase and W phase, read the TGRV_5 and TGRW_5 values and write the corrected values to TGRC_4 and TGRD_4, respectively, in the same way as for U-phase compensation. The TCNT_5 value should be cleared through the TCNTCMPCLR setting or by software.
[2]
[3]
TCNT_5 input capture occurs
[4] *
Interrupt processing
[5]
Notes:
The PFC settings must be completed in advance. * As an interrupt flag is set under the capture condition specified in TIOR, do not enable interrupt requests in TIER_5.
Figure 12.80 Example of Dead Time Compensation Setting Procedure
MTU ch3/4 ch5
Complementary PWM output
DC
+
Level conversion
Dead time delay input
W Inverter output monitor signals V U V U W U V W Motor
Figure 12.81 Example of Motor Control Circuit Configuration
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 12.82 is an operating example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough).
TGRA_4 Tdead
Upper arm signal Lower arm signal Inverter output monitor signal
Tdelay
Dead time delay signal Up-count/down-count signal (udflg) TCNT[15:0] TGR[15:0]
3DE7 3E5B 3DE7 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF
Figure 12.82 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.5
12.5.1
Interrupt Sources
Interrupt Sources and Priorities
There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 12.57 lists the MTU2 interrupt sources. Table 12.57 MTU2 Interrupts
Channel Name
Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRE_0 compare match TGRF_0 compare match TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow
Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFE_0 TGFF_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2
DMAC Activation Possible Not possible Not possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible
Priority High
0
TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 TGIE_0 TGIF_0
1
TGIA_1 TGIB_1 TCIV_1 TCIU_1
2
TGIA_2 TGIB_2 TCIV_2 TCIU_2
Low
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel Name
Interrupt Source TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TGRC_4 input capture/compare match TGRD_4 input capture/compare match TCNT_4 overflow/underflow TGRU_5 input capture/compare match TGRV_5 input capture/compare match TGRW_5 input capture/compare match
Interrupt Flag TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 TGFU_5 TGFV_5 TGFW_5
DMAC Activation Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Not possible Not possible Not possible Not possible
Priority High
3
TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3
4
TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4
5
TGIU_5 TGIV_5 TGIW_5
Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
(1)
Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. (2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. (3) Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.5.2
DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel. For details, see section 11, Direct Memory Access Controller (DMAC). In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC activation sources, one each for channels 0 to 4. 12.5.3 A/D Converter Activation
The A/D converter can be activated by one of the following three methods in the MTU2. Table 12.58 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode
The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions. * When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1 * When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0
The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. (3) A/D Converter Activation by A/D Converter Start Request Delaying Function
The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the TAD4AE or TAD4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 12.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated. Table 12.58 Interrupt Sources and A/D Converter Start Request Signals
Target Registers TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4 TGRE_0 and TCNT_0 TADCORA and TCNT_4 TADCORB and TCNT_4 TCNT_4 Trough in complementary PWM mode Compare match TRG0N TRG4AN TRG4BN Interrupt Source Input capture/compare match A/D Converter Start Request Signal TRGAN
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.6
12.6.1 (1)
Operation Timing
Input/Output Timing
TCNT Count Timing
Figures 12.83 and 12.84 show TCNT count timing in internal clock operation, and figure 12.85 shows TCNT count timing in external clock operation (normal mode), and figure 12.86 shows TCNT count timing in external clock operation (phase counting mode).
P Internal clock TCNT input clock TCNT N-1 N N+1 Falling edge Rising edge
Figure 12.83 Count Timing in Internal Clock Operation (Channels 0 to 4)
P Internal clock TCNT input clock TCNT N-1 N Rising edge
Figure 12.84 Count Timing in Internal Clock Operation (Channel 5)
P External clock TCNT input clock TCNT N-1 N N+1 Falling edge Rising edge
Figure 12.85 Count Timing in External Clock Operation (Channels 0 to 4)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
P External clock TCNT input clock TCNT N-1 N N-1 Rising edge Falling edge
Figure 12.86 Count Timing in External Clock Operation (Phase Counting Mode) (2) Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 12.87 shows output compare output timing (normal mode and PWM mode) and figure 12.88 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode).
P TCNT input clock N N+1
TCNT
TGR Compare match signal TIOC pin
N
Figure 12.87 Output Compare Output Timing (Normal Mode/PWM Mode)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
P TCNT input clock
TCNT
N
N+1
TGR
N
Compare match signal
TIOC pin
Figure 12.88 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) (3) Input Capture Signal Timing
Figure 12.89 shows input capture signal timing.
P Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 12.89 Input Capture Input Signal Timing
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Timing for Counter Clearing by Compare Match/Input Capture
Figures 12.90 and 12.91 show the timing when counter clearing on compare match is specified, and figure 12.92 shows the timing when counter clearing on input capture is specified.
P Compare match signal Counter clear signal TCNT N H'0000
TGR
N
Figure 12.90 Counter Clear Timing (Compare Match) (Channel 0 to Channel 4)
P Compare match signal Counter clear signal TCNT TGR N-1 N H'0000
Figure 12.91 Counter Clear Timing (Compare Match) (Channel 5)
P Input capture signal Counter clear signal TCNT N H'0000
TGR
N
Figure 12.92 Counter Clear Timing (Input Capture) (Channel 0 to Channel 5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(5)
Buffer Operation Timing
Figures 12.93 to 12.95 show the timing in buffer operation.
P TCNT Compare match buffer signal TGRA, TGRB TGRC, TGRD n N n n+1
N
Figure 12.93 Buffer Operation Timing (Compare Match)
P Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1
n
N
N+1
n
N
Figure 12.94 Buffer Operation Timing (Input Capture)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
P
TCNT TCNT clear signal Buffer transfer signal TGRA, TGRB, TGRE TGRC, TGRD, TGRF
n
H'0000
n
N
N
Figure 12.95 Buffer Transfer Timing (when TCNT Cleared) (6) Buffer Transfer Timing (Complementary PWM Mode)
Figures 12.96 to 12.98 show the buffer transfer timing in complementary PWM mode.
P
TCNTS
H'0000
TGRD_4 write signal Temporary register transfer signal
Buffer register Temporary register
n
N
n
N
Figure 12.96 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
P
TCNTS
P-x
P
H'0000
TGRD_4 write signal Buffer register Temporary register
n
N
n
N
Figure 12.97 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating)
P
TCNTS
P-1
P
H'0000
Buffer transfer signal Temporary register Compare register
N
n
N
Figure 12.98 Transfer Timing from Temporary Register to Compare Register
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.6.2 (1)
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match
Figures 12.99 and 12.100 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
P TCNT input clock TCNT N N+1
TGR Compare match signal TGF flag
N
TGI interrupt
Figure 12.99 TGI Interrupt Timing (Compare Match) (Channels 0 to 4)
P TCNT input clock TCNT N-1 N
TGR Compare match signal TGF flag
N
TGI interrupt
Figure 12.100 TGI Interrupt Timing (Compare Match) (Channel 5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
TGF Flag Setting Timing in Case of Input Capture
Figures 12.101 and 12.102 show the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
P Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 12.101 TGI Interrupt Timing (Input Capture) (Channels 0 to 4)
P Input capture signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 12.102 TGI Interrupt Timing (Input Capture) (Channel 5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
TCFV Flag/TCFU Flag Setting Timing
Figure 12.103 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 12.104 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
P TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000
TCFV flag
TCIV interrupt
Figure 12.103 TCIV Interrupt Setting Timing
P TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF
TCIU interrupt
Figure 12.104 TCIU Interrupt Setting Timing
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figures 12.105 and 12.106 show the timing for status flag clearing by the CPU, and figure 12.107 show the timing for status flag clearing by the DMAC.
TSR write cycle T1 T2 P
Address
TSR address
Write signal
Status flag Interrupt request signal
Figure 12.105 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
TSR write cycle T1 T2 P
Address
TSR address
Write signal
Status flag Interrupt request signal
Figure 12.106 Timing for Status Flag Clearing by CPU (Channel 5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
DMAC read cycle P, B Address Status flag Source addess
DMAC write cycyle
Destination addres
Interrupt request signal Flag clear signal
Figure 12.107 Timing for Status Flag Clearing by DMAC Activation (Channels 0 to 4)
12.7
12.7.1
Usage Notes
Module Standby Mode Setting
MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 27, Power-Down Modes. 12.7.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 12.108 shows the input clock conditions in phase counting mode.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Overlap TCLKA (TCLKC) TCLKB (TCLKD)
Phase Phase differdifference Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more
Figure 12.108 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 12.7.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: * Channels 0 to 4 f= * Channel 5 f= Where f: P: N: P N Counter frequency MTU2 peripheral clock operating frequency TGR set value P (N + 1)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.4
Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 12.109 shows the timing in this case.
TCNT write cycle T1 T2 P Address Write signal Counter clear signal TCNT N H'0000 TCNT address
Figure 12.109 Contention between TCNT Write and Clear Operations 12.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 12.110 shows the timing in this case.
TCNT write cycle T2 T1 P Address Write signal TCNT input clock TCNT N TCNT write data M TCNT address
Figure 12.110 Contention between TCNT Write and Increment Operations
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.6
Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 12.111 shows the timing in this case.
TGR write cycle T2 T1 P Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address
Figure 12.111 Contention between TGR Write and Compare Match
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.7
Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 12.112 shows the timing in this case.
TGR write cycle T1 T2
P Address Buffer register address
Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M
TGR
N
Figure 12.112 Contention between Buffer Register Write and Compare Match
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.8
Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 12.113 shows the timing in this case.
TGR write cycle T1 T2 P Address Write signal TCNT clear signal Buffer transfer signal Buffer register N M Buffer register address
Buffer register write data
TGR
N
Figure 12.113 Contention between Buffer Register Write and TCNT Clear
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.9
Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 12.114 and 12.115 show the timing in this case.
TGR read cycle T1 T2 P Address Read signal Input capture signal TGR Internal data bus N M
TGR address
N
Figure 12.114 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle T1 T2 P Address Read signal Input capture signal TGR Internal data bus N M
TGR address
M
Figure 12.115 Contention between TGR Read and Input Capture (Channel 5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 12.116 and 12.117 show the timing in this case.
TGR write cycle T1 T2 P Address Write signal Input capture signal TCNT TGR M M TGR address
Figure 12.116 Contention between TGR Write and Input Capture (Channels 0 to 4)
TGR write cycle T2 T1 P Address Write signal Input capture signal TCNT M TGR write data TGR N TGR address
Figure 12.117 Contention between TGR Write and Input Capture (Channel 5)
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 12.118 shows the timing in this case.
Buffer register write cycle T2 T1
P
Address Write signal Input capture signal TCNT TGR Buffer register M N N M
Buffer register address
Figure 12.118 Contention between Buffer Register Write and Input Capture 12.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to TGRD_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 12.119. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT write cycle T1 T2
P
Address Write signal TCNT_2 H'FFFE H'FFFF TCNT_2 write data TGRA_2 to TGRB_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D P N M M M Disabled H'FFFF N N+1 TCNT_2 address
Q
P
Figure 12.119 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 12.120. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values.
TGRA_3 TCDR
TCNT_3
TCNT_4
TDDR H'0000 Complementary PWM mode operation Counter operation stop Complementary PWM mode operation Complementary PMW restart
Figure 12.120 Counter Value during Complementary PWM Mode Stop 12.7.14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 12.121 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.
TGRA_3 TCNT3 TGRC_3 Point a Buffer transfer with compare match A3 TGRA_3, TGRC_3
TGRB_3, TGRA_4, TGRB_4 Point b
TGRD_3, TGRC_4, TGRD_4 H'0000
TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4
TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set
Figure 12.121 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit in TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 12.122 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source.
Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4
H'0000 TCFV_3 TCFV_4 Not set Not set
Figure 12.122 Reset Synchronous PWM Mode Overflow Flag
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.123 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR.
P TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000
TCFV
Figure 12.123 Contention between Overflow and Counter Clearing
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 12.124 shows the operation timing when there is contention between TCNT write and overflow.
TCNT write cycle T2 T1 P
Address Write signal
TCNT address
TCNT write data TCNT H'FFFF Disabled M
TCFV flag
Figure 12.124 Contention between TCNT Write and Overflow 12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00. 12.7.21 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module standby mode. 12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.8
12.8.1
MTU2 Output Pin Initialization
Operating Modes
The MTU2 has the following six operating modes. Waveform output is possible in all of these modes. * * * * * * Normal mode (channels 0 to 4) PWM mode 1 (channels 0 to 4) PWM mode 2 (channels 0 to 2) Phase counting modes 1 to 4 (channels 1 and 2) Complementary PWM mode (channels 3 and 4) Reset-synchronized PWM mode (channels 3 and 4)
The MTU2 output pin initialization method for each of these modes is described in this section. 12.8.2 Reset Start Operation
The MTU2 output pins (TIOC*) are initialized low by a power-on reset. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a power-on reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.8.3
Operation in Case of Re-Setting Due to Error During Operation, etc.
If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 12.59. Table 12.59 Mode Transition Combinations
After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29)
[Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.8.4
Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc.
* When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. * When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 12.59. The active level is assumed to be low. (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 12.125 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
1 2 3 Power-on TMDR TOER reset (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2 High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.125 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a power-on reset, MTU2 output is low and ports are in the high-impedance state. After a power-on reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Not necessary when restarting in normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1
Figure 12.126 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 Power-on TMDR TOER reset (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2 High-Z High-Z
Not initialized (TIOC*B)
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.126 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.125. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2
Figure 12.127 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting.
1 2 3 Power-onTMDR TOER reset (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2 High-Z High-Z
Not initialized (cycle register)
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.127 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 12.125. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode
Figure 12.128 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
1 2 3 Power-on TMDR TOER reset (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2 High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.128 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12.125. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(5)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode
Figure 12.129 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
12 6 7 8 9 10 11 1 2 3 4 5 14 15 (16) (17) (18) 13 Power-on TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0 init (disabled) (0) reset (normal) (1) (1 init (MTU2) (1) (CPWM) (1) (MTU2) (1) 0 out) 0 out)
MTU2 TIOC3A TIOC3B TIOC3D
module output
Port output PB16 PB17 PB19 High-Z High-Z High-Z
Figure 12.129 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.125. 11. 12. 13. 14. 15. 16. 17. 18. Initialize the normal mode waveform generation section with TIOR. Disable operation of the normal mode waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(6)
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode
Figure 12.130 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
1 2 3 4 5 6 Power-on TMDR TOER TIOR PFC TSTR reset (normal) (1) (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 11 12 14 15 16 17 18 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) (0 init (disabled) (0) 0 out)
MTU2 TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19
module output
High-Z High-Z High-Z
Figure 12.130 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 12.125. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(7)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode
Figure 12.131 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
1 2 3 Power-onTMDR TOER reset (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (TIOC*B)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.131 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a power-on reset, MTU2 output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(8)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1
Figure 12.132 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
1 2 3 Power-on TMDR TOER reset (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (TIOC*B)
Not initialized (TIOC*B)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.132 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.131. 11. 12. 13. 14. Not necessary when restarting in PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(9)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2
Figure 12.133 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting.
1 2 3 Power-on TMDR TOER reset (PWM1) (1) MTU2 module output
5 4 6 PFC TSTR TIOR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out)
TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2 High-Z High-Z Not initialized (TIOC*B)
Not initialized (cycle register)
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.133 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 12.131. 11. 12. 13. 14. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 12.134 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
2 3 1 Power-on TMDR TOER reset (PWM1) (1) 5 4 6 PFC TSTR TIOR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (TIOC*B)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.134 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12.131. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.135 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
1 2 3 4 5 6 Power-on TMDR TOER TIOR PFC TSTR reset (PWM1) (1) (1 init (MTU2) (1) 0 out) 7 8 9 10 11 12 13 14 15 16 17 18 19 Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU2) (1) 0 out)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19
Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z
Figure 12.135 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.131. 11. 12. 13. 14. 15. 16. 17. 18. 19. Set normal mode for initialization of the normal mode waveform generation section. Initialize the PWM mode 1 waveform generation section with TIOR. Disable operation of the PWM mode 1 waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.136 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
1 2 3 4 5 6 Power-on TMDR TOER TIOR PFC TSTR reset (PWM1) (1) (1 init (MTU2) (1) 0 out) 7 8 9 10 11 12 13 14 15 16 17 18 19 Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19
Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z
Figure 12.136 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 12.135. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 12.137 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
1 2 3 4 5 6 PFC TSTR Match Power-on TMDR TIOR reset (PWM2) (1 init (MTU2) (1) 0 out)
7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (cycle register)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.137 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU2 output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 12.138 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 7 8 9 10 11 12 13 Power-on TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR reset (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (cycle register) Not initialized (TIOC*B)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.138 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 12.137. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 12.139 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting.
2 3 5 4 6 1 PFC TSTR Match Power-on TMDR TIOR reset (PWM2) (1 init (MTU2) (1) 0 out) 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (cycle register)
Not initialized (cycle register)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.139 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 12.137. 10. 11. 12. 13. Not necessary when restarting in PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 12.140 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
1 2 3 5 4 6 Power-on TMDR TIOR PFC TSTR Match reset (PWM2) (1 init (MTU2) (1) 0 out)
7 8 9 10 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (cycle register)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.140 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12.137. 10. 11. 12. 13. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 12.141 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
1 2 Power-onTMDR reset (PCM)
3 4 5 6 TIOR PFC TSTR Match (1 init (MTU2) (1) 0 out) 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.141 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a power-on reset, MTU2 output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set in normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.142 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
1 2 Power-on TMDR reset (PCM)
3 5 4 6 TIOR PFC TSTR Match (1 init (MTU2) (1) 0 out) 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (TIOC*B)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.142 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 12.141. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 12.143 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
1 2 Power-on TMDR reset (PCM)
3 5 4 6 TIOR PFC TSTR Match (1 init (MTU2) (1) 0 out) 7 8 9 10 11 12 13 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
Not initialized (cycle register)
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.143 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 12.141. 10. 11. 12. 13. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 12.144 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
1 2 Power-on TMDR reset (PCM)
3 5 4 6 TIOR PFC TSTR Match (1 init (MTU2) (1) 0 out) 7 8 9 10 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC*A TIOC*B Port output PB, PC, PD*1 PB, PC, PD*2
High-Z High-Z
Notes: 1. This pin is multiplexed with TIOC*A. 2. This pin is multiplexed with TIOC*B.
Figure 12.144 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12.141. 10. 11. 12. 13. Not necessary when restarting in phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 12.145 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 Power-on TOCR TMDR TOER PFC TSTR reset (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19 High-Z High-Z High-Z
Figure 12.145 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a power-on reset, MTU2 output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM output initial value.) Set normal mode. (MTU2 output goes low.) Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.146 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 Power-on TOCR TMDR TOER PFC TSTR reset (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out)
MTU2 module output
TIOC3A TIOC3B TIOC3D Port output
Not initialized (TIOC3B) Not initialized (TIOC3D)
PB16 PB17 PB19
High-Z High-Z High-Z
Figure 12.146 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.145. 11. 12. 13. 14. Set PWM mode 1. (MTU2 output goes low.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.147 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
1 2 3 5 4 6 7 8 9 10 11 12 13 Power-on TOCR TMDR TOER PFC TSTR Match Error PFC TSTR PFC TSTR Match reset (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (MTU2) (1)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19
High-Z High-Z High-Z
Figure 12.147 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.145. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.148 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 Power-on TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR reset (CPWM) (1) (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0)
MTU2 module output
TIOC3A TIOC3B TIOC3D Port output
PB16 PB17 PB19
High-Z High-Z High-Z
Figure 12.148 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.145. 11. Set normal mode and make new settings. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.149 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode.
1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 Power-on TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) (RPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0)
reset MTU2 module output
TIOC3A TIOC3B TIOC3D Port output High-Z PB16 High-Z PB17 High-Z PB19
Figure 12.149 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 12.145. 11. Set normal mode. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(26) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 12.150 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in normal mode after re-setting.
1 2 3 5 4 6 Power-on TOCR TMDR TOER PFC TSTR reset (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19 High-Z High-Z High-Z
Figure 12.150 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a power-on reset, MTU2 output is low and ports are in the high-impedance state. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronized PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. The count operation is started by TSTR. The reset-synchronized PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized PWM output initial value.) Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(27) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.151 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
1 2 3 5 4 6 Power-on TOCR TMDR TOER PFC TSTR reset (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19
Not initialized (TIOC3B) Not initialized (TIOC3D) High-Z High-Z High-Z
Figure 12.151 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.150. 11. 12. 13. 14. Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.152 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in complementary PWM mode after resetting.
1 2 3 4 5 6 Power-on TOCR TMDR TOER PFC TSTR reset (RPWM) (1) (MTU2) (1)
7 Match
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19
8 9 10 11 12 13 14 15 16 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU2) (1)
High-Z High-Z High-Z
Figure 12.152 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.150. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU2 cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU2 output with the PFC. 16. Operation is restarted by TSTR.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(29) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.153 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in reset-synchronized PWM mode after resetting.
1 2 3 5 4 6 Power-on TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) reset
7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1)
MTU2 module output TIOC3A TIOC3B TIOC3D Port output PB16 PB17 PB19 High-Z High-Z High-Z
Figure 12.153 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 12.150. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence.
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
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Section 13 8-Bit Timers (TMR)
Section 13 8-Bit Timers (TMR)
This LSI has an on-chip 2-channel 8-bit timer based on an 8-bit counter. It can be used to count external events and, using compare-match signals with two registers, as a multifunction timer in a variety of applications, such as the generation of counter resets, interrupt requests, and pulse output with a user-defined duty cycle. Figure 13.1 shows a block diagram of the 8-bit timer.
13.1
Features
* Selection of seven clock sources The counters can be driven by one of six internal clock signals (P/8, P/64, P/8192, P/2, P/32, or P/1024) or an external clock input. * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal. * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM output. * Cascading of two channels (TMR_0 and TMR_1) Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode). TMR_1 can be used to count TMR_0 compare matches (compare match count mode). * Three interrupt sources Compare match A, compare match B, and overflow interrupts can be requested independently. * Generation of trigger to start A/D converter conversion
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Section 13 8-Bit Timers (TMR)
External clocks TMCI0 TMCI1 Clock select
Internal clocks P/8 P/64 P/8192 P/2 P/32 P/1024 Counter clock 1 Counter clock 0 TCORA_0 Compare match A1 Compare match A0 Comparator A_0 Overflow 1 Overflow 0 Counter clear 0 Counter clear 1 Compare match B1 Compare match B0 Control logic TCORB_0 TCSR_0 TCR_0 TCCR_0 CMIA0 CMIA1 CMIB0 CMIB1 OVI0 OVI1 Interrupt signals TCORB_1 TCSR_1 TCR_1 TCCR_1 TCORA_1
Comparator A_1
Comparator B_0
Comparator B_1
TMRI0 TMRI1 A/D conversion start request signal
[Legend] TCORA_0: TCNT_0: TCORB_0: TCSR_0: TCR_0: TCCR_0:
Time constant register A_0 Timer counter_0 Time constant register B_0 Timer control/status register_0 Timer control register_0 Timer counter control register_0
TCORA_1: TCNT_1: TCORB_1: TCSR_1: TCR_1: TCCR_1:
Time constant register A_1 Timer counter_1 Time constant register B_1 Timer control/status register_1 Timer control register_1 Timer counter control register_1
Figure 13.1 Block Diagram of 8-Bit Timer
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Peripheral bus
TMO0 TMO1
TCNT_0
TCNT_1
Section 13 8-Bit Timers (TMR)
13.2
Input/Output Pins
Table 13.1 shows the pin configuration of the TMR. Table 13.1 Pin Configuration
Channel 0 Name Timer output pin Timer clock input pin Timer reset input pin 1 Timer output pin Timer clock input pin Timer reset input pin Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Outputs compare match Inputs external clock for counter Inputs external reset to counter Outputs compare match Inputs external clock for counter Inputs external reset to counter
13.3
Register Descriptions
The TMR has the following registers. Channel 0: * * * * * * Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer counter control register_0 (TCCR_0) Timer control/status register_0 (TCSR_0)
Channel 1: * * * * * * Timer counter_1 (TCNT_1) Time constant register A_1 (TCORA_1) Time constant register B_1 (TCORB_1) Timer control register_1 (TCR_1) Timer counter control register_1 (TCCR_1) Timer control/status register_1 (TCSR_1)
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Section 13 8-Bit Timers (TMR)
13.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an external reset input signal, compare match A signal, or compare match B signal. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, bit OVF in TCSR is set to 1. TCNT is initialized to H'00.
TCNT_0 Bit: 7 6 5 4 3 2 1 0 7 6 5 TCNT_1 4 3 2 1 0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
13.3.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF.
TCORA_0 Bit: 7 6 5 4 3 2 1 0 7 6 5 TCORA_1 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
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Section 13 8-Bit Timers (TMR)
13.3.3
Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.
TCORB_0 Bit: 7 6 5 4 3 2 1 0 7 6 5 TCORB_1 4 3 2 1 0
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
13.3.4
Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition for clearing TCNT, and enables/disables interrupt requests.
Bit: 7 6 5 4 3 2 1 CKS[2:0] 0 R/W 0 R/W 0 R/W 0
CMIEB CMIEA OVIE
CCLR[1:0] 0 R/W 0 R/W
Initial value: 0 R/W: R/W
0 R/W
0 R/W
Bit 7
Bit Name CMIEB
Initial Value 0
R/W R/W
Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled
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Section 13 8-Bit Timers (TMR)
Bit 6
Bit Name CMIEA
Initial Value 0
R/W R/W
Description Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled
4, 3
CCLR[1:0]
00
R/W
Counter Clear 1 and 0* These bits select the method by which TCNT is cleared. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared at rising edge (TMRIS in TCCR is cleared to 0) of the external reset input or when the external reset input is high (TMRIS in TCCR is set to 1)
2 to 0
CKS[2:0]
000
R/W
Clock Select 2 to 0* These bits select the clock input to TCNT and count condition. See table 13.2.
Note:
*
To use an external reset or external clock, the function of the corresponding pin should be selected using the pin function controller (PFC). For details, see section 25, Pin Function Controller (PFC).
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Section 13 8-Bit Timers (TMR)
13.3.5
Timer Counter Control Register (TCCR)
TCCR selects the TCNT internal clock source and controls external reset input.
Bit: 7 -- Initial value: 0 R/W: R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3
TMRIS
2 -- 0 R/W
1
0
ICKS[1:0] 0 R/W 0 R/W
0 R/W
Bit 7 to 4
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
3
TMRIS
0
R/W
Timer Reset Input Select Selects an external reset input when the CCLR1 and CCLR0 bits in TCR are B'11. 0: Cleared at rising edge of the external reset 1: Cleared when the external reset is high
2
0
R/W
Reserved This bit is always read as 0. The write value should always be 0
1, 0
ICKS[1:0]
00
R/W
Internal Clock Select 1 and 0 These bits in combination with bits CKS2 to CKS0 in TCR select the internal clock. See table 13.2.
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Section 13 8-Bit Timers (TMR)
Table 13.2 Clock Input to TCNT and Count Condition
TCR Channel TMR_0 Bit 2 CKS2 0 0 TCCR Description Clock input prohibited. Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_1 overflow signal* . Clock input prohibited. Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_0 compare match A* .
1 1
Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
1
0
0 0 1 1
0
1
1
0 0 1 1
1 TMR_1 0 0
0 0 0
0 0 1
0 0 1 1
0
1
0
0 0 1 1
0
1
1
0 0 1 1
1
0
0
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Section 13 8-Bit Timers (TMR)
TCR Channel All Bit 2 CKS2 1 1 1
TCCR Description Uses external clock. Counts at rising edge* . Uses external clock. Counts at falling edge* . Uses external clock. Counts at both rising and falling 2 edges* .
2 2
Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 0 1 1 1 0 1
Notes: 1. If the clock input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. To use the external clock, the function of the corresponding pin should be selected using the pin function controller (PFC). For details, see section 25, Pin Function Controller (PFC).
13.3.6
Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output. * TCSR_0
Bit: 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE Initial value: 0 0 0 0 R/W: R/(W)*R/(W)*R/(W)* R/W Note: OS[3:2] 0 R/W 0 R/W OS[1:0] 0 R/W 0 R/W
* Only 0 can be written to this bit, to clear the flag.
* TCSR_1
Bit: 7 6 5 4 -- 0 R 3 2 1 0 CMFB CMFA OVF Initial value: 0 0 0 R/W: R/(W)*R/(W)*R/(W)* Note: OS[3:2] 0 R/W 0 R/W OS[1:0] 0 R/W 0 R/W
* Only 0 can be written to this bit, to clear the flag.
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Section 13 8-Bit Timers (TMR)
* TCSR_0
Bit 7 Bit Name CMFB Initial Value 0 R/W
1
Description
R/(W)* Compare Match Flag B [Setting condition] * * When TCNT matches TCORB When writing 0 after reading CMFB = 1 [Clearing condition]
6
CMFA
0
R/(W)*1 Compare Match Flag A [Setting condition] * * When TCNT matches TCORA When writing 0 after reading CMFA = 1 [Clearing condition]
5
OVF
0
R/(W)* Timer Overflow Flag [Setting condition] * * When TCNT overflows from H'FF to H'00 When writing 0 after reading OVF = 1 [Clearing condition]
1
4
ADTE
0
R/W
A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled
3, 2
OS[3:2]
00
R/W
Output Select 3 and 2*2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output)
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Section 13 8-Bit Timers (TMR)
Bit 1, 0
Bit Name OS[1:0]
Initial Value 00
R/W R/W
Description Output Select 1 and 0*2 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after resetting.
* TCSR_1
Bit 7 Bit Name CMFB Initial Value 0 R/W R/(W)*
1
Description Compare Match Flag B [Setting condition] * * When TCNT matches TCORB When writing 0 after reading CMFB = 1 [Clearing condition]
6
CMFA
0
R/(W)*
1
Compare Match Flag A [Setting condition] * * When TCNT matches TCORA When writing 0 after reading CMFA = 1 [Clearing condition]
5
OVF
0
R/(W)*
1
Timer Overflow Flag [Setting condition] * * When TCNT overflows from H'FF to H'00 When writing 0 after reading OVF = 1 [Clearing condition]
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Section 13 8-Bit Timers (TMR)
Bit 4 3, 2
Bit Name OS[3:2]
Initial Value 0 00
R/W R R/W
Description Reserved This is a read-only bit and cannot be modified. Output Select 3 and 2*2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output)
1, 0
OS[1:0]
00
R/W
Output Select 1 and 0*2 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after resetting.
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Section 13 8-Bit Timers (TMR)
13.4
13.4.1
Operation
Pulse Output
Figure 13.2 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. The control bits are set as follows: 1. In TCR, clear bit CCLR1 to 0 and set bit CCLR0 to 1 so that TCNT is cleared at a TCORA compare match. 2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a pulse width determined by TCORB. No software intervention is required. The output level of the 8-bit timer holds 0 until the first compare match occurs after a reset.
TCNT H'FF TCORA TCORB H'00 Counter clear
TMO
Figure 13.2 Example of Pulse Output
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Section 13 8-Bit Timers (TMR)
13.4.2
Reset Input
Figure 13.3 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRI input. The control bits are set as follows: 1. Set both bits CCLR1 and CCLR0 in TCR to 1 and set the TMRIS bit in TCCR to 1 so that TCNT is cleared at the high level input of the TMRI signal. 2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a desired delay time from a TMRI input determined by TCORA and with a pulse width determined by TCORB and TCORA.
TCORB TCORA TCNT
H'00
TMRI TMO
Figure 13.3 Example of Reset Input
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Section 13 8-Bit Timers (TMR)
13.5
13.5.1
Operation Timing
TCNT Count Timing
Figure 13.4 shows the TCNT count timing for internal clock input. Figure 13.5 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
P
Internal clock TCNT input clock
TCNT
N-1
N
N+1
Figure 13.4 Count Timing for Internal Clock Input at Falling Edge
P External clock input pin TCNT input clock TCNT N-1 N N+1
Figure 13.5 Count Timing for External Clock Input at Falling and Rising Edges
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Section 13 8-Bit Timers (TMR)
13.5.2
Timing of CMFA and CMFB Setting at Compare Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT values match, the compare match signal is not generated until the next TCNT clock input. Figure 13.6 shows this timing.
P TCNT TCOR Compare match signal CMF N N N+1
Figure 13.6 Timing of CMF Setting at Compare Match 13.5.3 Timing of Timer Output at Compare Match
When a compare match signal is generated, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.7 shows the timing when the timer output is toggled by the compare match A signal.
P Compare match A signal Timer output pin
Figure 13.7 Timing of Toggled Timer Output at Compare Match A
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Section 13 8-Bit Timers (TMR)
13.5.4
Timing of Counter Clear by Compare Match
TCNT is cleared when compare match A or B occurs, depending on the settings of bits CCLR1 and CCLR0 in TCR. Figure 13.8 shows the timing of this operation.
P Compare match signal TCNT N H'00
Figure 13.8 Timing of Counter Clear by Compare Match 13.5.5 Timing of TCNT External Reset
TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figures 13.9 and 13.10 show the timing of this operation.
P External reset input pin Clear signal TCNT N-1 N H'00
Figure 13.9 Timing of Clearance by External Reset (Rising Edge)
P External reset input pin Clear signal TCNT N-1 N H'00
Figure 13.10 Timing of Clearance by External Reset (High Level)
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Section 13 8-Bit Timers (TMR)
13.5.6
Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.11 shows the timing of this operation.
P TCNT Overflow signal H'FF H'00
OVF
Figure 13.11 Timing of OVF Setting
13.6
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). 13.6.1 16-Bit Counter Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. (1) Setting of Compare Match Flags
* The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. (2) Counter Clear Specification
* If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently.
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Section 13 8-Bit Timers (TMR)
(3)
Pin Output
* Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions. * Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions. 13.6.2 Compare Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are set to B'100, TCNT_1 counts compare match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel.
13.7
13.7.1
Interrupt Sources
Interrupt Sources
There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI. Their interrupt sources and priorities are shown in table 13.3. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. Table 13.3 8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources
Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt Source TCORA_0 compare match TCORB_0 compare match TCNT_0 overflow TCORA_1 compare match TCORB_1 compare match TCNT_1 overflow Interrupt Flag CMFA CMFB OVF CMFA CMFB OVF Low Low High Priority High
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Section 13 8-Bit Timers (TMR)
13.7.2
A/D Converter Activation
The A/D converter can be activated only by TMR_0 compare match A. If the ADTE bit in TCSR_0 is set to 1 when the CMFA flag in TCSR_0 is set to 1 by the occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started.
13.8
13.8.1
Usage Notes
Notes on Setting Cycle
If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in which the values of TCNT and TCOR match. TCNT updates the counter value at this last state. Therefore, the counter frequency is obtained by the following formula.
f = P/(N + 1) f: Counter frequency P: Operating frequency N: TCOR value
13.8.2
Conflict between TCNT Write and Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle, the clear takes priority and the write is not performed as shown in figure 13.12.
TCNT write cycle by CPU T1 T2 P Address Internal write signal Counter clear signal TCNT N H'00 TCNT address
Figure 13.12 Conflict between TCNT Write and Clear
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Section 13 8-Bit Timers (TMR)
13.8.3
Conflict between TCNT Write and Increment
If a TCNT input clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented as shown in figure 13.13.
TCNT write cycle by CPU T1 T2 P Address Internal write signal TCNT input clock TCNT N Counter write data M TCNT address
Figure 13.13 Conflict between TCNT Write and Increment 13.8.4 Conflict between TCOR Write and Compare Match
If a compare match event occurs during the T2 state of a TCOR write cycle, the TCOR write takes priority and the compare match signal is inhibited as shown in figure 13.14.
TCOR write cycle by CPU T1 T2 P Address Internal write signal TCNT TCOR N N TCOR write data Compare match signal Inhibited N+1 M TCOR address
Figure 13.14 Conflict between TCOR Write and Compare Match
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Section 13 8-Bit Timers (TMR)
13.8.5
Conflict between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.4. Table 13.4 Timer Output Priorities
Output Setting Toggle output 1-output 0-output No change Low Priority High
13.8.6
Switching of Internal Clocks and TCNT Operation
TCNT may be incremented erroneously depending on when the internal clock is switched. Table 13.5 shows the relationship between the timing at which the internal clock is switched (by writing to bits CKS1 and CKS0) and the TCNT operation. When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal clock pulse are always monitored. Table 13.5 assumes that the falling edge is selected. If the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and TCNT is incremented. This is similar to when the rising edge is selected. The erroneous incrementation of TCNT can also happen when switching between rising and falling edges of the internal clock, and when switching between internal and external clocks.
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Section 13 8-Bit Timers (TMR)
Table 13.5 Switching of Internal Clock and TCNT Operation
No. 1 Timing to Change CKS1 and CKS0 Bits Switching from low to low*
1
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT input clock TCNT N CKS bits changed N+1
2
Switching from low to high*
2
Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 N+2
CKS bits changed
3
Switching from high to low*
3
Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 CKS bits changed *4
N+2
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Section 13 8-Bit Timers (TMR)
No. 4
Timing to Change CKS1 and CKS0 Bits Switching from high to high
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 N+2 CKS bits changed
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated because the change of the signal levels is considered as a falling edge; TCNT is incremented.
13.8.7
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously. 13.8.8 Module Standby Setting
Operation of the TMR can be disabled or enabled using the standby control register. The initial setting is for operation of the TMR to be halted. Register access is enabled by clearing module standby mode. For details, see section 27, Power-Down Modes. 13.8.9 Interrupts in Module Standby Mode
If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode.
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Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT can simultaneously generate an internal reset signal for the entire LSI. The WDT is a single channel timer that counts up the clock oscillation settling period when the system leaves software standby mode or the temporary standby periods that occur when the clock frequency is changed. It can also be used as a general watchdog timer or interval timer.
14.1
Features
* Can be used to ensure the clock oscillation settling time The WDT is used in leaving software standby mode or the temporary standby periods that occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode, the WDTOVF signal is output externally. It is possible to select whether to reset the LSI internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset type. * Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. * Choice of eight counter input clocks Eight clocks (P x 1 to P x 1/16384) that are obtained by dividing the peripheral clock can be selected.
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Section 14 Watchdog Timer (WDT)
Figure 14.1 shows a block diagram of the WDT.
WDT Standby cancellation Standby control
Standby mode Peripheral clock Divider
Interrupt request WDTOVF Internal reset request*
Interrupt control Reset control WRCSR
Clock selection Clock selector Overflow WTCSR Clock WTCNT
Bus interface
[Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter WRCSR: Watchdog reset control/status register Note: * The internal reset signal can be generated by making a register setting.
Figure 14.1 Block Diagram of WDT
14.2
Input/Output Pin
Table 14.1 shows the pin configuration of the WDT. Table 14.1 Pin Configuration
Pin Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs the counter overflow signal in watchdog timer mode
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Section 14 Watchdog Timer (WDT)
14.3
Register Descriptions
The WDT has the following registers. Table 14.2 Register Configuration
Register Name Watchdog timer counter Watchdog timer control/status register Watchdog reset control/status register Note: * Abbreviation R/W WTCNT WTCSR WRCSR R/W R/W R/W Initial Value H'00 H'18 H'1F Address H'FFFE0002 H'FFFE0000 H'FFFE0004 Access Size 16* 16* 16*
For the access size, see section 14.3.4, Notes on Register Access.
14.3.1
Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a power-on reset caused by the RES pin or in deep standby mode or software standby mode. Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read from WTCNT. Note: The method for writing to WTCNT differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7 6 5 4 3 2 1 0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
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Section 14 Watchdog Timer (WDT)
14.3.2
Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in deep standby mode or software standby mode. When used to count the clock oscillation settling time for canceling software standby mode, it retains its value after counter overflow. Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from WTCSR. Note: The method for writing to WTCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7 6 5 4 -- 1 R 3 -- 1 R 0 R/W 2 1 CKS[2:0] 0 R/W 0 R/W 0
IOVF WT/IT TME Initial value: 0 0 R/W: R/(W) R/W 0 R/W
Bit 7
Bit Name IOVF
Initial Value 0
R/W R/(W)
Description Interval Timer Overflow Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT overflow in interval timer mode [Clearing condition] * When 0 is written to IOVF after reading IOVF
6
WT/IT
0
R/W
Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer mode 1: Use as watchdog timer mode Note: When the WTCNT overflows in watchdog timer mode, the WDTOVF signal is output externally. If this bit is modified when the WDT is running, the up-count may not be performed correctly.
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Section 14 Watchdog Timer (WDT)
Bit 5
Bit Name TME
Initial Value 0
R/W R/W
Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled
4, 3
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
2 to 0
CKS[2:0]
000
R/W
Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (P). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P) is 25 MHz. Bits 2 to 0 000: 001: 010: 011: 100: 101: 110: 111: Clock Ratio 1 x P 1/64 x P 1/128 x P 1/256 x P 1/512 x P 1/1024 x P 1/4096 x P 1/16384 x P Overflow Cycle 10.2 s 655.4 s 1.3 ms 2.6 ms 5.2 ms 10.5 ms 41.9 ms 167.8 ms
Note: If bits CKS[2:0] are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running.
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Section 14 Watchdog Timer (WDT)
14.3.3
Watchdog Reset Control/Status Register (WRCSR)
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. WRCSR is initialized to H'1F by input of a reset signal from the RES pin or in deep standby mode, but is not initialized by the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in software standby mode. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7 6 5 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 -- 1 R
WOVF RSTE RSTS
Initial value: 0 0 R/W: R/(W) R/W
0 R/W
Bit 7
Bit Name WOVF
Initial Value 0
R/W R/(W)
Description Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode [Clearing condition] * When 0 is written to WOVF after reading WOVF
6
RSTE
0
R/W
Reset Enable Selects whether to generate a signal to reset the LSI internally if WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Not reset when WTCNT overflows* 1: Reset when WTCNT overflows Note: * LSI not reset internally, but WTCNT and WTCSR reset within WDT.
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Section 14 Watchdog Timer (WDT)
Bit 5
Bit Name RSTS
Initial Value 0
R/W R/W
Description Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset
4 to 0
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
14.3.4
Notes on Register Access
The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. (1) Writing to WTCNT and WTCSR
These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write Address: H'FFFE0002
15 H'5A
8
7 Write data
0
WTCSR write Address: H'FFFE0000
15 H'A5
8
7 Write data
0
Figure 14.2 Writing to WTCNT and WTCSR
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Section 14 Watchdog Timer (WDT)
(2)
Writing to WRCSR
WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte transfer or longword transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 14.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit 15 Address: H'FFFE0004 H'A5 8 7 H'00 0
Writing to the RSTE and RSTS bits Address: H'FFFE0004
15 H'5A
8
7 Write data
0
Figure 14.3 Writing to WRCSR (3) Reading from WTCNT, WTCSR, and WRCSR
WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address H'FFFE0004. Byte transfer instructions must be used for reading from these registers.
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Section 14 Watchdog Timer (WDT)
14.4
14.4.1
WDT Usage
Canceling Software Standby Mode
The WDT can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (The WDT does not operate when resets are used for canceling, so keep the RES or MRES pin low until clock oscillation settles.) 1. Before making a transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. After setting the STBY bit to 1 and the DEEP bit to 0 in the standby control register (STBCR: see section 27, Power-Down Modes), the execution of a SLEEP instruction places the system in software standby mode and clock operation then stops. 4. The WDT starts counting by detecting the edge change of the NMI signal. 5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 14.4.2 Changing the Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. Note that, the WDT counts up by the clock to be set. 3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 5. The counter stops at the value of H'00. 6. Before changing WTCNT after execution of the frequency change instruction, always confirm that the value of WTCNT is H'00 by reading from WTCNT.
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Section 14 Watchdog Timer (WDT)
14.4.3
Using Watchdog Timer Mode
1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 64 x P clock cycles. 5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for 128 x P clock cycles. 6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin, the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.
WTCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 H'00 written in WTCNT WOVF = 1 WT/IT = 1 TME = 1 H'00 written in WTCNT
Time
WDTOVF and internal reset generated WDTOVF signal 64 x P clock cycles Internal reset signal* 128 x P clock cycles [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 14.4 Operation in Watchdog Timer Mode
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Section 14 Watchdog Timer (WDT)
14.4.4
Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting.
WTCNT value Overflow H'FF Overflow Overflow Overflow
H'00 ITI ITI ITI ITI
Time WT/IT = 0 TME = 1
[Legend] ITI: Interval timer interrupt request generation
Figure 14.5 Operation in Interval Timer Mode
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Section 14 Watchdog Timer (WDT)
14.5
Usage Notes
Pay attention to the following points when using the WDT in either the interval timer or watchdog timer mode. 14.5.1 Timer Variation
After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the peripheral clock, P, while the longest is the result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time difference is referred to as timer variation. This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation. 14.5.2 Prohibition against Setting H'FF to WTCNT
When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred. Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur immediately, regardless of the current clock selection by the CKS[2:0] bits. 14.5.3 System Reset by WDTOVF Signal
If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly. Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 14.6.
Reset input (low active)
RES
Reset signal to entire system (low active)
WDTOVF
Figure 14.6 Example of System Reset Circuit Using WDTOVF Signal
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Section 14 Watchdog Timer (WDT)
14.5.4
Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset occurs during DMAC burst transfer, manual reset exception handling will be pended until the CPU acquires the bus mastership. However, if the duration from generation of the manual reset to the bus cycle end is equal to or longer than the duration of the internal manual reset activated, the occurrence of the internal manual reset source is ignored instead of being pended, and the manual reset exception handling is not executed.
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Section 14 Watchdog Timer (WDT)
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Section 15 Realtime Clock (RTC)
Section 15 Realtime Clock (RTC)
This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator.
15.1
Features
* Clock and calendar functions (BCD format): Seconds, minutes, hours, date, day of the week, month, and year * 1-Hz to 64-Hz timer (binary format) 64-Hz counter indicates the state of the RTC divider circuit between 64 Hz and 1 Hz * Start/stop function * 30-second adjust function * Alarm interrupt: Frame comparison of seconds, minutes, hours, date, day of the week, month, and year can be used as conditions for the alarm interrupt * Periodic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds * Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read * Automatic leap year adjustment
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Section 15 Realtime Clock (RTC)
Figure 15.1 shows the block diagram of RTC.
Externally connected circuit
RTC_X1 Oscillator circuit RTC_X2
32.768 kHz
128 Hz
Count R64CNT RSECCNT RMINCNT RHRCNT RSECAR RMINAR RHRAR
Prescaler
Bus interface
RDAYCNT RTC operation control circuit RCR1 RCR2 RCR3
Interrupt control circuit
RDAYAR
RWKCNT RMONCNT
RWKAR RMONAR
RYRCNT
RYRAR
ARM PRD Interrupt CUP signals [Legend] RSECCNT: RMINCNT: RHRCNT: RWKCNT: RDAYCNT: RMONCNT: RYRCNT: R64CNT: RCR1: Second counter (8 bits) Minute counter (8 bits) Hour counter (8 bits) Day of week counter (8 bits) Date counter (8 bits) Month counter (8 bits) Year counter (16 bits) 64-Hz counter (8 bits) RTC control register 1 (8 bits) RSECAR: RMINAR: RHRAR: RWKAR: RDAYAR: RMONAR: RYRAR: RCR2: RCR3: Second alarm register (8 bits) Minute alarm registger (8 bits) Hour alarm register (8 bits) Day of week alarm register (8 bits) Date alarm register (8 bits) Month alarm register (8 bits) Year alarm register (16 bits) RTC control register 2 (8 bits) RTC control register 3 (8 bits)
Figure 15.1 RTC Block Diagram
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Peripheral bus
Section 15 Realtime Clock (RTC)
15.2
Input/Output Pin
Table 15.1 shows the RTC pin configuration. Table 15.1 Pin Configuration
Name RTC oscillator crystal pin RTC oscillator crystal pin Abbreviation RTC_X1 RTC_X2 I/O Input Output Description Connects 32.768-kHz crystal resonator for RTC Connects 32.768-kHz crystal resonator for RTC
15.3
Register Descriptions
The RTC has the following registers. Table 15.2 Register Configuration
Register Name 64-Hz counter Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date alarm register Month alarm register Year alarm register Abbreviation R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RYRAR R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'xx H'xx H'xx H'xx H'0x H'xx H'xx H'xxxx H'xx H'xx H'xx H'0x H'xx H'xx H'xxxx Address H'FFFE0800 H'FFFE0802 H'FFFE0804 H'FFFE0806 H'FFFE0808 H'FFFE080A H'FFFE080C H'FFFE080E H'FFFE0810 H'FFFE0812 H'FFFE0814 H'FFFE0816 H'FFFE0818 H'FFFE081A H'FFFE0820 Access Size 8 8 8 8 8 8 8 16 8 8 8 8 8 8 16
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Section 15 Realtime Clock (RTC)
Register Name RTC control register 1 RTC control register 2 RTC control register 3
Abbreviation RCR1 RCR2 RCR3
R/W R/W R/W R/W
Initial Value H'00 H'09 H'00
Address H'FFFE081C H'FFFE081E H'FFFE0824
Access Size 8 8 8
15.3.1
64-Hz Counter (R64CNT)
R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz. Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the RTC control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed at the same time is indicated. In this case, the R64CNT should be read again after writing 0 to the CF bit in RCR1 since the read value is not valid. After the RESET bit or ADJ bit in the RTC control register 2 (RCR2) is set to 1, the RTC divider circuit is initialized and R64CNT is initialized to H'00. R64CNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 -- Initial value: R/W: 0 R 6 1Hz -- R 5 2Hz -- R 4 4Hz -- R 3 8Hz -- R 2 1 0
16Hz 32Hz 64Hz -- R -- R -- R
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6 5 4 3 2 1 0
1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz
Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R
Indicate the state of the divider circuit between 64 Hz and 1 Hz.
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Section 15 Realtime Clock (RTC)
15.3.2
Second Counter (RSECCNT)
RSECCNT is used for setting/counting in the BCD-coded second section. The count operation is performed by a carry for each second of the 64-Hz counter. The assignable range is from 00 through 59 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RSECCNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 -- Initial value: R/W: 0 R -- R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 1 0
1 second -- R/W -- R/W -- R/W
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6 to 4 3 to 0
10 seconds 1 second
Undefined R/W Undefined R/W
Counting Ten's Position of Seconds Counts on 0 to 5 for 60-seconds counting. Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position.
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Section 15 Realtime Clock (RTC)
15.3.3
Minute Counter (RMINCNT)
RMINCNT is used for setting/counting in the BCD-coded minute section. The count operation is performed by a carry for each minute of the second counter. The assignable range is from 00 through 59 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RMINCNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 -- Initial value: R/W: 0 R -- R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 0
1 minute -- R/W -- R/W -- R/W
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0.The write value should always be 0.
6 to 4 3 to 0
10 minutes 1 minute
Undefined R/W Undefined R/W
Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minutes counting. Counting One's Position of Minutes Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position.
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Section 15 Realtime Clock (RTC)
15.3.4
Hour Counter (RHRCNT)
RHRCNT is used for setting/counting in the BCD-coded hour section. The count operation is performed by a carry for each 1 hour of the minute counter. The assignable range is from 00 through 23 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RHRCNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 0
10 hours -- R/W -- R/W -- R/W
1 hour -- R/W -- R/W -- R/W
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5, 4 3 to 0
10 hours 1 hour
Undefined R/W Undefined R/W
Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position.
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Section 15 Realtime Clock (RTC)
15.3.5
Day of Week Counter (RWKCNT)
RWKCNT is used for setting/counting day of week section. The count operation is performed by a carry for each day of the date counter. The assignable range is from 0 through 6 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RWKCNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day -- R/W -- R/W 0
Bit 7 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
Day
Undefined R/W
Day-of-Week Counting Day-of-week is indicated with a binary code. 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited)
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Section 15 Realtime Clock (RTC)
15.3.6
Date Counter (RDAYCNT)
RDAYCNT is used for setting/counting in the BCD-coded date section. The count operation is performed by a carry for each day of the hour counter. The assignable range is from 01 through 31 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RDAYCNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes. The range of date changes with each month and in leap years. Please confirm the correct setting. Leap years are recognized by dividing the year counter values by 400, 100, and 4 and obtaining a fractional result of 0. The year counter value of 0000 is included in the leap year.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 4 3 2 1 day -- R/W -- R/W -- R/W -- R/W 1 0
10 days -- R/W -- R/W
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5, 4 3 to 0
10 days 1 day
Undefined R/W Undefined R/W
Counting Ten's Position of Dates Counting One's Position of Dates Counts on 0 to 9 once per date. When a carry is generated, 1 is added to the ten's position.
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Section 15 Realtime Clock (RTC)
15.3.7
Month Counter (RMONCNT)
RMONCNT is used for setting/counting in the BCD-coded month section. The count operation is performed by a carry for each month of the date counter. The assignable range is from 01 through 12 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RMONCNT is not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4
10 months
3
2
1
0
1 month -- R/W -- R/W -- R/W -- R/W
-- R/W
Bit 7 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4 3 to 0
10 months 1 month
Undefined R/W Undefined R/W
Counting Ten's Position of Months Counting One's Position of Months Counts on 0 to 9 once per month. When a carry is generated, 1 is added to the ten's position.
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Section 15 Realtime Clock (RTC)
15.3.8
Year Counter (RYRCNT)
RYRCNT is used for setting/counting in the BCD-coded year section. The count operation is performed by a carry for each year of the month counter. The assignable range is from 0000 through 9999 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. RYRCNT is not initialized by a power-on reset or manual reset, in deep standby mode or software standby mode.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000 years Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W
100 years -- R/W -- R/W -- R/W -- R/W
10 years -- R/W -- R/W -- R/W -- R/W
1 year -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value
R/W
Description Counting Thousand's Position of Years Counting Hundred's Position of Years Counting Ten's Position of Years Counting One's Position of Years
15 to 12 1000 years Undefined R/W 11 to 8 7 to 4 3 to 0 100 years 10 years 1 year Undefined R/W Undefined R/W Undefined R/W
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Section 15 Realtime Clock (RTC)
15.3.9
Second Alarm Register (RSECAR)
RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 59 + ENB bits (practically in BCD), otherwise operation errors occur. The ENB bit in RSECAR is initialized to 0 by a power-on reset or in deep standby mode. The other bits are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 -- R/W R/W: R/W 6 5 10 seconds -- R/W -- R/W -- R/W 4 3 2 1 0
1 second -- R/W -- R/W -- R/W
Bit 7 6 to 4 3 to 0
Bit Name ENB 10 seconds 1 second
Initial Value 0
R/W R/W
Description When this bit is set to 1, a comparison with the RSECCNT value is performed. Ten's position of seconds setting value One's position of seconds setting value
Undefined R/W Undefined R/W
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Section 15 Realtime Clock (RTC)
15.3.10 Minute Alarm Register (RMINAR) RMINAR is an alarm register corresponding to the minute counter RMINCNT. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 59 + ENB bits (practically in BCD), otherwise operation errors occur. The ENB bit in RMINAR is initialized by a power-on reset or in deep standby mode. The other bits are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 -- R/W R/W: R/W 6 5 10 minutes -- R/W -- R/W -- R/W 4 3 2 1 0
1 minute -- R/W -- R/W -- R/W
Bit 7 6 to 4 3 to 0
Bit Name ENB 10 minutes 1 minute
Initial Value 0
R/W R/W
Description When this bit is set to 1, a comparison with the RMINCNT value is performed. Ten's position of minutes setting value One's position of minutes setting value
Undefined R/W Undefined R/W
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Section 15 Realtime Clock (RTC)
15.3.11 Hour Alarm Register (RHRAR) RHRAR is an alarm register corresponding to the BCD coded hour counter RHRCNT of the RTC. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 23 + ENB bits (practically in BCD), otherwise operation errors occur. The ENB bit in RHRAR is initialized by a power-on reset or in deep standby mode. The other bits are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 R/W: R/W 6 -- 0 R 5 4 3 2 1 0
10 hours -- R/W -- R/W -- R/W
1 hour -- R/W -- R/W -- R/W
Bit 7 6
Bit Name ENB
Initial Value 0 0
R/W R/W R
Description When this bit is set to 1, a comparison with the RHRCNT value is performed. Reserved This bit is always read as 0. The write value should always be 0.
5, 4 3 to 0
10 hours 1 hour
Undefined R/W Undefined R/W
Ten's position of hours setting value One's position of hours setting value
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Section 15 Realtime Clock (RTC)
15.3.12 Day of Week Alarm Register (RWKAR) RWKAR is an alarm register corresponding to the BCD coded day of week counter RWKCNT. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 0 through 6 + ENB bits (practically in BCD), otherwise operation errors occur. The ENB bit in RWKAR is initialized by a power-on reset or in deep standby mode. The other bits are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 R/W: R/W 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R -- R/W 2 1 Day -- R/W -- R/W 0
Bit 7 6 to 3
Bit Name ENB
Initial Value 0 All 0
R/W R/W R
Description When this bit is set to 1, a comparison with the RWKCNT value is performed. Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
Day
Undefined R/W
Day of week setting value 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited)
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Section 15 Realtime Clock (RTC)
15.3.13 Date Alarm Register (RDAYAR) RDAYAR is an alarm register corresponding to the BCD coded date counter RDAYCNT. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 01 through 31 + ENB bits (practically in BCD), otherwise operation errors occur. The ENB bit in RDAYAR is initialized by a power-on reset or in deep standby mode. The other bits are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 R/W: R/W 6 -- 0 R 5 4 3 2 1 day -- R/W -- R/W -- R/W -- R/W 1 0
10 days -- R/W -- R/W
Bit 7 6
Bit Name ENB
Initial Value 0 0
R/W R/W R
Description When this bit is set to 1, a comparison with the RDAYCNT value is performed. Reserved This bit is always read as 0. The write value should always be 0.
5, 4 3 to 0
10 days 1 day
Undefined R/W Undefined R/W
Ten's position of dates setting value One's position of dates setting value
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Section 15 Realtime Clock (RTC)
15.3.14 Month Alarm Register (RMONAR) RMONAR is an alarm register corresponding to the BCD coded month counter RMONCNT. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 01 through 12 + ENB bits (practically in BCD), otherwise operation errors occur. The ENB bit in RMONAR is initialized by a power-on reset or in deep standby mode. The other bits are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 R/W: R/W 6 -- 0 R 5 -- 0 R 4
10 months
3
2
1
0
1 month -- R/W -- R/W -- R/W -- R/W
-- R/W
Bit 7 6, 5
Bit Name ENB
Initial Value 0 All 0
R/W R/W R
Description When this bit is set to 1, a comparison with the RMONCNT value is performed. Reserved These bits are always read as 0. The write value should always be 0.
4 3 to 0
10 months 1 month
Undefined R/W Undefined R/W
Ten's position of months setting value One's position of months setting value
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Section 15 Realtime Clock (RTC)
15.3.15 Year Alarm Register (RYRAR) RYRAR is an alarm register corresponding to the year counter RYRCNT. The assignable range is from 0000 through 9999 (practically in BCD), otherwise operation errors occur. RYRAR is not initialized by a power-on reset, a manual reset, or in deep standby mode or software standby mode.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000 years Initial value: -- R/W: R/W -- R/W -- R/W -- R/W -- R/W
100 years -- R/W -- R/W -- R/W -- R/W
10 years -- R/W -- R/W -- R/W -- R/W
1 year -- R/W -- R/W -- R/W
Bit
Bit Name
Initial Value
R/W
Description Thousand's position of years setting value Hundred's position of years setting value Ten's position of years setting value One's position of years setting value
15 to 12 1000 years Undefined R/W 11 to 8 7 to 4 3 to 0 100 years 10 years 1 year Undefined R/W Undefined R/W Undefined R/W
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Section 15 Realtime Clock (RTC)
15.3.16 RTC Control Register 1 (RCR1) RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. RCR1 is initialized to H'00 by a power-on reset, a manual reset, or in deep standby mode. The CF flag is retained undefined until the division circuit is reset (the RESET and ADJ bits in RCR2 are set to 1). When using the CF flag, make sure to reset the divider circuit beforehand. This register is not initialized in software standby mode.
Bit: 7 CF Initial value: -- R/W: R/W 6 -- 0 R 5 -- 0 R 4 CIE 0 R/W 3 AIE 0 R/W 2 -- 0 R 1 -- 0 R 0 AF 0 R/W
Bit 7
Bit Name CF
Initial Value
R/W
Description Carry Flag Status flag that indicates that a carry has occurred. CF is set to 1 when a count-up to 64-Hz occurs at the second counter carry or 64-Hz counter read. A count register value read at this time cannot be guaranteed; another read is required. 0: No carry of 64-Hz counter by second counter or 64Hz counter [Clearing condition] * When 0 is written to CF 1: Carry of 64-Hz counter by second counter or 64 Hz counter [Setting condition] * When the second counter or 64-Hz counter is read during a carry occurrence by the 64-Hz counter, or 1 is written to CF.
Undefined R/W
6, 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 15 Realtime Clock (RTC)
Bit 4
Bit Name CIE
Initial Value 0
R/W R/W
Description Carry Interrupt Enable Flag When the carry flag (CF) is set to 1, the CIE bit enables interrupts. 0: A carry interrupt is not generated when the CF flag is set to 1 1: A carry interrupt is generated when the CF flag is set to 1
3
AIE
0
R/W
Alarm Interrupt Enable Flag When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. 0: An alarm interrupt is not generated when the AF flag is set to 1 1: An alarm interrupt is generated when the AF flag is set to 1
2, 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
AF
0
R/W
Alarm Flag The AF flag is set when the alarm time, which is set by an alarm register (ENB bit in RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR is set to 1), and counter match. 0: Alarm register and counter not match [Clearing condition] * When 0 is written to AF. 1: Alarm register and counter match* [Setting condition] * When alarm register (only a register with ENB bit set to 1) and counter match Note: * Writing 1 holds previous value.
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Section 15 Realtime Clock (RTC)
15.3.17 RTC Control Register 2 (RCR2) RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit RESET, and RTC count control. RCR2 is initialized to H'09 by a power-on reset or in deep standby mode. Bits other than the RTCEN and START bits are initialized by a manual reset. It is not initialized in software standby mode, and retains its contents.
Bit: 7
PEF
6
5
PES[2:0]
4
3
RTCEN
2
ADJ
1
0
RESET START
Initial value:
0
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
R/W: R/W
Bit 7
Bit Name PEF
Initial Value 0
R/W R/W
Description Periodic Interrupt Flag Indicates interrupt generation with the period designated by the PES2 to PES0 bits. When set to 1, PEF generates periodic interrupts. 0: Interrupts not generated with the period designated by the bits PES2 to PES0. [Clearing condition] When 0 is written to PEF 1: Interrupts generated with the period designated by the PES2 to PES0 bits. [Setting condition] When an interrupt is generated with the period designated by the bits PES0 to PES2 or when 1 is written to the PEF flag
6 to 4
PES[2:0]
000
R/W
Interrupt Enable Flags These bits specify the periodic interrupt. 000: No periodic interrupts generated 001: Periodic interrupt generated every 1/256 second 010: Periodic interrupt generated every 1/64 second 011: Periodic interrupt generated every 1/16 second 100: Periodic interrupt generated every 1/4 second 101: Periodic interrupt generated every 1/2 second 110: Periodic interrupt generated every 1 second 111: Periodic interrupt generated every 2 seconds
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Section 15 Realtime Clock (RTC)
Bit 3
Bit Name RTCEN
Initial Value 1
R/W R/W
Description Crystal Oscillator Control Controls the operation of the crystal oscillator for the RTC. 0: Halts the crystal oscillator for the RTC. 1: Runs the crystal oscillator for the RTC.
2
ADJ
0
R/W
30-Second Adjustment When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit (RTC prescaler and R64CNT) will be simultaneously reset. This bit always reads 0. Important: When using this bit, see section 15.5.5, Procedure for Setting the 30-Second Adjustment Function. 0: Runs normally. 1: 30-second adjustment.
1
RESET
0
R/W
Reset Writing 1 to this bit initializes the divider circuit. In this case, the RESET bit is automatically reset to 0 after 1 is written to and the divider circuit (RTC prescaler and R64CNT) is reset. Thus, there is no need to write 1 to this bit. This bit is always read as 0. 0: Runs normally. 1: Divider circuit is reset.
0
START
1
R/W
Start Bit Halts and restarts the counter (clock). 0: Second/minute/hour/day/week/month/year counter halts. 1: Second/minute/hour/day/week/month/year counter runs normally. Note: The 64-Hz counter always runs unless stopped with the RTCEN bit.
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Section 15 Realtime Clock (RTC)
15.3.18 RTC Control Register 3 (RCR3) When the ENB bit in RCR3 is set to 1, RCR3 compares the value of RYRCNT and that of RYRAR. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The ENB bit in RCR3 is initialized by a power-on reset or in deep standby mode. Remaining fields of RCR3 are not initialized by a power-on reset or manual reset, or in deep standby and software standby modes.
Bit: 7 ENB Initial value: 0 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
R/W: R/W
Bit 7
Bit Name ENB
Initial Value 0
R/W R/W
Description When this bit is set to 1, comparison of the year alarm register (RYRAR) and the year counter (RYRCNT) is performed. Reserved These bits are always read as 0. The write value should always be 0.
6 to 0
All 0
R
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Section 15 Realtime Clock (RTC)
15.4
Operation
RTC usage is shown below. 15.4.1 Initial Settings of Registers after Power-On
All the registers should be set after the power is turned on. 15.4.2 Setting Time
Figure 15.2 shows how to set the time when the clock is stopped.
Stop clock, reset divider circuit Write 1 to RESET and 0 to START in the RCR2 register
Set seconds, minutes, hour, day, day of the week, month, and year
Order is irrelevant
Start clock
Write 1 to START in the RCR2 register
Figure 15.2 Setting Time
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Section 15 Realtime Clock (RTC)
15.4.3
Reading Time
Figure 15.3 shows how to read the time.
Disable the carry interrupt
Write 0 to CIE in RCR1
Clear the carry flag
Write 0 to CF in RCR1 (Set AF in RCR1 to 1 so that alarm flag is not cleared.)
Read counter register
Yes
Carry flag = 1? No
Read RCR1 and check CF bit
(a) To read the time without using interrupts
Clear the carry flag
Enable the carry interrupt
Write 1 to CIE in RCR1 Write 0 to CF in RCR1 (Set AF in RCR1 to 1 so that alarm flag is not cleared.)
Clear the carry flag
Read counter register
Yes
interrupt No Disable the carry interrupt (b) To read the time using interrupts
Read RCR1 and check CF bit
Write 0 to CIE in RCR1
Figure 15.3 Reading Time If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 15.3 shows the method of reading the time without using interrupts; part (b) in figure 15.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used.
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Section 15 Realtime Clock (RTC)
15.4.4
Alarm Function
Figure 15.4 shows how to use the alarm function.
Clock running
Disable alarm interrupt
Write 0 to AIE in RCR1 to prevent errorneous interrupt
Set alarm time
Clear alarm flag
Always clear, since the flag may have been set while the alarm time was being set.
Enable alarm interrupt
Write 1 to AIE in RCR1
Monitor alarm time (wait for interrupt or check alarm flag)
Figure 15.4 Using Alarm Function Alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. Set the ENB bit in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is not placed to 0. When the clock and alarm times match, 1 is set in the AF bit in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is set in the AIE bit in RCR1, an interrupt is generated when an alarm occurs. The alarm flag is set when the clock and alarm times match. However, the alarm flag can be cleared by writing 0.
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Section 15 Realtime Clock (RTC)
15.5
15.5.1
Usage Notes
Register Writing during RTC Count
Do not write to the count registers (RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, and RYRCNT) during the RTC counting (while the START bit in RCR2 is 1). If any of the count registers is written to during the RTC counting, the count register may not be read correctly immediately after the execution of a write instruction. The RTC counting must be stopped before writing to any of the count registers. 15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts
The method of using the periodic interrupt function is shown in figure 15.5. A periodic interrupt can be generated periodically at the interval set by the flags PES0 to PES2 in RCR2. When the time set by the PES0 to PES2 has elapsed, the PEF is set to 1. The PEF is cleared to 0 upon periodic interrupt generation or when the flags PES0 to PES2 are set. Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used.
Set PES, clear PEF
Set PES0 to PES2, and clear PEF to 0, in RCR2
Elapse of time set by PES
Clear PEF
Clear PEF to 0
Figure 15.5 Using Periodic Interrupt Function
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Section 15 Realtime Clock (RTC)
15.5.3
Transition to Standby Mode after Setting Register
When a transition to standby mode is made after registers in the RTC are set, sometimes counting is not performed correctly. In case the registers are set, be sure to make a transition to standby mode after waiting for two RTC clocks or more. 15.5.4 Crystal Oscillator Circuit for RTC
Crystal oscillator circuit constants (recommended values) for the RTC are shown in table 15.3, and the RTC crystal oscillator circuit in figure 15.6. Table 15.3 Crystal Oscillator Circuit Constants (Recommended Values)
fosc 32.768 kHz Cin 10 to 22 pF Cout 10 to 22 pF
This LSI RTC_X1
Rf RD RTC_X2 XTAL
Cin
Cout
Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. Built-in resistance value Rf (Typ value) = 10 M, RD (Typ value) = 400 k 3. Cin and Cout values include floating capacitance due to the wiring. Take care when using a ground plane. 4. The crystal oscillation stabilization time may differ depending on the mounted circuit component constants, stray capacitance, and so forth, so a suitable value should be determined in consultation with the resonator manufacturer. 5. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. Make wiring length as short as possible. Do not allocate signal lines close to oscillation circuit. (Correct oscillation may not be possible if there is externally induced noise in the RTC_X1 and RTC_X2 pins.) 6. Ensure that the wiring of the crystal oscillator connection pins (RTC_X1 and RTC_X2) is routed as far away as possible from the power lines (except GND) and signal lines. 7. When crystal oscillation circuit for RTC is not used, connect the RTC_X1 pin to GND and leave the RTC_X2 pin open
Figure 15.6 Example of Connecting Crystal Oscillator Circuit for RTC
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Section 15 Realtime Clock (RTC)
15.5.5
Procedure for Setting the 30-Second Adjustment Function
Figure 15.7 shows the procedure for setting the 30-second adjustment function.
Stop clock
Clear the START bit in RCR2 to 0.
Set minutes, hours, date, day of the week, month, and year
The order is irrelevant. For the respective counters, read out each value and then write it back.
Set ADJ bit
Set the ADJ bit in RCR2 to 1.
Start clock
Set the START bit in RCR2 to 1.
Figure 15.7 Procedure for Setting the 30-Second Adjustment Function To use the 30-second adjustment function, the minutes, hours, date, day of the week, month, and year counters need to be written to. Thus, after clearing the START bit in RCR2 and reading out the minutes, hours, date, day of the week, month, and year counters and then writing the read values back, set the ADJ bit in RCR2 to 1. After the 30-second adjustment, set the START bit in RCR2 to 1 to start the clock operation.
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Section 15 Realtime Clock (RTC)
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Section 16 Serial Communication Interface with FIFO (SCIF)
Section 16 Serial Communication Interface with FIFO (SCIF)
This LSI has an eight-channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clocked synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication.
16.1
Features
* Asynchronous serial communication: Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, framing, and overrun errors Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the serial port register when a framing error occurs. * Clocked synchronous serial communication: Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clocked synchronous communication function. There is one serial data communication format. Data length: 8 bits Receive error detection: Overrun errors * Full duplex communication: The transmitting and receiving sections are independent, so the SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external)
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Section 16 Serial Communication Interface with FIFO (SCIF)
* Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. * When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. * The quantity of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be ascertained. * A time-out error (DR) can be detected when receiving in asynchronous mode. Figure 16.1 shows a block diagram of the SCIF.
Module data bus
Peripheral bus
SCFRDR (16 stage)
SCFTDR (16 stage)
SCSMR SCLSR SCFDR SCFCR
SCBRR
RxD
SCRSR
SCTSR
SCFSR SCSCR SCSPTR
Transmission/reception control
Baud rate generator
Bus interface
P P/4 P/16 P/64
TxD
Parity generation Parity check
SCK
Clock External clock
TXI RXI ERI BRI SCIF
[Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register
SCFSR: Serial status register SCBRR: Bit rate register SCSPTR: Serial port register SCFCR: FIFO control register SCFDR: FIFO data count register SCLSR: Line status register
Figure 16.1 Block Diagram of SCIF
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.2
Input/Output Pins
Table 16.1 shows the pin configuration of the SCIF. Table 16.1 Pin Configuration
Channel 0 to 7 Pin Name Serial clock pins Receive data pins Transmit data pins Symbol SCK0 to SCK7 RxD0 to RxD7 TxD0 to TxD7 I/O I/O Input Output Function Clock I/O Receive data input Transmit data output
16.3
Register Descriptions
The SCIF has the following registers. Table 16.2 Register Configuration
Channel 0 Register Name Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit FIFO data register_0 Serial status register_0 Receive FIFO data register_0 FIFO control register_0 FIFO data count register_0 Serial port register_0 Line status register_0 Abbreviation SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 R/W R/W R/W R/W W R/(W)* R R/W R R/W R/(W)*
2 1
Initial Value Address H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'FFFE8000 H'FFFE8004 H'FFFE8008 H'FFFE800C H'FFFE8010 H'FFFE8014 H'FFFE8018 H'FFFE801C H'FFFE8020 H'FFFE8024
Access Size 16 8 16 8 16 8 16 16 16 16
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Section 16 Serial Communication Interface with FIFO (SCIF)
Channel 1
Register Name Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit FIFO data register_1 Serial status register_1 Receive FIFO data register_1 FIFO control register_1 FIFO data count register_1 Serial port register_1 Line status register_1
Abbreviation SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 SCFSR_3 SCFRDR_3 SCFCR_3 SCFDR_3 SCSPTR_3 SCLSR_3
R/W R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* R/W R/W R/W W R/(W)* R R/W R R/W R/(W)*
2 1 2 1 2 1
Initial Value Address H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'FFFE8800 H'FFFE8804 H'FFFE8808 H'FFFE880C H'FFFE8810 H'FFFE8814 H'FFFE8818 H'FFFE881C H'FFFE8820 H'FFFE8824 H'FFFE9000 H'FFFE9004 H'FFFE9008 H'FFFE900C H'FFFE9010 H'FFFE9014 H'FFFE9018 H'FFFE901C H'FFFE9020 H'FFFE9024 H'FFFE9800 H'FFFE9804 H'FFFE9808 H'FFFE980C H'FFFE9810 H'FFFE9814 H'FFFE9818 H'FFFE981C H'FFFE9820 H'FFFE9824
Access Size 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16
2
Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit FIFO data register_2 Serial status register_2 Receive FIFO data register_2 FIFO control register_2 FIFO data count register_2 Serial port register_2 Line status register_2
3
Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit FIFO data register_3 Serial status register_3 Receive FIFO data register_3 FIFO control register_3 FIFO data count register_3 Serial port register_3 Line status register_3
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Section 16 Serial Communication Interface with FIFO (SCIF)
Channel 4
Register Name Serial mode register_4 Bit rate register_4 Serial control register_4 Transmit FIFO data register_4 Serial status register_4 Receive FIFO data register_4 FIFO control register_4 FIFO data count register_4 Serial port register_4 Line status register_4
Abbreviation SCSMR_4 SCBRR_4 SCSCR_4 SCFTDR_4 SCFSR_4 SCFRDR_4 SCFCR_4 SCFDR_4 SCSPTR_4 SCLSR_4 SCSMR_5 SCBRR_5 SCSCR_5 SCFTDR_5 SCFSR_5 SCFRDR_5 SCFCR_5 SCFDR_5 SCSPTR_5 SCLSR_5 SCSMR_6 SCBRR_6 SCSCR_6 SCFTDR_6 SCFSR_6 SCFRDR_6 SCFCR_6 SCFDR_6 SCSPTR_6 SCLSR_6
R/W R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* R/W R/W R/W W R/(W)* R R/W R R/W R/(W)* R/W R/W R/W W R/(W)* R R/W R R/W R/(W)*
2 1 2 1 2 1
Initial Value Address H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'FFFEA000 H'FFFEA004 H'FFFEA008 H'FFFEA00C H'FFFEA010 H'FFFEA014 H'FFFEA018 H'FFFEA01C H'FFFEA020 H'FFFEA024 H'FFFEA800 H'FFFEA804 H'FFFEA808 H'FFFEA80C H'FFFEA810 H'FFFEA814 H'FFFEA818 H'FFFEA81C H'FFFEA820 H'FFFEA824 H'FFFEB000 H'FFFEB004 H'FFFEB008 H'FFFEB00C H'FFFEB010 H'FFFEB014 H'FFFEB018 H'FFFEB01C H'FFFEB020 H'FFFEB024
Access Size 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16
5
Serial mode register_5 Bit rate register_5 Serial control register_5 Transmit FIFO data register_5 Serial status register_5 Receive FIFO data register_5 FIFO control register_5 FIFO data count register_5 Serial port register_5 Line status register_5
6
Serial mode register_6 Bit rate register_6 Serial control register_6 Transmit FIFO data register_6 Serial status register_6 Receive FIFO data register_6 FIFO control register_6 FIFO data count register_6 Serial port register_6 Line status register_6
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Section 16 Serial Communication Interface with FIFO (SCIF)
Channel 7
Register Name Serial mode register_7 Bit rate register_7 Serial control register_7 Transmit FIFO data register_7 Serial status register_7 Receive FIFO data register_7 FIFO control register_7 FIFO data count register_7 Serial port register_7 Line status register_7
Abbreviation SCSMR_7 SCBRR_7 SCSCR_7 SCFTDR_7 SCFSR_7 SCFRDR_7 SCFCR_7 SCFDR_7 SCSPTR_7 SCLSR_7
R/W R/W R/W R/W W R/(W)* R R/W R R/W R/(W)*
2 1
Initial Value Address H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0050 H'0000 H'FFFEB800 H'FFFEB804 H'FFFEB808 H'FFFEB80C H'FFFEB810 H'FFFEB814 H'FFFEB818 H'FFFEB81C H'FFFEB820 H'FFFEB824
Access Size 16 8 16 8 16 8 16 16 16 16
Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that cannot be modified. 2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be modified.
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.1
Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the receive FIFO data register (SCFRDR). The CPU cannot read or write to SCRSR directly.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
16.3.2
Receive FIFO Data Register (SCFRDR)
SCFRDR is a 16-byte FIFO register that stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When SCFRDR is full of receive data, subsequent serial data is lost. SCFRDR is initialized to an undefined value by a power-on reset or in deep standby mode.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-- R
-- R
-- R
-- R
-- R
-- R
-- R
-- R
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.3
Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
16.3.4
Transmit FIFO Data Register (SCFTDR)
SCFTDR is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. SCFTDR is initialized to an undefined value by a power-on reset or in deep standby mode.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-- W
-- W
-- W
-- W
-- W
-- W
-- W
-- W
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.5
Serial Mode Register (SCSMR)
SCSMR specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 3 2 -- 0 R 1 0
O/E STOP 0 R/W 0 R/W
CKS[1:0] 0 R/W 0 R/W
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
C/A
0
R/W
Communication Mode Selects whether the SCIF operates in asynchronous or clocked synchronous mode. 0: Asynchronous mode 1: Clocked synchronous mode
6
CHR
0
R/W
Character Length Selects 7-bit or 8-bit data length in asynchronous mode. In the clocked synchronous mode, the data length is always 8 bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name PE
Initial Value 0
R/W R/W
Description Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clocked synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.
4
O/E
0
R/W
Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clocked synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity* 1: Odd parity*
2 1
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit Name STOP
Initial Value 0
R/W R/W
Description Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clocked synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character.
2
0
R
Reserved This bit is always read as 0. The write value should always be 0.
1, 0
CKS[1:0]
00
R/W
Clock Select Select the internal clock source of the on-chip baud rate generator. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.8, Bit Rate Register (SCBRR). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.6
Serial Control Register (SCSCR)
SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 REIE 0 R/W 2 -- 0 R 1 0
CKE[1:0] 0 R/W 0 R/W
Bit 15 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7
TIE
0
R/W
Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial status register (SCFSR) is set to1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled* Note: * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 6
Bit Name RIE
Initial Value 0
R/W R/W
Description Receive Interrupt Enable Enables or disables the receive FIFO data full interrupts (RXI) requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled 1: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled* Note: * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0.
5
TE
0
R/W
Transmit Enable Enables or disables the SCIF serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit Name RE
Initial Value 0
R/W R/W
Description Receive Enable Enables or disables the SCIF serial receiver. 0: Receiver disabled* 1: Receiver enabled*
1 2
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clocked synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1. 3 REIE 0 R/W Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: * ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. Set so If SCIF wants to inform INTC of ERI or BRI interrupt requests during DMA transfer.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
1, 0
CKE[1:0]
00
R/W
Clock Enable Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of these bits, the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clocked synchronous mode, the C/A bit in SCSMR is set to 1, and then these bits are set. * Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited * Clocked synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7
Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the receive FIFO data register, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is initialized by a power-on reset or in deep standby mode.
Bit: 15 14 13 12 11 10 9 8 7 ER 0 R 6 5 4 3 FER 0 R 2 PER 0 R 1 RDF 0 DR
PER[3:0] Initial value: R/W: Note: 0 R 0 R 0 R 0 R 0 R
FER[3:0] 0 R 0 R
TEND TDFE BRK
0 1 1 0 R/(W)*R/(W)*R/(W)*R/(W)*
0 0 R/(W)*R/(W)*
* Only 0 can be written to clear the flag after 1 is read.
Bit 15 to 12
Bit Name PER[3:0]
Initial Value 0000
R/W R
Description Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). After the ER bit in SCFSR is set, the value indicated by bits 15 to 12 represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER3 to PER0 show 0.
11 to 8
FER[3:0]
0000
R
Number of Framing Errors Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits 11 to 8 represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER3 to FER0 show 0.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 7
Bit Name ER
Initial Value 0
R/W
Description
R/(W)* Receive Error Indicates the occurrence of a framing error, or of a 1 parity error when receiving data that includes parity. * 0: Receiving is in progress or has ended normally [Clearing conditions] * * ER is cleared to 0 a power-on reset ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER
1: A framing error or parity error has occurred. [Setting conditions] * ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive 2 operation*
*
ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCFRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 6
Bit Name TEND
Initial Value 1
R/W
Description
R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition] * TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in 1 SCFTDR*
1: End of transmission [Setting conditions] * * * TEND is set to 1 when the chip is a power-on reset TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR)
TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Note: 1. Do not use this bit as a transmit end flag when the DMAC writes data to SCFTDR due to a TXI interrupt request.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 5
Bit Name TDFE
Initial Value 1
R/W
Description
R/(W)* Transmit FIFO Data Empty Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions] * TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written TDFE is cleared to 0 when the DMAC is activated by the transmit FIFO data empty interrupt (TXI) and writes data exceeding the specified transmission trigger number to SCFTDR
*
1: The quantity of transmit data in SCFTDR is less than or equal to the specified transmission trigger 1 number* [Setting conditions] * * TDFE is set to 1 by a power-on reset TDFE is set to 1 when the quantity of transmit data in SCFTDR becomes less than or equal to the specified transmission trigger number as a result of transmission
Note: 1. Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 4
Bit Name BRK
Initial Value 0
R/W
Description
R/(W)* Break Detection Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions] * * BRK is cleared to 0 when the chip is a power-on reset BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK
1
1: Break signal received* [Setting condition] *
BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data
Note: 1. When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. 3 FER 0 R Framing Error Indication Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions] * * FER is cleared to 0 when the chip undergoes a power-on reset FER is cleared to 0 when no framing error is present in the next data read from SCFRDR
1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition] * FER is set to 1 when a framing error is present in the next data read from SCFRDR
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name PER
Initial Value 0
R/W R
Description Parity Error Indication Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions] * * PER is cleared to 0 when the chip undergoes a power-on reset PER is cleared to 0 when no parity error is present in the next data read from SCFRDR
1: A receive parity error occurred in the next data read from SCFRDR [Setting condition] * PER is set to 1 when a parity error is present in the next data read from SCFRDR
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 1
Bit Name RDF
Initial Value 0
R/W
Description
R/(W)* Receive FIFO Data Full Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR). 0: The quantity of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions] * * RDF is cleared to 0 by a power-on reset, standby mode RDF is cleared to 0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written RDF is cleared to 0 when DMAC read SCFRDR until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number
*
1: The quantity of receive data in SCFRDR is more than the specified receive trigger number [Setting condition] * RDF is set to 1 when a quantity of receive data more than the specified receive trigger number is 1 stored in SCFRDR*
Note: 1. As SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read when RDF is 1 becomes the specified receive trigger number. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 0
Bit Name DR
Initial Value 0
R/W
Description
R/(W)* Receive Data Ready Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clocked synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions] * * * DR is cleared to 0 when the chip undergoes a power-on reset DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written DR is cleared to 0 when all receive data in SCFRDR are read after the DMAC is activated by the receive FIFO data full interrupt (RXI)
1: Next receive data has not been received [Setting condition] * DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the 1 elapse of 15 ETU from the last stop bit. *
Note: 1. This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (ETU: elementary time unit) Note: * Only 0 can be written to clear the flag after 1 is read.
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.8
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset or in deep standby mode. Each channel has independent baud rate generator control, so different values can be set in eight channels.
Bit: 7 6 5 4 3 2 1 0
Initial value:
1
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
R/W: R/W
The SCBRR setting is calculated as follows: * Asynchronous mode:
N= P x 106 - 1 64 x 22n-1 x B
* Clocked synchronous mode:
N= P x 106 - 1 8 x 22n-1 x B
B: N: P: n:
Bit rate (bits/s) SCBRR setting for baud rate generator (0 N 255) (The setting must satisfy the electrical characteristics.) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.)
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.3 SCSMR Settings
SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1
The bit rate error in asynchronous is given by the following formula:
Error (%) = P x 106 -1 (N + 1) x B x 64 x 22n-1 x 100
Table 16.4 lists examples of SCBRR settings in asynchronous mode, and table 16.5 lists examples of SCBRR settings in clocked synchronous mode. Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (1)
P (MHz) 5 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (2)
P (MHz) 8 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (3)
P (MHz) 12.288 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (4)
P (MHz) 20 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 24 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 126 92 186 92 186 92 186 92 46 28 22 28.7 Error (%) 0.31 0.46 -0.08 0.46 -0.08 0.46 -0.08 0.46 -0.61 -1.03 1.55
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode) (5)
P (MHz) 30 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 3 2 2 1 1 0 0 0 0 0 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0.00 -0.54 36 Error n 3 3 2 2 1 1 0 0 0 0 0 N (%) n 3 3 2 2 1 1 0 0 0 0 0 N 168 123 246 123 246 123 246 123 61 37 30 38 Error (%) -0.19 -0.24 0.16 -0.24 0.16 -0.24 0.16 -0.24 -0.24 0.00 -0.24 40 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -1.36
N 132 97 194 97 194 97 194 97 48 29 23
n 3 3 2 2 1 1 0 0 0 0 0
N 145 106 214 106 214 106 214 106 53 32 26
n 3 3 3 2 2 1 1 0 0 0 0
N 177 129 64 129 64 129 64 129 64 39 32
159 -0.12 116 0.16 233 0.16 116 0.16 233 0.16 116 0.16 233 0.16 116 0.16 58 35 28 -0.69 0.00 1.02
Note: Settings with an error of 1% or less are recommended.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.5 Bit Rates and SCBRR Settings (Clocked Synchronous Mode) (1)
P (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2M n -- 3 3 2 1 0 0 0 0 -- 0 -- -- 5 N -- 77 38 77 124 249 124 49 24 -- 4 -- -- n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- --
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.5 Bit Rates and SCBRR Settings (Clocked Synchronous Mode) (2)
P (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2M 33 n -- -- 3 3 2 2 1 1 0 0 0 0 0 -- N -- -- 255 125 200 100 200 80 160 80 31 15 7 -- 36 n -- -- -- 3 2 2 1 1 0 0 0 0 0 -- N -- -- -- 140 224 112 224 89 179 89 35 17 8 -- 38 n -- -- -- 3 2 2 1 1 0 0 0 0 -- -- N -- -- -- 147 237 118 237 94 189 94 37 18 -- -- 40 n -- -- -- 3 2 2 1 1 0 0 0 0 0 -- N -- -- -- 155 249 124 249 99 199 99 39 19 9 --
[Legend] Blank: No setting possible --: Setting possible, but error occurs *: Continuous transmission/reception not possible
Table 16.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 16.7 and 16.8 list the maximum rates when the external clock input is used.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)
Settings P (MHz) 5 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 33 36 38 40 Maximum Bit Rate (bits/s) 156250 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 1031250 1125000 1187500 1250000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
P (MHz) 5 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 33 36 38 40 External Input Clock (MHz) 1.2500 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 8.2500 9.0000 9.5000 10.0000 Maximum Bit Rate (bits/s) 78125 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 515625 562500 593750 625000
Table 16.8 Maximum Bit Rates with External Clock Input (Clocked Synchronous Mode, tScyc = 12 tpcyc)
P (MHz) 5 8 16 24 28.7 30 33 36 38 40 External Input Clock (MHz) 0.4166 0.6666 1.3333 2.0000 2.3916 2.5000 2.7500 3.0000 3.1666 3.3333 Maximum Bit Rate (bits/s) 416666.6 666666.6 1333333.3 2000000.0 2391666.6 2500000.0 2750000.0 3000000.0 3166666.6 3333333.3
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9
FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive data FIFO registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 6 5 4 3 -- 0 R 2 1 0
RTRG[1:0]
TTRG[1:0]
TFRST RFRST LOOP
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
7, 6
RTRG[1:0]
00
R/W
Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register (SCFRDR) is increased more than the set trigger number shown below. * Asynchronous mode * 00: 1 01: 4 10: 8 11: 14 Clocked synchronous mode 00: 1 01: 2 10: 8 11: 14
Note: In clock synchronous mode, to transfer the receive data using DMAC, set the receive trigger number to 1. If a number other than 1 is set, CPU must read the receive data left in SCFRDR.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 5, 4
Bit Name TTRG[1:0]
Initial Value 00
R/W R/W
Description Transmit FIFO Data Trigger Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag is set to 1 when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of empty bytes in SCFTDR when the TDFE flag is set to 1.
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2
TFRST
0
R/W
Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.
1
RFRST
0
R/W
Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 0
Bit Name LOOP
Initial Value 0
R/W R/W
Description Loop-Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled
16.3.10 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is initialized to H'0000 by a power on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 0 R 0 R 12 11 10 T[4:0] 0 R 0 R 0 R 9 8 7 -- 0 R 6 -- 0 R 5 -- 0 R 0 R 0 R 4 3 2 R[4:0] 0 R 0 R 0 R 1 0
Bit 15 to 13
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
12 to 8
T[4:0]
00000
R
T4 to T0 bits indicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. Reserved These bits are always read as 0. The write value should always be 0.
7 to 5
--
All 0
R
4 to 0
R[4:0]
00000
R
R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data.
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.11 Serial Port Register (SCSPTR) SCSPTR controls input/output and data of pins multiplexed to SCIF function. Bits 3 and 2 can control input/output data of SCK pin. Bits 1 and 0 can input data from RxD pin and output data to TxD pin, so they control break of serial transmitting/receiving. The CPU can always read and write to SCSPTR. SCSPTR is initialized to H'0050 by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 1 R 5 -- 0 R 4 -- 1 R 3 2 1 0
SPB2 DT
SCKIO SCKDT SPB2 IO
0 R/W
-- R/W
0 R/W
-- R/W
Bit 15 to 7
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
6
--
1
R
Reserved This bit is always read as 1. The write value should always be 1.
5
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
4
--
1
R
Reserved This bit is always read as 1. The write value should always be 1.
3
SCKIO
0
R/W
SCK Port Input/Output Indicates input or output of the serial port SCK pin. When the SCK pin is actually used as a port outputting the SCKDT bit value, the CKE[1:0] bits in SCSCR should be cleared to 0. 0: SCKDT bit value not output to SCK pin 1: SCKDT bit value output to SCK pin
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Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 2
Bit Name SCKDT
Initial Value
Undefined
R/W R/W
Description SCK Port Data Indicates the input/output data of the serial port SCK pin. Input/output is specified by the SCKIO bit. For output, the SCKDT bit value is output to the SCK pin. The SCK pin status is read from the SCKDT bit regardless of the SCKIO bit setting. However, SCK input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level
1
SPB2IO
0
R/W
Serial Port Break Input/Output Indicates input or output of the serial port TxD pin. When the TxD pin is actually used as a port outputting the SPB2DT bit value, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value not output to TxD pin 1: SPB2DT bit value output to TxD pin
0
SPB2DT
Undefined
R/W
Serial Port Break Data Indicates the input data of the RxD pin and the output data of the TxD pin used as serial ports. Input/output is specified by the SPB2IO bit. When the TxD pin is set to output, the SPB2DT bit value is output to the TxD pin. The RxD pin status is read from the SPB2DT bit regardless of the SPB2IO bit setting. However, RxD input and TxD output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit: 15 -- Initial value: R/W: Note: * 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 ORER 0 R/(W)*
Only 0 can be written to clear the flag after 1 is read.
Bit 15 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
0
ORER
0
R/(W)* Overrun Error Indicates the occurrence of an overrun error. 1 0: Receiving is in progress or has ended normally* [Clearing conditions] * ORER is cleared to 0 when the chip is a power-on reset * ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1: An overrun error has occurred*2 [Setting condition] * ORER is set to 1 when the next serial receiving is finished while the receive FIFO is full of 16-byte receive data. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) retains the data before an overrun error has occurred, and the next received data is discarded. When the ORER bit is set to 1, the SCIF cannot continue the next serial reception.
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.4
16.4.1
Operation
Overview
For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a clocked synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead of the CPU, and enabling continuous high-speed communication. The transmission format is selected in the serial mode register (SCSMR), as shown in table 16.9. The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.10. (1) Asynchronous Mode
* Data length is selectable: 7 or 8 bits * Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks. * The number of stored data bytes is indicated for both the transmit and receive FIFO registers. * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the on-chip baud rate generator. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clocked Synchronous Mode
* The transmission/reception format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCIF operates on the input serial clock. The onchip baud rate generator is not used.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.9 SCSMR Settings and SCIF Communication Formats
SCSMR Settings Bit 7 Bit 6 Bit 5 Bit 3 C/A CHR PE STOP Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 x x x Clocked synchronous 8 bits Not set Set 7 bits Not set Set Asynchronous SCIF Communication Format Data Length 8 bits Parity Bit Not set Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None
[Legend] x: Don't care
Table 16.10 SCSMR and SCSCR Settings and SCIF Clock Source Selection
SCSMR Bit 7 C/A 0 SCSCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 1 [Legend] x: Don't care x 0 1 Clocked synchronous External Mode Asynchronous Clock Source Internal SCIF Transmit/Receive Clock SCK Pin Function SCIF does not use the SCK pin Outputs a clock with a frequency 16 times the bit rate Inputs a clock with frequency 16 times the bit rate
Setting prohibited Internal External Outputs the serial clock Inputs the serial clock
Setting prohibited
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.4.2
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit.
Idle state (mark state) 1 Serial data 0 Start bit 1 bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 Parity bit 1 bit or none 1 Stop bit 1 1
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 16.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)
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Section 16 Serial Communication Interface with FIFO (SCIF)
(1)
Transmit/Receive Formats
Table 16.11 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 16.11 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits CHR 0 0 0 0 1 1 1 1 PE STOP 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 START START START START START START START START 2 Serial Transmit/Receive Format and Frame Length 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data
[Legend] START: Start bit STOP: Stop bit P: Parity bit
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Section 16 Serial Communication Interface with FIFO (SCIF)
(2)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR). For clock source selection, refer to table 16.10. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal on the SCK pin. The frequency of this output clock is 16 times the desired bit rate. (3) Transmitting and Receiving Data
* SCIF Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.3 shows a sample flowchart for initializing the SCIF.
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 After reading ER, DR, and BRK flags in SCFSR, and each flag in SCLSR, write 0 to clear them Set CKE[1:0] bits in SCSCR (leaving TIE, RIE, TE, and RE bits cleared to 0) [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [1] [4] Sets PFC for external pins used. Set as RxD input at reciving and TxD at transmission. However, no setting for SCK pin is required when CKE[1:0] is 00. [5] Set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. When the intrnal clock output is selected, a clock starts to be output from the SCK pin at this point.
Set data transfer format in SCSMR
[2] [3]
Set value in SCBRR Set RTRG[1:0], TTRG[1:0], and MCE bits in SCFCR, and clear TFRST and RFRST bits to 0 PFC setting for external pins used SCK, TxD, RxD
[4]
Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization
[5]
Figure 16.3 Sample Flowchart for SCIF Initialization
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Section 16 Serial Communication Interface with FIFO (SCIF)
* Transmitting Serial Data (Asynchronous Mode) Figure 16.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear to 0. The quantity of transmit data that can be written is 16 - (transmit trigger set number). [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output during serial transmission: To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0.
Read TDFE flag in SCFSR No
TDFE = 1? Yes Write transmit data in SCFTDR, and read 1 from TDFE flag and TEND flag in SCFSR, then clear to 0
[1]
All data transmitted? Yes Read TEND flag in SCFSR
No
[2]
TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1
No
No In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR.
[3]
Clear TE bit in SCSCR to 0 End of transmission
Figure 16.4 Sample Flowchart for Transmitting Serial Data
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Section 16 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. Figure 16.5 shows an example of the operation for transmission.
Start 1 bit Serial data 0 D0 D1 Parity Stop bit bit D7 0/1 1 Start bit 0 D0 D1 Parity Stop Data bit bit D7 0/1 1
Data
1 Idle state (mark state)
TDFE TEND
TXI interrupt request Data written to SCFTDR and TDFE TXI interrupt flag read as 1 then cleared to 0 by request TXI interrupt handler One frame
Figure 16.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit)
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Section 16 Serial Communication Interface with FIFO (SCIF)
* Receiving Serial Data (Asynchronous Mode) Figures 16.6 and 16.7 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
Start of reception
Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR
[1]
[1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure:
ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No
Yes
Error handling [2]
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR. [3]
No
All data received? Yes Clear RE bit in SCSCR to 0 End of reception
Figure 16.6 Sample Flowchart for Receiving Serial Data
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Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling No ORER = 1? Yes Overrun error handling
* Whether a framing error or parity error has occurred in the receive data that is to be read from the receive FIFO data register (SCFRDR) can be ascertained from the FER and PER bits in the serial status register (SCFSR). * When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored.
No ER = 1? Yes Receive error handling
No BRK = 1? Yes Break handling
No DR = 1? Yes Read receive data in SCFRDR
Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0
End
Figure 16.7 Sample Flowchart for Receiving Serial Data (cont)
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Section 16 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing error occurs, reception is not suspended. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 16.8 shows an example of the operation for reception.
Start bit 0 D0 D1 Data Parity bit D7 0/1 Stop Start bit bit 1 0 D0 D1 Data Parity Stop bit bit D7 0/1
1 Serial data
1
1 Idle state (mark state)
RDF
FER One frame
RXI interrupt request Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler
ERI interrupt request generated by receive error
Figure 16.8 Example of SCIF Receive Operation (8-Bit Data, Parity, 1 Stop Bit)
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.4.3
Operation in Clocked Synchronous Mode
In clocked synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCIF transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 16.9 shows the general format in clocked synchronous serial communication.
One unit of transfer data (character or frame) * Serial clock LSB Serial data
Don't care
*
MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Don't care
Bit 0
Note: * High except in continuous transfer
Figure 16.9 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clocked synchronous mode, the SCIF receives data by synchronizing with the rising edge of the serial clock.
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Section 16 Serial Communication Interface with FIFO (SCIF)
(1)
Transmit/Receive Formats
The data length is fixed at eight bits. No parity bit can be added. (2) Clock
An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCIF is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive FIFO data trigger number. (3) Transmitting and Receiving Data
* SCIF Initialization (Clocked Synchronous Mode) Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents.
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Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.10 shows a sample flowchart for initializing the SCIF.
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading ER, DR, and BRK flags in SCFSR, write 0 to clear them Set data transfer format in SCSMR Set CKE[1:0] bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set value in SCBRR Set RTRG[1:0] and TTRG[1:0] bits in SCFCR, and clear TFRST and RFRST bits to 0 PFC setting for external pins used SCK, TxD, RxD [2] [1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. [2] Set the data transfer format in SCSMR. [3] Set the CKE1 and CKE0 bits. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. [5] Sets PFC for external pins used. Set as RxD input at reciving and TxD at transmission. [6] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE, and REIE bits to enable the TxD, RxD, and SCK pins to be used. When transmitting, the TxD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCK pin at this point.
[1]
[3]
[4]
[5]
Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits End of initialization
[6]
Figure 16.10 Sample Flowchart for SCIF Initialization
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Section 16 Serial Communication Interface with FIFO (SCIF)
* Transmitting Serial Data (Clocked Synchronous Mode) Figure 16.11 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission
Read TDFE flag in SCFSR No
[1]
SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear these flags to 0.
TDFE = 1? Yes Write transmit data to SCFTDR and read 1 from TDFE and TEND flags in SCFSR, then clear these flags to 0
[2] [1]
Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0.
All data transmitted? Yes Read TEND flag in SCFSR
No
[2]
TEND = 1? Yes Clear TE bit in SCSCR to 0 End of transmission
No
Figure 16.11 Sample Flowchart for Transmitting Serial Data
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Section 16 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCIF outputs eight synchronous clock pulses. If an external clock source is selected, the SCIF outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCIF checks the SCFTDR transmit data at the timing for sending the MSB (bit 7). If data is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the next frame is started. If there is no data, the TxD pin holds the state after the TEND flag in SCFSR is set to 1 and the MSB (bit 7) is sent. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 16.12 shows an example of SCIF transmit operation.
Serial clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDFE
TEND
TXI interrupt request Data written to SCFTDR TXI and TDFE flag cleared interrupt to 0 by TXI interrupt request handler
One frame
Figure 16.12 Example of SCIF Transmit Operation
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Section 16 Serial Communication Interface with FIFO (SCIF)
* Receiving Serial Data (Clocked Synchronous Mode) Figures 16.13 and 16.14 show sample flowcharts for receiving serial data. When switching from asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared to 0.
Start of reception Read ORER flag in SCLSR
ORER = 1? No Read RDF flag in SCFSR No
Yes [1] Error handling [2]
[1] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1.
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [3]
[2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt.
No
All data received? Yes Clear RE bit in SCSCR to 0 End of reception
[3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR. However, the RDF bit is cleared to 0 automatically when an RXI interrupt activates the DMAC to read the data in SCFRDR.
Figure 16.13 Sample Flowchart for Receiving Serial Data (1)
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Section 16 Serial Communication Interface with FIFO (SCIF)
Error handling No
ORER = 1? Yes Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 16.14 Sample Flowchart for Receiving Serial Data (2) In serial reception, the SCIF operates as described below. 1. The SCIF synchronizes with serial clock input or output and starts the reception. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If the check is not passed (overrun error is detected), further reception is prevented. 3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI). Figure 16.15 shows an example of SCIF receive operation.
Serial clock LSB Serial data RDF ORER
Data read from SCFRDR and RXI interrupt RDF flag cleared to 0 by RXI request interrupt handler
MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Bit 7
Bit 0
RXI interrupt request
BRI interrupt request by overrun error
One frame
Figure 16.15 Example of SCIF Receive Operation
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Section 16 Serial Communication Interface with FIFO (SCIF)
* Transmitting and Receiving Serial Data Simultaneously (Clocked Synchronous Mode) Figure 16.16 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling the SCIF for transmission/reception.
[1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear these flags to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [3] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0.
Initialization
Start of transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1? Yes Write transmit data to SCFTDR, and read 1 from TDFE and TEND flags in SCFTDR, then clear these flags to 0
[1]
Read ORER flag in SCLSR Yes [2] No Read RDF flag in SCFSR Error handling
ORER = 1?
No
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
[3]
No
All data received? Yes Clear TE and RE bits in SCSCR to 0 [4] When switching from a transmit operation Note: or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1.
End of transmission and reception
Figure 16.16 Sample Flowchart for Transmitting/Receiving Serial Data
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.5
SCIF Interrupts
The SCIF has four interrupt sources: transmit FIFO data empty (TXI), receive error (ERI), receive FIFO data full (RXI), and break (BRI). Table 16.12 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the CPU. When an RXI request is enabled by the RIE bit, and the RDF flag or the DR flag in SCFSR is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU. The RXI interrupt request caused by the DR flag is generated only in asynchronous mode. When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt without requesting an RXI interrupt. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR. Table 16.12 SCIF Interrupt Sources
Interrupt Source BRI ERI RXI TXI Description Interrupt initiated by break (BRK) or overrun error (ORER) Interrupt initiated by receive error (ER) DMAC Activation Not possible Not possible Priority on Reset Release High
Interrupt initiated by receive FIFO data full (RDF) or Possible data ready (DR) Interrupt initiated by transmit FIFO data empty (TDFE) Possible Low
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.6
Usage Notes
Note the following when using the SCIF. 16.6.1 SCFTDR Writing and TDFE Flag
The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). 16.6.2 SCFRDR Reading and RDF Flag
The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after reading the number of the received data in the receive FIFO data register (SCFRDR) which is less than the trigger number. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR).
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.6.3
Restriction on DMAC Usage
1. When the DMAC writes data to SCFTDR with a TXI interrupt request, the state of the TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag in such a case. 2. When one channel is used in full duplex communication with the DMAC used for transmission and the CPU used for reception, if the receive data are read from the receive FIFO data register (SCFRDR) after the RDF or DR flag in the serial status register (SCFSR) has been set, the RDF or DR flag may be cleared. 3. When one channel is used in full duplex communication with the DMAC used for reception and the CPU used for transmission, if the transmit data is written to the transmit FIFO data register (SCFTDR) after the TDFE or TEND flag in the serial status register (SCFSR) has been set, the TDFE or TEND flags may be cleared. 16.6.4 Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate. 16.6.5 Sending a Break Signal
The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work. During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and SPB2DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin.
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Section 16 Serial Communication Interface with FIFO (SCIF)
16.6.6
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.17.
16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1
Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1:
M = (0.5 D - 0.5 1 ) - (L - 0.5) F (1 + F) x 100 % 2N N
Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2:
When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
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Section 17 I C Bus Interface 3 (IIC3)
2
Section 17 I2C Bus Interface 3 (IIC3)
The I2C bus interface 3 conforms to and provides a subset of the Philips I2C (Inter-IC) bus interface functions. However, the configuration of the registers that control the I2C bus differs partly from the Philips register configuration.
17.1
Features
* Selection of I2C format or clocked synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C bus format: * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * The direct memory access controller (DMAC) can be activated by a transmit-data-empty request or receive-data-full request to transfer data. * Direct bus drive Two pins, SCL0 to SCL2 and SDA0 to SDA2, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous serial format: * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error * The direct memory access controller (DMAC) can be activated by a transmit-data-empty request or receive-data-full request to transfer data.
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Section 17 I C Bus Interface 3 (IIC3)
2
Figure 17.1 shows a block diagram of the I2C bus interface 3.
Transfer clock generation circuit
SCL
Output control
Transmission/ reception control circuit
ICCR1 ICCR2 ICMR
Noise filter
ICDRT
SDA
Output control
ICDRS
SAR
Noise filter
Address comparator
ICDRR
NF2CYC
Bus state decision circuit Arbitration decision circuit [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: NF2CYC:
ICIER
ICSR
I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register NF2CYC register
Interrupt generator
Figure 17.1 Block Diagram of I2C Bus Interface 3
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Peripheral bus
Interrupt request
Section 17 I C Bus Interface 3 (IIC3)
2
17.2
Input/Output Pins
Table 17.1 shows the pin configuration of the I2C bus interface 3. Specifications for the voltage applied to I/O pins for the I2C bus interface are different from others because of the pin configuration difference. For details, see section 31, Electrical Characteristics. Table 17.1 Pin Configuration
Channel 0 to 2 Pin Name Serial clock Serial data Symbol SCL0 to SCL2 SDA0 to SDA2 I/O I/O I/O Function I2C serial clock input/output I C serial data input/output
2
Figure 17.2 shows an example of I/O pin connections to external circuits. Specifications for the voltage applied to I/O pins for the I2C bus interface are different from others because of the pin configuration difference. For details, see section 31, Electrical Characteristics.
I2C bus power supply*
SCL in SCL out
SCL
SCL
SDA in SDA out
SDA
SDA
SCL SDA
(Master)
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
SDA in SDA out (Slave 2)
Note: * Turn on/off PVcc for the I2C bus power supply and for this LSI simultaneously.
Figure 17.2 External Circuit Connections of I/O Pins
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SCL SDA
Section 17 I C Bus Interface 3 (IIC3)
2
17.3
Register Descriptions
The I2C bus interface 3 has the following registers. Table 17.2 Register Configuration
Channel 0 Register Name I2C bus control register 1 I C bus control register 2 I2C bus mode register I2C bus interrupt enable register I C bus status register Slave address register I2C bus transmit data register I2C bus receive data register NF2CYC register 1 I C bus control register 1 I2C bus control register 2 I C bus mode register I C bus interrupt enable register I2C bus status register Slave address register I2C bus transmit data register I C bus receive data register NF2CYC register 2 I2C bus control register 1 I2C bus control register 2 I C bus mode register I2C bus interrupt enable register I2C bus status register Slave address register I2C bus transmit data register I C bus receive data register NF2CYC register
2 2 2 2 2 2 2 2
Abbreviation R/W ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value H'00 H'7D H'38 H'00 H'00 H'00 H'FF H'FF H'02 H'00 H'7D H'38 H'00 H'00 H'00 H'FF H'FF H'02 H'00 H'7D H'38 H'00 H'00 H'00 H'FF H'FF H'02
Address H'FFFEE000 H'FFFEE001 H'FFFEE002 H'FFFEE003 H'FFFEE004 H'FFFEE005 H'FFFEE006 H'FFFEE007 H'FFFEE008 H'FFFEE080 H'FFFEE081 H'FFFEE082 H'FFFEE083 H'FFFEE084 H'FFFEE085 H'FFFEE086 H'FFFEE087 H'FFFEE088 H'FFFEE100 H'FFFEE101 H'FFFEE102 H'FFFEE103 H'FFFEE104 H'FFFEE105 H'FFFEE106 H'FFFEE107 H'FFFEE108
Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
NF2CYC R/W
NF2CYC R/W
NF2CYC R/W
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Section 17 I C Bus Interface 3 (IIC3)
2
17.3.1
I2C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I2C bus interface 3, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. ICCR1 is initialized to H'00 by a power-on reset or deep standby mode.
Bit: 7 6 5 4 TRS 0 R/W 0 R/W 3 2 1 0
ICE RCVD MST Initial value: 0 0 R/W 0 R/W R/W: R/W
CKS[3:0] 0 R/W 0 R/W 0 R/W
Bit 7
Bit Name ICE
Initial Value 0
R/W R/W
Description I C Bus Interface 3 Enable 0: This module is halted. 1: This bit is enabled for transfer operations.
2
6
RCVD
0
R/W
Reception Disable Enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 5 4
Bit Name MST TRS
Initial Value 0 0
R/W R/W R/W
Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. When seven bits after the start condition is issued in slave receive mode match the slave address set to SAR and the 8th bit is set to 1, TRS is automatically set to 1. If an overrun error occurs in master receive mode with the clocked synchronous serial format, MST is cleared and the mode changes to slave receive mode. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST = 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode
2
3 to 0
CKS[3:0]
0000
R/W
Transfer Clock Select These bits should be set according to the necessary transfer rate (table 17.3) in master mode.
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Section 17 I C Bus Interface 3 (IIC3)
2
Table 17.3 Transfer Rate
Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate P = P = P = P = P = P = 16.7 MHz 20.0 MHz 25.0 MHz 30.0 MHz 33.3 MHz 40 MHz 595 kHz 417 kHz 347 kHz 260 kHz 208 kHz 167 kHz 149 kHz 130 kHz 149 kHz 104 kHz 86.8 kHz 65.1 kHz 52.1 kHz 41.7 kHz 37.2 kHz 32.6 kHz 714 kHz 500 kHz 417 kHz 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 893 kHz 625 kHz 521 kHz 391 kHz 313 kHz 250 kHz 223 kHz 195 kHz 223 kHz 156 kHz 130 kHz 97.7 kHz 78.1 kHz 62.5 kHz 55.8 kHz 48.8 kHz 1071 kHz 1189 kHz 1430 kHz 750 kHz 625 kHz 469 kHz 375 kHz 300 kHz 268 kHz 234 kHz 268 kHz 188 kHz 156 kHz 117 kHz 93.8 kHz 75.0 kHz 67.0 kHz 58.6 kHz 833 kHz 694 kHz 520 kHz 416 kHz 333 kHz 297 kHz 260 kHz 297 kHz 208 kHz 173 kHz 130 kHz 104 kHz 83.3 kHz 74.3 kHz 65.0 kHz 1000 kHz 833 kHz 625 kHz 500 kHz 400 kHz 357 kHz 313 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz
CKS3 CKS2 CKS1 CKS0 Clock 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 P/28 P/40 P/48 P/64 P/80 P/100 P/112 P/128 P/112 P/160 P/192 P/256 P/320 P/400 P/448 P/512
Note: The settings should satisfy external specifications.
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Section 17 I C Bus Interface 3 (IIC3)
2
17.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus. ICCR2 is initialized to H'7D by a power-on reset or deep standby mode.
Bit: 7
BBSY
6
SCP
5
4
3
2 -- 1 R
1
IICRST
0 -- 1 R
SDAO SDAOP SCLO
Initial value:
0
1 R/W
1 R/W
1 R/W
1 R
0 R/W
R/W: R/W
Bit 7
Bit Name BBSY
Initial Value 0
R/W R/W
Description Bus Busy Enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial format, this 2 bit is always read as 0. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition.
2
6
SCP
1
R/W
Start/Stop Issue Condition Disable Controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. Even if 1 is written to this bit, the data will not be stored.
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 5
Bit Name SDAO
Initial Value 1
R/W R/W
Description SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance).
4
SDAOP
1
R/W
SDAO Write Protect Controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0. This bit is always read as 1.
3
SCLO
1
R
SCL Output Level Monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
2
1
R
Reserved This bit is always read as 1. The write value should always be 1.
1
IICRST
0
R/W
IIC Control Part Reset Resets the control part except for I C registers. If this bit is set to 1 when hang-up occurs because of communication failure during I2C bus operation, some IIC3 registers and the control part can be reset.
2
0
1
R
Reserved This bit is always read as 1. The write value should always be 1.
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Section 17 I C Bus Interface 3 (IIC3)
2
17.3.3
I2C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. ICMR is initialized to H'38 by a power-on reset or deep standby mode. Bits BC[2:0] are initialized to H'0 by the IICRST bit in ICCR2.
Bit: 7 6 5 -- 1 R 4 -- 1 R 3
BCWP
2
1 BC[2:0]
0
MLS WAIT Initial value: 0 0 R/W R/W: R/W
1 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name MLS
Initial Value 0
R/W R/W
Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used.
2
6
WAIT
0
R/W
Wait Insertion In master mode with the I C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the I2C bus format or with the clocked synchronous serial format.
2
5, 4
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 3
Bit Name BCWP
Initial Value 1
R/W R/W
Description BC Write Protect Controls the BC[2:0] modifications. When modifying the BC[2:0] bits, this bit should be cleared to 0. In clocked synchronous serial mode, the BC[2:0] bits should not be modified. 0: When writing, values of the BC[2:0] bits are set. 1: When reading, 1 is always read. When writing, settings of the BC[2:0] bits are invalid.
2 to 0
BC[2:0]
000
R/W
Bit Counter These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Should be made between transfer frames. If these bits are set to a value other than B'000, the setting should be made while the SCL pin is low. The value returns to B'000 at the end of a data transfer, including the acknowledge bit. These bits are cleared by a power-on reset, in deep standby mode, software standby mode, or module standby mode. These bits are also cleared by setting the IICRST bit of ICCR2 to 1. With the clocked synchronous serial format, these bits should not be modified. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits
2
Clocked Synchronous Serial Format 000: 8 bits 001: 1 bit 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits
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Section 17 I C Bus Interface 3 (IIC3)
2
17.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits received. ICIER is initialized to H'00 by a power-on reset or deep standby mode.
Bit: 7
TIE
6
TEIE
5
RIE
4
NAKIE
3
STIE
2
1
0
ACKE ACKBR ACKBT
Initial value:
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
R/W: R/W
Bit 7
Bit Name TIE
Initial Value 0
R/W R/W
Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1 or 0, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled.
6
TEIE
0
R/W
Transmit End Interrupt Enable Enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled.
5
RIE
0
R/W
Receive Interrupt Enable Enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) in the clocked synchronous format when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) are disabled. 1: Receive data full interrupt request (RXI) are enabled.
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 4
Bit Name NAKIE
Initial Value 0
R/W R/W
Description NACK Receive Interrupt Enable Enables or disables the NACK detection interrupt request (NAKI) and the overrun error (OVE set in ICSR) interrupt request (ERI) in the clocked synchronous format when the NACKF or AL/OVE bit in ICSR is set. NAKI can be canceled by clearing the NACKF, AL/OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable Enables or disables the stop condition detection interrupt request (STPI) when the STOP bit in ICSR is set. 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. This bit can be canceled by setting the BBSY bit in ICCR2 to 1. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
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Section 17 I C Bus Interface 3 (IIC3)
2
17.3.5
I2C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status. ICSR is initialized to H'00 by a power-on reset or deep standby mode.
Bit: 7 6 5 4 3 2 1 0
ADZ
TDRE TEND RDRF NACKF STOP AL/OVE AAS
Initial value:
0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name TDRE
Initial Value 0
R/W R/W
Description Transmit Data Register Empty [Clearing conditions] * * * * * * When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When the start condition (including retransmission) is issued When slave mode is changed from receive mode to transmit mode
[Setting conditions]
6
TEND
0
R/W
Transmit End [Clearing conditions] * * * * When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clocked synchronous serial format
2
[Setting conditions]
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 5
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full [Clearing conditions] * * * When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read When a receive data is transferred from ICDRS to ICDRR
[Setting condition]
4
NACKF
0
R/W
No Acknowledge Detection Flag [Clearing condition] * When 0 is written in NACKF after reading NACKF =1 When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1
[Setting condition] *
3
STOP
0
R/W
Stop Condition Detection Flag [Clearing condition] * * * When 0 is written in STOP after reading STOP = 1 In master mode, when a stop condition is detected after frame transfer In slave mode, when the slave address in the first byte, after detecting start condition, matches the address set in SAR, and then the stop condition is detected [Setting conditions]
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 2
Bit Name AL/OVE
Initial Value 0
R/W R/W
Description Arbitration Lost Flag/Overrun Error Flag Indicates that arbitration was lost in master mode with 2 the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface 3 detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been occupied by another master. [Clearing condition] * When 0 is written in AL/OVE after reading AL/OVE =1 If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clocked synchronous format while RDRF = 1
[Setting conditions] * * * 1 AAS 0 R/W
Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA[6:0] in SAR. [Clearing condition] * * * When 0 is written in AAS after reading AAS = 1 When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. [Setting conditions]
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Section 17 I C Bus Interface 3 (IIC3)
2
Bit 0
Bit Name ADZ
Initial Value 0
R/W R/W
Description General Call Address Recognition Flag This bit is valid in slave receive mode with the I C bus format. [Clearing condition] * * When 0 is written in ADZ after reading ADZ = 1 When the general call address is detected in slave receive mode [Setting condition]
2
17.3.6
Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the slave address. In slave mode with the I2C bus format, if the upper seven bits of SAR match the upper seven bits of the first frame received after a start condition, this module operates as the slave device. SAR is initialized to H'00 by a power-on reset or deep standby mode.
Bit: 7 6 5 4 SVA[6:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 FS 0 R/W
Bit 7 to 1
Bit Name SVA[6:0]
Initial Value 0000000
R/W R/W
Description Slave Address These bits set a unique address in these bits, differing form the addresses of other slave devices 2 connected to the I C bus.
0
FS
0
R/W
Format Select 0: I C bus format is selected 1: Clocked synchronous serial format is selected
2
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Section 17 I C Bus Interface 3 (IIC3)
2
17.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the empty space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF. ICDRT is initialized to H'FF by a power-on reset or deep standby mode.
Bit: 7 6 5 4 3 2 1 0
Initial value:
1
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
R/W: R/W
17.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. ICDRR is initialized to H'FF by a power-on reset or deep standby mode.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
1 R
1 R
1 R
1 R
1 R
1 R
1 R
1 R
17.3.9
I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- --
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Section 17 I C Bus Interface 3 (IIC3)
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17.3.10 NF2CYC Register (NF2CYC) NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the SCL and SDA pins. For details of the noise filter, see section 17.4.7, Noise Filter. NF2CYC is initialized to H'02 by a power-on reset or in deep standby mode.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 1 R 0
NF2 CYC
0 R/W
Bit 7 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
1
R
Reserved This bit is always read as 0. The write value should always be 1.
0
NF2CYC
0
R/W
Noise Filtering Range Select 0: The noise less than one cycle of the peripheral clock can be filtered out 1: The noise less than two cycles of the peripheral clock can be filtered out
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Section 17 I C Bus Interface 3 (IIC3)
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17.4
Operation
The I2C bus interface 3 can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 17.4.1 I2C Bus Format
Figure 17.3 shows the I2C bus formats. Figure 17.4 shows the I2C bus timing. The first frame following a start condition always consists of eight bits.
(a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 17.3 I2C Bus Formats
SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P
Figure 17.4 I2C Bus Timing
[Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high.
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Section 17 I C Bus Interface 3 (IIC3)
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17.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 17.5 and 17.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the WAIT bit in ICMR and bits CKS[3:0] in ICCR1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 17 I C Bus Interface 3 (IIC3)
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SCL (Master output) SDA (Master output)
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0 R/W
9
1 Bit 7
2 Bit 6
Slave address SDA (Slave output) TDRE
A
TEND
ICDRT
Address + R/W
Data 1
Data 2
ICDRS
Address + R/W
Data 1
User [2] Instruction of start processing condition issuance
[4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 17.5 Master Transmit Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
A/A
TEND
ICDRT
Data n
ICDRS
Data n
User [5] Write data to ICDRT processing
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 17.6 Master Transmit Mode Operation Timing (2)
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Section 17 I C Bus Interface 3 (IIC3)
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17.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 17.7 and 17.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started*, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Note: * If only one byte is received, read ICDRR (dummy-read) after the RCVD bit in ICCR1 is set.
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Section 17 I C Bus Interface 3 (IIC3)
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Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A 9 1
Master receive mode 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR User processing
Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read)
Figure 17.7 Master Receive Mode Operation Timing (1)
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SCL (Master output) SDA (Master output) SDA (Slave output) RDRF
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCVD
ICDRS
Data n-1
Data n
ICDRR User processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[6] Issue stop condition
[7] Read ICDRR, and clear RCVD
[8] Set slave receive mode
Figure 17.8 Master Receive Mode Operation Timing (2) 17.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 17.9 and 17.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened. 5. Clear TDRE.
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Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE A 9
Slave transmit mode 1 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
ICDRT
Data 1
Data 2
Data 3
ICDRS
Data 1
Data 2
ICDRR User processing [2] Write data to ICDRT (data 3)
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
Figure 17.9 Slave Transmit Mode Operation Timing (1)
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Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
TDRE 9 A 1 2 3 4 5 6 7 8 9 A
Slave receive mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TEND TRS
ICDRT
ICDRS
Data n
ICDRR
User processing
[3] Clear TEND
[4] Read ICDRR (dummy read) after clearing TRS
[5] Clear TDRE
Figure 17.10 Slave Transmit Mode Operation Timing (2)
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Section 17 I C Bus Interface 3 (IIC3)
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17.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 17.11 and 17.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
1
Bit 7
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
Data 1
User processing
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 17.11 Slave Receive Mode Operation Timing (1)
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Section 17 I C Bus Interface 3 (IIC3)
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SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
Data 1
User processing
[3] Set ACKBT
[3] Read ICDRR
[4] Read ICDRR
Figure 17.12 Slave Receive Mode Operation Timing (2) 17.4.6 Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format
Figure 17.13 shows the clocked synchronous serial transfer format. The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2.
SCL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SDA
Figure 17.13 Clocked Synchronous Serial Transfer Format
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Section 17 I C Bus Interface 3 (IIC3)
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(2)
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1.
SCL SDA (Output) TRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
Bit 0
Bit 1
TDRE
ICDRT ICDRS
Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
User processing
[3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS
[3] Write data to ICDRT
[3] Write data to ICDRT
Figure 17.14 Transmit Mode Operation Timing
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Section 17 I C Bus Interface 3 (IIC3)
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(3)
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 17.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data. Notes: Follow the steps below to receive only one byte with MST = 1 specified. See figure 17.16 for the operation timing. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be output. 3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1. This causes the SCL to be fixed to the high level after outputting one byte of the receive clock.
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Section 17 I C Bus Interface 3 (IIC3)
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SCL SDA (Input) MST TRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
2 Bit 1
Bit 0
Bit 1
RDRF ICDRS ICDRR Data 1 Data 2 Data 1 [2] Set MST (when outputting the clock) Data 3
Data 2
User processing
[3] Read ICDRR
[3] Read ICDRR
Figure 17.15 Receive Mode Operation Timing
SCL SDA (Input) MST RCVD BC2 to BC0 000
1
2
3
4
5
6
7
8
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
111
110
101
100
011
010
001
000
[2] Set MST
[3] Set the RCVD bit after checking if BC2 = 1
Figure 17.16 Operation Timing For Receiving One Byte (MST = 1)
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Section 17 I C Bus Interface 3 (IIC3)
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17.4.7
Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched internally. Figure 17.17 shows a block diagram of the noise filter circuit. The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or SDA input signal
C D Latch Q D
C Q Latch D
C Q Latch Match detector 1 Internal SCL or SDA signal 0
Match detector NF2CYC Peripheral clock cycle Sampling clock
Figure 17.17 Block Diagram of Noise Filter
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Section 17 I C Bus Interface 3 (IIC3)
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17.4.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface 3 are shown in figures 17.18 to 17.21.
Start Initialize Read BBSY in ICCR2 No BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1 Write 1 to BBSY and 0 to SCP Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER ACKBR=0 ? Yes Transmit mode? Yes Write transmit data in ICDRT Read TDRE in ICSR No No TDRE=1 ? Yes Last byte? Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No STOP=1 ? Yes Set MST and TRS in ICCR1 to 0 Clear TDRE in ICSR End [15] [14] [11] [12] [13] [9] [8] [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. [7] [13] Issue the stop condition. No No [6] [1] [1] [2] [3] [2] [3] [4] [4] [5] [6] [7] [8] [9] Test the status of the SCL and SDA lines. Set master transmit mode. Issue the start condition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. Wait for ICDRT empty. Set the last byte of transmit data.
[10] Wait for last byte to be transmitted. [11] Clear the TEND flag. Master receive mode [12] Clear the STOP flag.
Figure 17.18 Sample Flowchart for Master Transmit Mode
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Section 17 I C Bus Interface 3 (IIC3)
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Master receive mode Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR [2] [3] [1] [1] Clear TEND, select master receive mode, and then clear TDRE. * [2] Set acknowledge to the transmit device. * [3] Dummy-read ICDDR. * [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [5] [8] Read the (final byte - 1) of received data. [6] [9] Wait for the last byte to be receive. [10] Clear the STOP flag. Set ACKBT in ICIER to 1 [7] Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR No RDRF = 1 ? Yes Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No STOP = 1 ? Yes Read ICDRR Clear RCVD in ICCR1 to 0 Clear MST in ICCR1 to 0 End [13] [14] [15] [12] [10] [11] When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. Notes: * Make sure that no interrupt will be generated during steps [1] to [3]. [9] [15] Set slave receive mode. [8] [11] Issue the stop condition. [12] Wait for the creation of stop condition. [13] Read the last byte of receive data. [14] Clear RCVD.
Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes
Figure 17.19 Sample Flowchart for Master Receive Mode
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Section 17 I C Bus Interface 3 (IIC3)
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Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No TDRE = 1 ? Yes No Last byte? Yes Write transmit data in ICDRT Read TEND in ICSR No [5] TEND = 1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy-read ICDRR Clear TDRE in ICSR End [4] [3] [1]
[1] Clear the AAS flag. [2] Set transmit data for ICDRT (except for the last byte). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag. [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL. [9] Clear the TDRE flag.
[6] [7] [8] [9]
Figure 17.20 Sample Flowchart for Slave Transmit Mode
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Section 17 I C Bus Interface 3 (IIC3)
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Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR
[1] [2] Set acknowledge to the transmit device. [2] [3] [3] Dummy-read ICDRR. [4] Wait for 1 byte to be received.
Read RDRF in ICSR No
[4]
[5] Check whether it is the (last receive - 1). [6] Read the receive data. [7] Set acknowledge of the last byte.
RDRF = 1 ? Yes
Last receive - 1?
Yes
[5]
[8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received. [10] Read for the last byte of receive data.
No Read ICDRR
[6]
Set ACKBT in ICIER to 1 Read ICDRR Read RDRF in ICSR No
[7] [8]
Note: When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR.
[9]
RDRF = 1 ? Yes Read ICDRR End
[10]
Figure 17.21 Sample Flowchart for Slave Receive Mode
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Section 17 I C Bus Interface 3 (IIC3)
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17.5
Interrupt Requests
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost/overrun error. Table 17.4 shows the contents of each interrupt request. Table 17.4 Interrupt Requests
Interrupt Request Transmit data Empty Transmit end Receive data full STOP recognition NACK detection Arbitration lost/ overrun error Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE = 1) * (TIE = 1) (TEND = 1) * (TEIE = 1) (RDRF = 1) * (RIE = 1) (STOP = 1) * (STIE = 1) {(NACKF = 1) + (AL = 1)} * (NAKIE = 1) I C Bus Format
2
Clocked Synchronous Serial Format
When the interrupt condition described in table 17.4 is 1, the CPU executes an interrupt exception handling. Note that a TXI or RXI interrupt can activate the DMAC if the setting for DMAC activation has been made. In such a case, an interrupt request is not sent to the CPU. Interrupt sources should be cleared in the exception handling. The TDRE and TEND bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an excessive data of one byte may be transmitted.
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Section 17 I C Bus Interface 3 (IIC3)
2
17.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 17.22 shows the timing of the bit synchronous circuit and table 17.5 shows the time when the SCL output changes from low to Hi-Z then SCL is monitored.
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Section 17 I C Bus Interface 3 (IIC3)
2
(1) Normal case
Synchronous clock*1
VIH
SCL pin
Internal delay*2 Internally monitored SCL
Monitored value is high level Time for monitoring SCL (2) When SCL is driven low at first by the slave device
Synchronous clock*1
Slave low level output
VIH VIH
SCL pin Internal delay*2 Internally monitored SCL
SCL not driven to low level Internal delay*2
Monitored value is high level Monitored value is low level Time for Time for monitoring SCL monitoring SCL (3) When the rising speed of SCL is slow Synchronous clock*1
Monitored value is high level Time for monitoring SCL
SCL pin
VIH
The rate is slower than the settings. SCL not driven to low level
Internal delay*2 Internally monitored SCL
Time for monitoring SCL
Monitored value is low level
Notes: 1. Clock whose transfer rate is set by bits CKS[3:0] in I2C bus control register 1 (ICCR1). 2. 3 to 4 tpcyc when the NF2CYC bit in NF2CYC is 0 and 4 to 5 tpcyc when the NF2CYC bit is 1.
Figure 17.22 Bit Synchronous Circuit Timing
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Section 17 I C Bus Interface 3 (IIC3)
2
Table 17.5 Time for Monitoring SCL
CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL*1 9 tpcyc*2 21 tpcyc*2 33 tpcyc*2 81 tpcyc*2
Notes: 1. Monitors the (on-board) SCL level after the time (pcyc) for monitoring SCL has passed since the rising edge of the SCL monitor timing reference clock. 2. pcyc = P x cyc
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Section 17 I C Bus Interface 3 (IIC3)
2
17.7
17.7.1
Usage Note
Issuance of Stop Condition and Start Condition (Retransmission)
Issue a start (retransmission) or stop condition after the falling edge of the 9th clock has been recognized. The falling edge of the 9th clock can be recognized by checking the SCLO bit in the I2C bus control register 2 (ICCR2). When a start (retransmission) or stop condition is issued with a certain timing under the following conditions (1 or 2), the start (retransmission) or stop condition may not be output correctly. Usage under conditions other than those described below will not cause any problem. 1. SCL takes longer to rise than the period defined in section 17.6, Bit Synchronous Circuit, due to the load of the SCL bus (load capacitance or pull-up resistance). 2. The low-level period between the 8th and 9th clock is prolonged by the slave device, which activates the bit synchronous circuit. 17.7.2 Settings for Multi-Master Operation
1. Transfer rate setting In multi-master operation, specify a transfer rate of at least 1/1.8 of the fastest transfer rate among the other masters. For example, when the fastest of the other masters is at 400 kbps, the IIC transfer rate of this LSI must be specified as 223 kbps (= 400/1.8) or a higher rate. 2. MST and TRS bits in ICCR1 In multi-master operation, use the MOV instruction to set the MST and TRS bits in ICCR1. 3. Loss of arbitration When arbitration is lost, check whether the MST and TRS bits in ICCR1 are 0. If the MST and TRS bits in ICCR1 have been set to a value other than 0, clear the bits to 0. 17.7.3 Reading ICDRR in Master Receive Mode
In master receive mode, read ICDRR before the rising edge of the 8th clock of SCL. If ICDRR cannot be read before the rising edge of the 8th clock so that the next round of reception proceeds with the RDRF bit in ICSR set to 1, the 8the clock is fixed low and the 9th clock is output. If ICDRR cannot be read before the rising edge of the 8th clock of SCL, set the RCVD bit in ICRR1 to 1 so that transfer proceeds in byte units.
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Section 18 Serial Sound Interface (SSI)
Section 18 Serial Sound Interface (SSI)
The serial sound interface (hereinafter referred to as the "SSI") is a transceiver module designed to send or receive audio data interface with a variety of devices offering Philips format. It also provides additional modes for other common formats as well as multi-channel mode.
18.1
Features
* Number of channels: Two channels * Operating mode: Non-compressed mode The non-compressed mode supports serial audio streams divided by channels. * Serves as both a transmitter and a receiver * Capable of using serial bus format * Asynchronous transfer takes place between the data buffer and the shift register. * It is possible to select a value as the dividing ratio for the clock used by the serial but interface. * It is possible to control data transmission or reception with DMAC and interrupt requests. * Selects the oversample clock from among the pins AUDIO_CLK, or AUDIO_X1 and AUDIO_X2. External clock frequency input through the pins AUDIO_CLK, or AUDIO_X1 and AUDIO_X2: 1 to 40 MHz Crystal oscillator frequency for the pins AUDIO_X1 and AUDIO_X2: 10 to 25 MHz Figure 18.1 shows a schematic diagram of the four channels in the SSI module.
SSIWS0 SSISCK0 SSIDATA0 SSIWS1 SSISCK1 SSIDATA1
SSI0
SSI1
AUDIO_CLK AUDIO_X1 AUDIO_X2
Figure 18.1 Schematic Diagram of SSI Module
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Section 18 Serial Sound Interface (SSI)
Figure 18.2 shows a block diagram of the SSI module when it is used alone.
Peripheral bus Interrupt request SSI module Register SSICR SSISR SSITDR SSIRDR Data buffer DMA request
Control circuit Serial audio bus SSIDATA MSB
Barrel shifter
Shift register
LSB
SSIWS Bit counter
SSISCK
Serial clock control Divider
AUDIO_CLK
AUDIO_X1
AUDIO_X2
[Legend] SSICR: SSISR: SSITDR: SSIRDR:
Control register Status register Transmit data register Receive data register
Oscillation circuit
Figure 18.2 Block Diagram of SSI
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Section 18 Serial Sound Interface (SSI)
18.2
Input/Output Pins
Table 18.1 shows the pin assignments relating to the SSI module. Table 18.1 Pin Assignments
Pin Name SSISCK0 SSIWS0 SSIDATA0 SSISCK1 SSIWS1 SSIDATA1 AUDIO_CLK AUDIO_X1 AUDIO_X1 Number of Pins 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O Input Input Output Description Serial bit clock Word selection Serial data input/output Serial bit clock Word selection Serial data input/output External clock for audio (Entering oversample clock 256/384/512fs) Crystal oscillator for audio (Entering oversample clock 256/384/512fs)
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Section 18 Serial Sound Interface (SSI)
18.3
Register Description
The SSI has the following registers. Note that explanation in the text does not refer to the channels. Table 18.2 Register Description
Channel 0 Register Name Control register 0 Status register 0 Transmit data register 0 Receive data register 0 1 Control register 1 Status register 1 Transmit data register 1 Receive data register 1 Abbreviation SSICR0 SSISR0 SSITDR0 SSIRDR0 SSICR1 SSISR1 SSITDR1 SSIRDR1 R/W R/W R/W* R/W R R/W R/W* R/W R Initial Value H'00000000 H'02000003 H'00000000 H'00000000 H'00000000 H'02000003 H'00000000 H'00000000 Address H'FFFED000 H'FFFED004 H'FFFED008 H'FFFED00C H'FFFED080 H'FFFED084 H'FFFED088 H'FFFED08C Access Size 32 32 32 32 32 32 32 32
Note:
*
For this register, bits 26 and 27 are capable of reading and writing, although the others are read-only bits. For details, refer to section 18.3.2, Status Register (SSISR).
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Section 18 Serial Sound Interface (SSI)
18.3.1
Control Register (SSICR)
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and sets operating mode. SSICR is initialized to H'00000000 by a power-on reset or in deep standby mode.
Bit: 31
--
30
-- 0 R
29
-- 0 R
28
27
26
25
24
23
22
21
20
DWL[2:0]
19
18
17
SWL[2:0]
16
DMEN UIEN OIEN IIEN DIEN 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
CHNL[1:0] 0 R/W 0 R/W 0 R/W
Initial value: R/W: Bit:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
15
14
13
12
11
10
9
8
7
-- 0 R
6
5
CKDV[2:0]
4
3
MUEN 0 R/W
2
-- 0 R
1
TRMD 0 R/W
0
EN 0 R/W
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 29
Bit Name
Initial Value All 0
R/W R
Description Reserved The read value is not guaranteed. The write value should always be 0.
28
DMEN
0
R/W
DMA Enable Enables/disables the DMA request. 0: DMA request is disabled. 1: DMA request is enabled.
27
UIEN
0
R/W
Underflow Interrupt Enable 0: Underflow interrupt is disabled. 1: Underflow Interrupt is enabled.
26
OIEN
0
R/W
Overflow Interrupt Enable 0: Overflow interrupt is disabled. 1: Overflow interrupt is enabled.
25
IIEN
0
R/W
Idle Mode Interrupt Enable 0: Idle mode interrupt is disabled. 1: Idle mode interrupt is enabled.
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Section 18 Serial Sound Interface (SSI)
Bit 24
Bit Name DIEN
Initial Value 0
R/W R/W
Description Data Interrupt Enable 0: Data interrupt is disabled. 1: Data interrupt is enabled.
23, 22
CHNL[1:0]
00
R/W
Channels These bits show the number of channels in each System Word. 00: Having one channel per System Word 01: Having two channels per System Word 10 Having three channels per System Word 11: Having four channels per System Word
21 to 19
DWL[2:0]
000
R/W
Data Word Length Indicates the number of bits in a data word. 000: 8 bits 001: 16 bits 010: 18 bits 011: 20 bits 100: 22 bits 101: 24 bits 110: 32 bits 111: Reserved
18 to 16
SWL[2:0]
000
R/W
System Word Length Indicates the number of bits in a system word. 000: 8 bits 001: 16 bits 010: 24 bits 011: 32 bits 100: 48 bits 101: 64 bits 110: 128 bits 111: 256 bits
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Section 18 Serial Sound Interface (SSI)
Bit 15
Bit Name SCKD
Initial Value 0
R/W R/W
Description Serial Bit Clock Direction 0: Serial bit clock is input, slave mode. 1: Serial bit clock is output, master mode. Note: SSI0 and SSI1 permit only the following setting: (SCKD, SWSD) = (0,0) and (1,1). Other settings are prohibited.
14
SWSD
0
R/W
Serial WS Direction 0: Serial word select is input, slave mode. 1: Serial word select is output, master mode. Note: SSI0 and SSI1 permit only the following setting: (SCKD, SWSD) = (0,0) and (1,1). Other settings are prohibited.
13
SCKP
0
R/W
Serial Bit Clock Polarity 0: SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge). 1: SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge).
SCKP = 0 SSIDATA input sampling timing at the time of reception (TRMD = 0) SSIDATA output change timing at the time of transmission (TRMD = 1) SSIWS input sampling timing at the time of slave mode (SWSD = 0) SSIWS output change timing at the time of master mode (SWSD = 1) SSISCK rising edge SSISCK falling edge SSISCK rising edge SSISCK falling edge SCKP = 1 SSISCK falling edge SSISCK rising edge SSISCK falling edge SSISCK rising edge
12
SWSP
0
R/W
Serial WS Polarity 0: SSIWS is low for 1st channel, high for 2nd channel. 1: SSIWS is high for 1st channel, low for 2nd channel.
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Section 18 Serial Sound Interface (SSI)
Bit 11
Bit Name SPDP
Initial Value 0
R/W R/W
Description Serial Padding Polarity 0: Padding bits are low. 1: Padding bits are high. Note: When MUEN = 1, padding bits are low. (The MUTE function is given priority.)
10
SDTA
0
R/W
Serial Data Alignment 0: Transmitting and receiving in the order of serial data and padding bits 1: Transmitting and receiving in the order of padding bits and serial data
9
PDTA
0
R/W
Parallel Data Alignment This bit is ignored if CPEN = 1. When the data word length is 32, 16 or 8 bit, this configuration field has no meaning. This bit applies to SSIRDR in receive mode and SSITDR in transmit mode. 0: Parallel data (SSITDR, SSIRDR) is left-aligned 1: Parallel data (SSITDR, SSIRDR) is right-aligned. * DWL = 000 (with a data word length of 8 bits), the PDTA setting is ignored. All data bits in SSIRDR or SSITDR are used on the audio serial bus. Four data words are transmitted or received at each 32-bit access. The first data word is derived from bits 7 to 0, the second from bits 15 to 8, the third from bits 23 to 16 and the last data word is derived from bits 31 to 24. * DWL = 001 (with a data word length of 16 bits), the PDTA setting is ignored. All data bits in SSIRDR or SSITDR are used on the audio serial bus. Two data words are transmitted or received at each 32-bit access. The first data word is derived from bits 15 to 0 and the second data word is derived from bits 31 to 16.
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Section 18 Serial Sound Interface (SSI)
Bit 9
Bit Name PDTA
Initial Value 0
R/W R/W
Description * DWL = 010, 011, 100, 101 (with a data word length of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned) The data bits used in SSIRDR or SSITDR are the following: Bits 31 down to (32 minus the number of bits in the data word length specified by DWL). That is, If DWL = 011, the data word length is 20 bits; therefore, bits 31 to 12 in either SSIRDR or SSITDR are used. All other bits are ignored or reserved. * DWL = 010, 011, 100, 101 (with a data word length of 18, 20, 22 or 24 bits), PDTA = 1 (right-aligned) The data bits used in SSIRDR or SSITDR are the following: Bits (the number of bits in the data word length specified by DWL minus 1) to 0 i.e. if DWL = 011, then DWL = 20 and bits 19 to 0 are used in either SSIRDR or SSITDR. All other bits are ignored or reserved. * DWL = 110 (with a data word length of 32 bits), the PDTA setting is ignored. All data bits in SSIRDR or SSITDR are used on the audio serial bus.
8
DEL
0
R/W
Serial Data Delay 0: 1 clock cycle delay between SSIWS and SSIDATA 1: No delay between SSIWS and SSIDATA
7
0
R
Reserved The read value is undefined. The write value should always be 0.
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Section 18 Serial Sound Interface (SSI)
Bit 6 to 4
Bit Name CKDV[2:0]
Initial Value 000
R/W R/W
Description Serial Oversample Clock Divide Ratio Sets the ratio between oversample clock* (AUDIO_CLK, or AUDIO_X1 and AUDIO_X2) and the serial bit clock. In addition, combining these bits and the CKDV3 bit in the standby control register enables to divide the clock further by 1/4. This bit is ignored if SCKD = 0. The serial bit clock is used in the shift register and is provided on the SSISCK module pin. * When CKDV3 = 1
000: Serial bit clock frequency = Oversample clock Frequency/1 001: Serial bit clock frequency = Oversample clock frequency/2 010: Serial bit clock frequency = Oversample clock frequency/4 011: Serial bit clock frequency = Oversample clock frequency/8 100: Serial bit clock frequency = Oversample clock frequency/16 101: Serial bit clock frequency = Oversample clock frequency/6 110: Serial bit clock frequency = Oversample clock frequency/12 111: Setting prohibited
*
When CKDV3 = 0
000: Serial bit clock frequency = Oversample clock Frequency/4 001: Serial bit clock frequency = Oversample clock frequency/8 010: Serial bit clock frequency = Oversample clock frequency/16 011: Serial bit clock frequency = Oversample clock frequency/32 100: Serial bit clock frequency = Oversample clock frequency/64 101: Serial bit clock frequency = Oversample clock frequency/24 110: Serial bit clock frequency = Oversample clock frequency/48 111: Setting prohibited
Note: * AUDIO_X1 and AUDIO_X2 is selected as oversample clock when the PD0MD0 bit in the port D control register (PDCR1) of PFC is set to 0, and AUDIO_CLK is selected when the bit is set to 1.
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Section 18 Serial Sound Interface (SSI)
Bit 3
Bit Name MUEN
Initial Value 0
R/W R/W
Description Mute Enable 0: Module is not muted. 1: Module is muted.
2
0
R
Reserved The read value is undefined. The write value should always be 0.
1
TRMD
0
R/W
Transmit/Receive Mode Select 0: Module is in receive mode. 1: Module is in transmit mode.
0
EN
0
R/W
SSI Module Enable 0: Module is disabled. 1: Module is enabled.
18.3.2
Status Register (SSISR)
SSISR consists of status flags indicating the operational status of the SSI module and bits indicating the current channel numbers and word numbers. SSISR is initialized to H'02000003 by a power-on reset or in deep standby mode.
Bit: 31
--
30
-- 0 R
29
-- 0 R
28
27
26
25
24
23
-- -- R
22
-- -- R
21
-- -- R
20
-- -- R
19
-- -- R
18
-- -- R
17
-- -- R
16
-- -- R
DMRQ UIRQ OIRQ IIRQ DIRQ 0 R 0 0 R/W*1 R/W*1 R 1*2 0 R
Initial value: R/W: Bit:
0 R
15
--
14
-- -- R
13
-- -- R
12
-- -- R
11
-- -- R
10
-- -- R
9
-- -- R
8
-- -- R
7
-- -- R
6
-- -- R
5
-- -- R
4
-- -- R
3
2
1
0
CHNO[1:0] SWNO IDST 0 R 0 R 1 R 1*2 R
Initial value: R/W:
-- R
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is ignored. 2. The SSI clock must be kept supplied until the SSI is in the idle state.
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Section 18 Serial Sound Interface (SSI)
Bit 31 to 29
Bit Name
Initial Value All 0
R/W R
Description Reserved The read value is not guaranteed. The write value should always be 0.
28
DMRQ
0
R
DMA Request Status Flag This status flag allows the CPU to recognize the value of the DMA request pin on the SSI module. * TRMD = 0 (Receive mode) If DMRQ = 1, the SSIRDR has unread data. If SSIRDR is read, DMRQ = 0 until there is new unread data. * TRMD = 1 (Transmit mode) If DMRQ = 1, SSITDR requires data to be written to continue the transmission to the audio serial bus. Once data is written to SSITDR, DMRQ = 0 until it requires further transmit data.
27
UIRQ
0
R/W*1 Underflow Error Interrupt Status Flag This status flag indicates that data was supplied at a lower rate than was required. In either case, this bit is set to 1 regardless of the value of the UIEN bit and can be cleared by writing 0 to this bit. If UIRQ = 1 and UIEN = 1, an interrupt occurs. * TRMD = 0 (Receive mode) If UIRQ = 1, SSIRDR was read before there was new unread data indicated by the DMRQ or DIRQ bit. This can lead to the same received sample being stored twice by the host leading to potential corruption of multi-channel data. * TRMD = 1 (Transmit mode) If UIRQ = 1, SSITDR did not have data written to it before it was required for transmission. This will lead to the same sample being transmitted once more and a potential corruption of multi-channel data. This is more serious error than a receive mode underflow as the output SSI data results in error. Note: When underflow error occurs, the current data in the data buffer of this module is transmitted until the next data is filled.
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Section 18 Serial Sound Interface (SSI)
Bit 26
Bit Name OIRQ
Initial Value 0
R/W R/W*
1
Description Overflow Error Interrupt Status Flag This status flag indicates that data was supplied at a higher rate than was required. In either case this bit is set to 1 regardless of the value of the OIEN bit and can be cleared by writing 0 to this bit. If OIRQ = 1 and OIEN = 1, an interrupt occurs. * TRMD = 0 (Receive mode) If OIRQ = 1, SSIRDR was not read before there was new unread data written to it. This will lead to the loss of a sample and a potential corruption of multi-channel data. Note: When an overflow error occurs, the current data in the data buffer of this module is overwritten by the next incoming data from the SSI interface. * TRMD = 1 (Transmit mode) If OIRQ = 1, SSITDR had data written to it before it was transferred to the shift register. This will lead to the loss of a sample and a potential corruption of multi-channel data.
25
IIRQ
1*2
R
Idle Mode Interrupt Status Flag This interrupt status flag indicates whether the SSI module is in idle state. This bit is set regardless of the value of the IIEN bit to allow polling. The interrupt can be masked by clearing IIEN, but cannot be cleared by writing to this bit. If IIRQ = 1 and IIEN = 1, an interrupt occurs. 0: The SSI module is not in idle state. 1: The SSI module is in idle state.
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Section 18 Serial Sound Interface (SSI)
Bit 24
Bit Name DIRQ
Initial Value 0
R/W R
Description Data Interrupt Status Flag This status flag indicates that the module has data to be read or requires data to be written. In either case this bit is set to 1 regardless of the value of the DIEN bit to allow polling. The interrupt can be masked by clearing DIEN, but cannot be cleared by writing to this bit. If DIRQ= 1 and DIEN = 1, an interrupt occurs. * TRMD = 0 (Receive mode) 0: No unread data in SSIRDR 1: Unread data in SSIRDR * TRMD = 1 (Transmit mode) 0: Transmit buffer is full. 1: Transmit buffer is empty and requires data to be written to SSITDR.
23 to 4
Undefined
R
Reserved The read value is not guaranteed. The write value should always be 0.
3, 2
CHNO[1:0]
00
R
Channel Number This value indicates the current channel number. * TRMD = 0 (Receive mode) CHNO indicates which channel the data in SSIRDR currently represents. This value will change as the data in SSIRDR is updated from the shift register. * TRMD = 1 (Transmit mode) CHNO indicates which channel is required to be written to SSITDR. This value will change as the data is copied to the shift register, regardless of whether the data is written to SSITDR.
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Section 18 Serial Sound Interface (SSI)
Bit 1
Bit Name SWNO
Initial Value 1
R/W R
Description System Word Number This status bit indicates the current word number. * TRMD = 0 (Receive mode) SWNO indicates which system word the data in SSIRDR currently represents. This value will change as the data in SSIRDR is updated from the shift register, regardless of whether SSIRDR has been read. * TRMD = 1 (Transmit mode) SWNO indicates which system word is required to be written to SSITDR. This value will change as the data is copied to the shift register, regardless of whether the data is written to SSITDR.
0
IDST
1*2
R
Idle Mode Status Flag This status flag indicates that the serial bus activity has stopped. This bit is cleared if EN = 1 and the serial bus are currently active. This bit is automatically set to 1 under the following conditions. * SSI = Master transmitter (SWSD = 1 and TRMD = 1) This bit is set to 1 if the EN bit is cleared and the data written to SSITDR is completely output from the serial data input/output pin (SSIDATA), that is, the output of the system word length is completed. * SSI = Master receiver (SWSD = 1 and TRMD = 0) This bit is set to 1 if the EN bit is cleared and the current system word is completed. * SSI = Slave transmitter/receiver (SWSD = 0) This bit is set to 1 if the EN bit is cleared and the current system word is completed. Note: If the external master stops the serial bus clock before the current system word is completed, this bit is not set.
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is ignored. 2. The SSI clock must be kept supplied until the SSI is in the idle state.
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Section 18 Serial Sound Interface (SSI)
18.3.3
Transmit Data Register (SSITDR)
SSITDR is a 32-bit register that stores data to be transmitted. Data written to this register is transferred to the shift register upon transmission request. If the data word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR. The data in the buffer can be accessed by reading this register. SSITDR is initialized to H'00000000 by a power-on reset or in deep standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 R/W: R/W Bit: 15
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
18.3.4
Receive Data Register (SSIRDR)
SSIRDR is a 32-bit register that stores receive messages. Data in this register is transferred from the shift register each time data word is received. If the data word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR. SSIRDR is initialized to H'00000000 by a power-on reset or in deep standby mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value: R/W: Bit:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
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Section 18 Serial Sound Interface (SSI)
18.4
18.4.1
Operation Description
Bus Format
The SSI module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus format can be selected from one of the four major modes shown in table 18.3. Table 18.3 Bus Format for SSI Module
Non-Compressed Slave Receiver TRMD CPEN SCKD SWSD EN MUEN DIEN IIEN OIEN UIEN DEL PDTA SDTA SPDP SWSP SCKP SWL [2:0] DWL [2:0] CHNL [1:0] Configuration Bits 0 0 0 0 Control Bits Non-Compressed Slave Transmitter 1 0 0 0 Non-Compressed Master Receiver 0 0 1 1 Non-Compressed Master Transmitter 1 0 1 1
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Section 18 Serial Sound Interface (SSI)
18.4.2
Non-Compressed Modes
The non-compressed modes support all serial audio streams split into channels. It supports Philips, Sony and Matsushita modes as well as many more variants on these modes. (1) Slave Receiver
This mode allows the module to receive serial data from another device. The clock and word select signal used for the serial data stream is also supplied from an external device. If these signals do not conform to the format specified in the configuration fields of the SSI module, operation is not guaranteed. (2) Slave Transmitter
This mode allows the module to transmit serial data to another device. The clock and word select signal used for the serial data stream is also supplied from an external device. If these signals do not conform to the format specified in the configuration fields of the SSI module, operation is not guaranteed. (3) Master Receiver
This mode allows the module to receive serial data from another device. The clock and word select signals are internally derived from the AUDIO_CLK input clock. The format of these signals is defined in the configuration fields of the SSI module. If the incoming data does not follow the configured format, operation is not guaranteed. (4) Master Transmitter
This mode allows the module to transmit serial data to another device. The clock and word select signals are internally derived from the AUDIO_CLK input clock. The format of these signals is defined in the configuration fields of the SSI module. (5) Operating Setting Related to Word Length
All bits related to the SSICR's word length are valid in non-compressed modes. There are many configurations the SSI module supports, but some of the combinations are shown below for the popular formats by Philips, Sony, and Matsushita.
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Section 18 Serial Sound Interface (SSI)
1. Philips Format Figures 18.3 and 18.4 demonstrate the supported Philips format both with and without padding. Padding occurs when the data word length is smaller than the system word length.
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00 System word length = data word length
SSISCK
SSIWS
LSB +1
LSB +1
SSIDATA
prev. sample MSB
LSB MSB
LSB next sample
System word 1 = data word 1
System word 2 = data word 2
Figure 18.3 Philips Format (without Padding)
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length
SSISCK
SSIWS
SSIDATA
MSB
LSB
MSB
LSB
Next
Data word 1 System word 1
Padding
Data word 2 System word 2
Padding
Figure 18.4 Philips Format (with Padding)
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Section 18 Serial Sound Interface (SSI)
2. Sony Format Figure 18.5 shows Sony format and figure 18.6 shows Matsushita format. Padding is assumed in both cases, but may not be present in a final implementation if the system word length equals the data word length.
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length
SSISCK
SSIWS
SSIDATA
MSB
LSB
MSB
LSB
Next
Data word 1 System word 1
Padding
Data word 2 System word 2
Padding
Figure 18.5 Sony Format (Transmitted and Received in the order of Serial Data and Padding Bits) 3. Matsushita Format
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 1 System word length > data word length SSISCK
SSIWS
SSIDATA
Prev.
MSB
LSB
MSB
LSB
Padding
Data word 1 System word 1
Padding
Data word 2 System word 2
Figure 18.6 Matsushita Format (Transmitted and Received in the order of Padding Bits and Serial Data)
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Section 18 Serial Sound Interface (SSI)
(6)
Multi-channel Formats
Some devices extend the definition of the specification by Philips and allow more than 2 channels to be transferred within two system words. The SSI module supports the transfer of 2, 3 and 4 channels by using the CHNL, SWL and DWL bits only when the system word length (SWL) is greater than or equal to the data word length (DWL) multiplied by channels (CHNL). Table 18.4 shows the number of padding bits for each of the valid setting. If setting is not valid, "" is indicated instead of a number. Table 18.4 The Number of Padding Bits for Each Valid Setting
Padding Bits Per System Word Decoded Channels per System SWL Word [2:0] DWL[2:0] 000 001 010 011 100 101 110
CHNL [1:0]
Decoded Word Length 8
16
18
20
22
24
32
00
1
000 001 010 011 100 101 110 111
8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256
0 8 16 24 40 56 120 248 0 8 16 32 48 112 240
0 8 16 32 48 112 240 0 16 32 96 224
6 14 30 46 110 238 12 28 92 220
4 12 28 44 108 236 8 24 88 216
2 10 26 42 106 234 4 20 84 212
0 8 24 40 104 232 0 16 80 208
0 16 32 96 224 0 64 192
01
2
000 001 010 011 100 101 110 111
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Section 18 Serial Sound Interface (SSI)
Padding Bits Per System Word Decoded Channels per System SWL Word [2:0]
DWL[2:0] 000
001
010
011
100
101
110
CHNL [1:0]
Decoded Word Length 8
16
18
20
22
24
32
10
3
000 001 010 011 100 101 110 111
8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256
0 8 24 40 104 232 0 16 32 96 224
0 16 80 208 0 64 192
10 74 202 56 184
4 68 196 48 176
62 190 40 168
56 184 32 160
32 160 0 128
11
4
000 001 010 011 100 101 110 111
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Section 18 Serial Sound Interface (SSI)
When the SSI module acts as a transmitter, each word written to SSITDR is transmitted to the serial audio bus in the order they are written. When the SSI module acts as a receiver, each word received by the serial audio bus is read in the order received from the SSIRDR register. Figures 18.7 to 18.9 show how 2, 3 and 4 channels are transferred to the serial audio bus. Note that there are no padding bits in the first example, the second example is left-aligned and the third is right-aligned. This selection is arbitrary and is just for demonstration purposes only.
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 01, SPDP = don't care, SDTA = don't care System word length = data word length x 2 SSISCK SSIWS SSIDATA
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
Data word 1
Data word 2
Data word 3
Data word 4
Data word 1
Data word 2
Data word 3
Data word 4
System word 1
System word 2
System word 1
System word 2
Figure 18.7 Multichannel Format (2 Channels Without Padding)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = 1, SDTA = 0 System word length = data word length x 3
SSISCK SSIWS SSIDATA
MSB LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
MSB
Padding
Data word 1
Data word 2
System word 1
Data word 3
Data word 4
Data word 5
Data word 6
System word 2
Figure 18.8 Multichannel Format (3 Channels with High Padding)
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Padding
Section 18 Serial Sound Interface (SSI)
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 11, SPDP = 0, SDTA = 1 System word length = data word length x 4
SSISCK SSIWS SSIDATA
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
Padding
Data word 1
Data word 2
Data word 3
Data word 4
Padding
Data word 5
Data word 6
Data word 7
Data word 8
System word 1
System word 2
Figure 18.9 Multichannel Format (4 Channels; Transmitting and Receiving in the order of Padding Bits and Serial Data; with Padding) (7) Bit Setting Configuration Format
Several more configuration bits in non-compressed mode are shown below. These bits are not mutually exclusive, but some combinations may not be useful for any other device. These configuration bits are described below with reference to figure 18.10, Basic Sample Format.
SWL = 6 bits (not attainable in SSI module, demonstration only) DWL = 4 bits (not attainable in SSI module, demonstration only) CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0 4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus. SSISCK SSIWS 1st channel 2nd channel
SSIDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Key for this and following diagrams: Arrow head indicates sampling point of receiver TDn 0 1 Bit n in SSITDR means a low level on the serial bus (padding or mute) means a high level on the serial bus (padding)
Figure 18.10 Basic Sample Format (Transmit Mode with Example System/Data Word Length)
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Section 18 Serial Sound Interface (SSI)
Figure 18.10 uses a system word length of 6 bits and a data word length of 4 bits. These settings are not possible with the SSI module but are used only for clarification of the other configuration bits. 1. Inverted Clock
As basic sample format configuration except SCKP = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Figure 18.11 Inverted Clock 2. Inverted Word Select
As basic sample format configuration except SWSP = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Figure 18.12 Inverted Word Select 3. Inverted Padding Polarity
As basic sample format configuration except SPDP = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD28
1
1
TD31 TD30 TD29 TD28
1
1
TD31 TD30 TD29 TD28
1
1
TD31
Figure 18.13 Inverted Padding Polarity
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Section 18 Serial Sound Interface (SSI)
4. Transmitting and Receiving in the Order of Padding Bits and Serial Data; with Delay
As basic sample format configuration except SDTA = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
Figure 18.14 Transmitting and Receiving in the Order of Padding Bits and Serial Data; with Delay 5. Transmitting and Receiving in the Order of Padding Bits and Serial Data; without Delay
As basic sample format configuration except SDTA = 1 and DEL = 1 SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA
TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
Figure 18.15 Transmitting and Receiving in the Order of Padding Bits and Serial Data; without Delay 6. Transmitting and Receiving in the Order of Serial Data and Padding Bits; without Delay
As basic sample format configuration except DEL = 1 SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30
Figure 18.16 Transmitting and Receiving in the Order of Serial Data and Padding Bits; without Delay
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Section 18 Serial Sound Interface (SSI)
7. Parallel Right-Aligned with Delay
As basic sample format configuration except PDTA = 1 SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA
TD0
0
0
TD3
TD2
TD1
TD0
0
0
TD3
TD2
TD1
TD0
0
0
TD3
Figure 18.17 Parallel Right-Aligned with Delay 8. Mute Enabled
As basic sample format configuration except MUEN = 1 (TD data ignored) SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18.18 Mute Enabled
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Section 18 Serial Sound Interface (SSI)
18.4.3
Operation Modes
There are three modes of operation: configuration, enabled and disabled. Figure 18.19 shows how the module enters each of these modes.
Reset Module configration (after reset)
EN = 0 (IDST = 1)
EN = 1 (IDST = 0)
Module disabled (waiting until bus inactive)
Module enabled (normal tx/rx) EN = 0 (IDST = 0)
Figure 18.19 Operation Modes (1) Configuration Mode
This mode is entered after the module is released from reset. All required configuration fields in the control register should be defined in this mode, before the SSI module is enabled by setting the EN bit. Setting the EN bit causes the module to enter the module enabled mode. (2) Module Enabled Mode
Operation of the module in this mode is dependent on the operation mode selected. For details, refer to section 18.4.4, Transmit Operation and section 18.4.5, Receive Operation, below.
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Section 18 Serial Sound Interface (SSI)
18.4.4
Transmit Operation
Transmission can be controlled either by DMA or interrupt. DMA control is preferred to reduce the processor load. In DMA control mode the processor will only receive interrupts if there is an underflow or overflow of data or the DMAC has finished its transfer. The alternative method is using the interrupts that the SSI module generates to supply data as required. This mode has a higher interrupt load as the module is only double buffered and will require data to be written at least every system word period. When disabling the module, the SSI clock* must remain present until the SSI module is in idle state, indicated by the IIRQ bit. Figure 18.20 shows the transmit operation in DMA control mode, and figure 18.21 shows the transmit operation in interrupt control mode. Note: * Input clock from the SSISCK pin when SCKD = 0. Input clock from the AUDIO_CLK pin, or AUDIO_X1 and AUDIO_X2 pins when SCKD = 1.
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Section 18 Serial Sound Interface (SSI)
(1)
Transmission Using DMA Controller
Start
Release from reset, set SSICR configuration bits.
Define TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
Set up DMA controller to provide transmission data as required.
Enable SSI module, enable DMA, enable error interrupts.
EN = 1, DMEN = 1, UIEN = 1, OIEN = 1
Wait for interrupt from DMAC or SSI.
SSI error interrupt? No No DMAC: End of Tx data? Yes Yes
Yes
More data to be send? No Disable SSI module, disable DMA, disable error interrupts, enable Idle interrupt. EN = 0, DMEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Wait for idle interrupt from SSI module.
End* Note: * If the SSI encounters an error interrupt underflow/overflow, go back to the start in the flowchart again.
Figure 18.20 Transmission Using DMA Controller
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Section 18 Serial Sound Interface (SSI)
(2)
Transmission using Interrupt Data Flow Control
Start Define TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL.
Release from reset, set SSICR configuration bits.
Enable SSI module, enable data interrupts, enable error interrupts.
EN = 1, DIEN = 1, UIEN = 1, OIEN = 1
For n = ( (CHNL + 1) x 2) Loop
Wait for interrupt from SSI.
Data interrupt? Yes Load data of channel n
No
Use SSI status register bits to realign data after underflow/overflow.
Next channel
Yes
More data to be send? No Disable SSI module, disable data interrupts disable error interrupts, enable Idle interrupt. EN = 0, DIEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Wait for Idle interrupt from SSI module.
End
Figure 18.21 Transmission Using Interrupt Data Flow Control
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Section 18 Serial Sound Interface (SSI)
18.4.5
Receive Operation
Like transmission, reception can be controlled either by DMA or interrupt. Figures 18.22 and 18.23 show the flow of operation. When disabling the SSI module, the SSI clock* must be kept supplied until the IIRQ bit is in idle state. Note: * Input clock from the SSISCK pin when SCKD = 0. Input clock from the AUDIO_CLK pin, or AUDIO_X1 and AUDIO_X2 pins when SCKD = 1.
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Section 18 Serial Sound Interface (SSI)
(1)
Reception Using DMA Controller
Start
Define TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL.
Release from reset, define SSICR configuration bits.
Setup DMA controller to transfer data from SSI module to memory.
Enable SSI module, enable DMA, enable error interrupts.
EN = 1, DMEN = 1, UIEN = 1, OIEN = 1
Wait for interrupt from DMAC or SSI
SSI error interrupt?
No No
DMAC: End of Rx data?
Yes
Yes Yes
More data to be send?
No
Disable SSI module, disable DMA, disable error interrupts, enable Idle interrupt.
EN = 0, DMEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Wait for idle interrupt from SSI module.
End*
Note: * If the SSI encounters an error interrupt underflow/overflow, go back to the start in the flowchart again.
Figure 18.22 Reception Using DMA Controller
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Section 18 Serial Sound Interface (SSI)
(2)
Reception Using Interrupt Data Flow Control
Start
Release from reset, define SSICR configuration bits.
Define TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL.
Enable SSI module, enable data interrupts, enable error interrupts.
EN = 1, DIEN = 1, UIEN = 1, OIEN = 1
Wait for interrupt from SSI.
SSI error interrupt?
Yes
Use SSI status register bits to realign data after underflow/overflow.
No
Read data from receive data register.
Yes
Receive more data?
No
Disable SSI module, disable data interrupts, disable error interrupts, enable idle interrupt.
EN = 0, DIEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Wait for idle interrupt from SSI module.
End
Figure 18.23 Reception Using Interrupt Data Flow Control
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Section 18 Serial Sound Interface (SSI)
When an underflow or overflow error condition has matched, the CHNO [1:0] bit and the SWNO bit can be used to recover the SSI module to a known status. When an underflow or overflow occurs, the host can read the channel number and system word number to determine what point the serial audio stream has reached. In the transmitter case, the host can skip forward through the data it wants to transmit until it finds the sample data that matches what the SSI module is expecting to transmit next, and so resynchronize with the audio data stream. In the receiver case the host CPU can store null data to make the number of receive data items consistent until it is ready to store the sample data that the SSI module is indicating will be received next, and so resynchronize with the audio data stream. 18.4.6 Temporary Stop and Restart Procedures in Transmit Mode
The following procedures can be used for implementation. (1) Procedure for the Repeated Transfer and Stop without having to Reconfigure the DMAC
1. Set SSICR.DMEN = 0 (disabling a DMA request) to stop the DMA transfer. 2. Wait for SSISR.DIRQ = 1 (transmit mode: the transmit buffer is empty) using a polling, interrupt, or the like. 3. With SSICR.EN = 0 (disabling an SSI module operation), stop the transfer. 4. Before attempting another transfer, make sure that SSISR.IDST = 1 is reached. 5. Set SSICR.EN = 1 (enabling an SSI module operation). 6. Wait for SSISR.DIRQ = 1, using a polling, interrupt, or the like. 7. Setting SSICR.DMEN = 1 (enabling a DMA request) will restart the DMA transfer. (2) Procedure for Reconfiguring the DMAC after an SSI stop
1. Set SSICR.DMEN = 0 (disabling a DMA request) to stop the DMA transfer. 2. Wait for SSISR.DIRQ = 1 (transmit mode: the transmit buffer is empty), using a polling, interrupt, or the like. 3. With SSICR.EN = 0 (disabling an SSI module operation), stop the transfer. 4. Stop the DMAC with DMSCNT of the DMAC. 5. Before attempting another transfer, make sure that SSISR.IDST = 1 is reached. 6. Set SSICR.EN = 1 (enabling an SSI module operation). 7. Set the DMAC registers and start the transfer. 8. Setting SSICR.DMEN = 1 (enabling a DMA request) will restart the DMA transfer.
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Section 18 Serial Sound Interface (SSI)
18.4.7
Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface. If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode and the shift register uses the bit clock that was input to the SSISCK pin. If the serial clock direction is set to output (SCKD = 1), the SSI module is in clock master mode, and the shift register uses the bit clock that was input from the AUDIO_CLK pin or AUDIO_X1 and AUDIO_X2 pins, or the bit clock that is generated by dividing them. This input clock is then divided by the ratio in the serial oversampling clock divide ratio (CKDV) in SSICR and used as the bit clock in the shift register. In either case the module pin, SSISCK, is the same as the bit clock.
18.5
18.5.1
Usage Notes
Limitations from Overflow during Receive DMA Operation
If an overflow occurs while the receive DMA is in operation, the module should be restarted. The receive buffer in the SSI consists of 32-bit registers that share the L and R channels. Therefore, data to be received at the L channel may sometimes be received at the R channel if an overflow occurs, for example, under the following condition: the control register (SSICR) has a 32-bit setting for both data word length (DWL2 to DWL0) and system word length (SWL2 to SWL). If an overflow is confirmed with the overflow error interrupt or overflow error status flag (the OIRQ bit in SSISR), write 0 to the EN bit in SSICR and DMEN bit to disable DMA in the SSI module, thus stopping the operation. (In this case, the controller setting should also be stopped.) After this, write 0 to the OIRQ bit to clear the overflow status, set DMA again and restart the transfer.
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Section 18 Serial Sound Interface (SSI)
18.5.2
Note on Using Oversample Clock
To use the externally input clock as the oversample clock, refer to the section 4.6.1, Note on Inputting External Clock, in which the terms EXTAL and XTAL pins should be replaced by the AUDIO_X1 and AUDIO_X2 pins respectively. To use the crystal resonator, refer to the section 4.6.2, Note on Using Crystal Resonator, in which the terms EXTAL and XTAL pins should be replaced by the AUDIO_X1 and AUDIO_X2 pins respectively. Also, see section 4.6.3, Note on Resonator. 18.5.3 Restriction on Stopping Clock Supply
Once the bits MSTP53 and MSTP52 in the standby control register 5 (STBCR5) are cleared to 0 and the SSI operation is started, do not set these bits to 1 (stops clock supply to the SSI).
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Section 18 Serial Sound Interface (SSI)
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.1
19.1.1
Summary
Overview
This document primarily describes the programming interface for the RCAN-ET module. It serves to facilitate the hardware/software interface so that engineers involved in the RCAN-ET implementation can ensure the design is successful. 19.1.2 Scope
The CAN Data Link Controller function is not described in this document. It is the responsibility of the reader to investigate the CAN Specification Document (see references). The interfaces from the CAN Controller are described, in so far as they pertain to the connection with the User Interface. The programming model is described in some detail. It is not the intention of this document to describe the implementation of the programming interface, but to simply present the interface to the underlying CAN functionality. The document places no constraints upon the implementation of the RCAN-ET module in terms of process, packaging or power supply criteria. These issues are resolved where appropriate in implementation specifications. 19.1.3 Audience
In particular this document provides the design reference for software authors who are responsible for creating a CAN application using this module. In the creation of the RCAN-ET user interface LSI engineers must use this document to understand the hardware requirements.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.1.4 1. 2. 3. 4.
References
CAN License Specification, Robert Bosch GmbH, 1992 CAN Specification Version 2.0 part A, Robert Bosch GmbH, 1991 CAN Specification Version 2.0 part B, Robert Bosch GmbH, 1991 Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany, 1997 5. Road vehicles - Controller area network (CAN): Part 1: Data link layer and physical signalling (ISO-11898-1, 2002) 19.1.5 * * * * * * * * * * * * Features
Supports CAN specification 2.0B Bit timing compliant with ISO-11898-1 16 Mailbox version Clock 16 to 40 MHz 15 programmable Mailboxes for transmit/receive + 1 receive-only mailbox Sleep mode for low power consumption and automatic recovery from sleep mode by detecting CAN bus activity Programmable receive filter mask (standard and extended identifier) supported by all Mailboxes Programmable CAN data rate up to 1MBit/s Transmit message queuing with internal priority sorting mechanism against the problem of priority inversion for real-time applications Data buffer access without SW handshake requirement in reception Flexible micro-controller interface Flexible interrupt structure
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.2
19.2.1
Architecture
Block Diagram
The RCAN-ET device offers a flexible and sophisticated way to organise and control CAN frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox, Mailbox Control and CAN Interface. The figure below shows the block diagram of the RCAN-ET Module. The bus interface timing is designed according to the peripheral bus I/F required for each product.
CRx CAN Interface REC Can Core TEC CTx
BCR
Transmit Buffer
Receive Buffer
Control Signals
Status Signals
Micro Processor Interface (MPI) MCR 16-bit peripheral bus GSR IRR IMR
TXPR TXCR
TXACK ABACK RFPR UMSR
32-bit internal Bus System
RXPR MBIMR
Mailbox Control
Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15
control0 LAFM DATA
Mailbox 0 to 15 (RAM)
Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15
control1
Mailbox 0 to 15 (register)
Figure 19.1 RCAN-ET Architecture
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Important: Although core of RCAN-ET is designed based on a 32-bit bus system, the whole RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord (32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual, LongWord access means the two consecutive accesses. 19.2.2 (1) Functions of Each Block
Micro Processor Interface (MPI)
The MPI allows communication between the Renesas CPU and RCAN-ET's registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-ET so that the RCAN-ET can automatically exit the Sleep mode. It contains registers such as MCR, IRR, GSR and IMR. (2) Mailbox
The Mailboxes consists of RAM configured as message buffers and registers. There are 16 Mailboxes, and each mailbox has the following information. * CAN message control (identifier, rtr, ide,etc) * CAN message data (for CAN Data frames) * Local Acceptance Filter Mask for reception * CAN message control (dlc) * 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, AutoTransmission for Remote Request bit, New Message Control bit
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
(3)
Mailbox Control
The Mailbox Control handles the following functions: * For received messages, compare the IDs and generate appropriate RAM addresses/data to store messages from the CAN Interface into the Mailbox and set/clear appropriate registers accordingly. * To transmit messages, RCAN-ET will run the internal arbitration to pick the correct priority message, and load the message from the Mailbox into the Tx-buffer of the CAN Interface and set/clear appropriate registers accordingly. * Arbitrates Mailbox accesses between the CPU and the Mailbox Control. * Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and MBIMR. (4) CAN Interface
This block conforms to the requirements for a CAN Bus Data Link Controller which is specified in Ref. [3, 5]. It fulfils all the functions of a standard Data Link Controller as specified by the OSI 7 Layer Reference model. This functional entity also provides the registers and the logic which are specific to a given CAN bus, which includes the Receive Error Counter, Transmit Error Counter, the Bit Configuration Registers and various useful Test Modes. This block also contains functional entities to hold the data received and the data to be transmitted for the CAN Data Link Controller. 19.2.3 Input/Output Pins
Table 19.1 shows the pin configuration of the RCAN-ET. Table 19.1 Pin Configuration
Channel 0 Name Transmit data pin Receive data pin 1 Transmit data pin Receive data pin Abbreviation CTx0 CRx0 CTx1 CRx1 I/O Output Input Output Input Function CAN-bus transmit pin CAN-bus receive pin CAN-bus transmit pin CAN-bus receive pin
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19.2.4
Memory Map
The diagram of the memory map is shown below.
Bit 15 H'000 H'002 H'004 H'006 H'008 H'00A H'00C Master Control Register (MCR) General Status Register(GSR) Bit timing Configuration Register 1 (BCR1) Bit timing Configuration Register 0 (BCR0) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Transmit Error Counter (TEC) Receive Error Counter (REC) H'100 H'0A4 Bit 0 H'0A0 Bit 15 Bit 0
H'020 H'022
Transmit Pending Register (TXPR1) Transmit Pending Register (TXPR0) H'104
Mailbox-0 Control 0 (STDID, EXTID, RTR, IDE)
LAFM
H'108 H'02A Transmit Cancel Register (TXCR0) H'10A H'10C H'032 Transmit Acknowledge Register (TXACK0) H'10E H'110
0 2
Mailbox 0 Data (8 bytes)
1 3 5 7
4 6
Mailbox-0 Control 1 (NMC, MBC, DLC) H'03A Abort Acknowledge Register (ABACK0) H'120 H'042 Data Frame Receive Pending Register (RXPR0) H'140 H'04A Mailbox-2 Control/LAFM/Data etc. Mailbox-1 Control/LAFM/Data etc.
Remote Frame Pending Register (RFPR0)
H'160
Mailbox-3 Control/LAFM/Data etc.
H'052
Mailbox Interrupt Mask Register (MBIMR0)
H'05A
Unread Message Status Register (UMSR0)
H'2E0
Mailbox-15 Control/LAFM/Data etc.
Note: The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed. Addresses shown above are offset addrsses. As for actual addresses, see section 30, List of Registers.
Figure 19.2 RCAN-ET Memory Map
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.3
19.3.1
Mailbox
Mailbox Structure
Mailboxes play a role as message buffers to transmit/receive CAN frames. Each Mailbox is comprised of 3 identical storage fields that are 1): Message Control, 2): Local Acceptance Filter Mask, 3): Message Data. The following table shows the address map for the control, LAFM, data and addresses for each mailbox. Table 19.2 Address Map for Each Mailbox
Address Control0 Mailbox 0 (Receive Only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 bytes H'100 to H'103 H'120 to H'123 H'140 to H'143 H'160 to H'163 H'180 to H'183 H'1A0 to H'1A3 H'1C0 to H'1C3 H'1E0 to H'1E3 H'200 to H'203 H'220 to H'223 H'240 to H'243 H'260 to H'263 H'280 to H'283 H'2A0 to H'2A3 H'2C0 to H'2C3 H'2E0 to H'2E3 LAFM 4 bytes H'104 to H'107 H'124 to H'127 H'144 to H'147 H'164 to H'167 H'184 to H'187 H'1A4 to H'1A7 H'1C4 to H'1C7 H'1E4 to H'1E7 H'204 to H'207 H'224 to H'227 H'244 to H'247 H'264 to H'267 H'284 to H'287 H'2A4 to H'2A7 H'2C4 to H'2C7 H'2E4 to H'2E7 Data 8 bytes H'108 to H'10F H'128 to H'12F H'148 to H'14F H'168 to H'16F H'188 to H'18F H'1A8 to H'1AF H'1C8 to H'1CF H'1E8 to H'1EF H'208 to H'20F H'228 to H'22F H'248 to H'24F H'268 to H'26F H'288 to H'28F H'2A8 to H'2AF H'2C8 to H'2CF H'2E8 to H'2EF Control1 2 bytes H'110 to H'111 H'130 to H'131 H'150 to H'151 H'170 to H'171 H'190 to H'191 H'1B0 to H'1B1 H'1D0 to H'1D1 H'1F0 to H'1F1 H'210 to H'211 H'230 to H'231 H'250 to H'251 H'270 to H'271 H'290 to H'291 H'2B0 to H'2B1 H'2D0 to H'2D1 H'2F0 to H'2F1
Mailbox-0 is a receive-only box, and all the other Mailboxes can operate as both receive and transmit boxes, dependant upon the MBC (Mailbox Configuration) bits in the Message Control. The following diagram shows the structure of a Mailbox in detail.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Table 19.3 Roles of Mailboxes
Tx MB15 to MB1 MB0 OK Rx OK OK
MB0 (reception MB) Regiter Name Address 15 MB[0].CONTROL0H MB[0].CONTROL0L MB[0].LAFMH MB[0].LAFML MB[0].MSG_DATA[0][1] MB[0].MSG_DATA[2][3] MB[0].MSG_DATA[4][5] MB[0].MSG_DATA[6][7] MB[0].CONTROL1H, L H'100 H'102 H'104 H'106 H'108 H'10A H'10C H'10E H'110 0 0 NMC
IDE_ LAFM
Byte: 8-bit access, Word: 16-bit access, LW (LongWord): 32-bit access Data Bus 14 RTR 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Word/LW Word
EXTID_ LAFM[17:16]
Access Size
Field Name
IDE
STDID[10:0] EXTID[15:0]
EXTID[17:16]
Control 0
0
0
STDID_LAFM[10:0] EXTID_LAFM[15:0]
Word/LW Word LAFM
MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 0 0 MBC[2:0] 0 0 0
MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 0 DLC[3:0]
Byte/Word/LW Byte/Word Byte/Word/LW Byte/Word Byte/Word Control 1 Data
MB1 to 15 (MB for transmission/reception) Register Name Address 15 MB[n].CONTROL0H MB[n].CONTROL0L MB[n].LAFMH MB[n].LAFML H'100 + n x 32 H'102 + n x 32 H'104 + n x 32 LAFM H'106 + n x 32
IDE_
Data Bus 14 RTR 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0
Access Size
Field Name
IDE
STDID[10:0] EXTID[15:0]
EXTID[17:16]
Word/LW Control 0 Word
0
0
STDID_LAFM[10:0] EXTID_LAFM[15:0]
EXTID_ LAFM[17:16]
Word/LW LAFM Word Byte/Word/LW Data Byte/Word Byte/Word/LW Byte/Word
MB[n].MSG_DATA[0][1] H'108 + n x 32 MB[n].MSG_DATA[2][3] H'10A + n x 32 MB[n].MSG_DATA[4][5] H'10C + n x 32 MB[n].MSG_DATA[6][7] H'10E + n x 32 MB[n].CONTROL1H, L H'110 + n x 32 Notes: 1. 2. 3. 4. 5. 0 0
MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_2 MSG_DATA_4 MSG_DATA_6 NMC ATX DART MBC[2:0] 0 0 0
MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 0 DLC[3:0]
Byte/Word
Control 1
All bits shadowed in grey are reserved and the write value should be 0. The value returned by a read may not always be 0 and should not be relied upon. MBC1 bit in mailbox is fixed to 1. ATX and DART are not supported by mailbox-0, and the MBC setting of mailbox-0 is limited. When the MCR15 bit is 1, the order of STDID, RTR, IDE and EXTID of both message control and LAFM differs from HCAN2. n = 0 to 15 (mailbox number)
Figure 19.3 Mailbox-n Structure
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.3.2
Message Control Field
STDID[10:0]: These bits set the identifier (standard identifier) of data frames and remote frames. EXTID[17:0]: These bits set the identifier (extended identifier) of data frames and remote frames. RTR (Remote Transmission Request bit): Used to distinguish between data frames and remote frames. This bit is overwritten by received CAN Frames depending on Data Frames or Remote Frames. Important: Please note that, when ATX bit is set with the setting MBC = B'001, the RTR bit will never be set. When a Remote Frame is received, the CPU can be notified by the corresponding RFPR set or IRR[2] (Remote Frame Request Interrupt), however, as RCAN-ET needs to transmit the current message as a Data Frame, the RTR bit remains unchanged. In case of overrun condition, the message received is discarded. Consequently, when a remote frame is causing overrun (UMSR is set) into a Mailbox configured with ATX = 1/NMC = 0, the transmission of the corresponding data frame is not carried out. Important: In order to support automatic answer to remote frame when MBC = B'001 is used and ATX = 1 the RTR flag must be programmed to zero to allow data frame to be transmitted. Note: when a Mailbox is configured to send a remote frame request the DLC used for transmission is the one stored into the Mailbox.
RTR 0 1 Description Data frame Remote frame
IDE (Identifier Extension bit): Used to distinguish between the standard format and extended format of CAN data frames and remote frames.
IDE 0 1 Description Standard format Extended format
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
* Mailbox-0
Bit: 15 0 Initial value: R/W: 0 R 14 0 0 R 13 NMC 0 R/W 12 0 0 R 11 0 0 R 1 R/W 10 9 MBC[2:0] 1 R/W 1 R/W 8 7 0 0 R 6 0 0 R 5 0 0 R 4 0 0 R 0 R/W 3 2 1 0 DLC[3:0] 0 R/W 0 R/W 0 R/W
Note: MBC[1] of MB0 is always "1". * Mailbox-15 to 1
Bit: 15 0 Initial value: R/W: 0 R 14 0 0 R 13 NMC 0 R/W 12 11 10 9 MBC[2:0] 1 R/W 1 R/W 1 R/W 8 7 0 0 R 6 0 0 R 5 0 0 R 4 0 0 R 0 R/W 3 2 1 0 ATX DART 0 R/W 0 R/W DLC[3:0] 0 R/W 0 R/W 0 R/W
NMC (New Message Control): When this bit is set to '0', the Mailbox of which the RXPR or RFPR bit is already set does not store the new message but maintains the old one and sets the UMSR correspondent bit. When this bit is set to '1', the Mailbox of which the RXPR or RFPR bit is already set overwrites with the new message and sets the UMSR correspondent bit. Important: Please note that if a remote frame is overwritten with a data frame or vice versa could be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this case the RTR bit within the Mailbox Control Field should be relied upon.
NMC 0 1 Description Overrun mode (Initial value) Overwrite mode
ATX (Automatic Transmission of Data Frame): When this bit is set to '1' and a Remote Frame is received into the Mailbox DLC is stored. Then, a Data Frame is transmitted from the same Mailbox using the current contents of the message data and updated DLC by setting the corresponding TXPR automatically. The scheduling of transmission is still governed by ID priority or Mailbox priority as configured with the Message Transmission Priority control bit (MCR.2). In order to use this function, MBC[2:0] needs to be programmed to be B'001. When a transmission is performed by this function, the DLC (Data Length Code) to be used is the one that has been received. Application needs to guarantee that the DLC of the remote frame correspond to the DLC of the data frame requested. Important: When ATX is used and MBC = B'001 the filter for the IDE bit cannot be used since ID of remote frame has to be exactly the same as that of data frame as the reply message.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Important: Please note that, when this function is used, the RTR bit will never be set despite receiving a Remote Frame. When a Remote Frame is received, the CPU will be notified by the corresponding RFPR set, however, as RCAN-ET needs to transmit the current message as a Data Frame, the RTR bit remains unchanged.
ATX 0 1 Description Automatic Transmission of Data Frame disabled (Initial value) Automatic Transmission of Data Frame enabled
DART (Disable Automatic Re-Transmission): When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. In effect, when this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is set to '0', RCAN-ET tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR.
DART 0 1 Description Re-transmission enabled (Initial value) Re-Transmission disabled
MBC[2:0] (Mailbox Configuration): These bits configure the nature of each Mailbox as follows. When MBC = B'111, the Mailbox is inactive, i.e., it does not receive or transmit a message regardless of TXPR or other settings. The MBC = B'110, B'101 and B'100 settings are prohibited. When the MBC is set to any other value, the LAFM field becomes available. Please don't set TXPR when MBC is set as reception. Similarly, please don't set TXPR, when MBC is set as remote frame transmission and RTR in Mailbox is cleared. There is no hardware protection, and TXPR remains set. MBC[1] of Mailbox-0 is fixed to "1" by hardware. This is to ensure that MB0 cannot be configured to transmit Messages.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Table 19.4 Mailbox Function Setting
Data Frame MBC[2] MBC[1] MBC[0] Transmit Remote Frame Transmit Data Frame Receive Remote Frame Receive
Remarks
0 0
0 0
0 1
Yes Yes
Yes Yes
No No
No Yes
* * * *
Not allowed for Mailbox-0 Can be used with ATX* Not allowed for Mailbox-0 LAFM can be used Allowed for Mailbox-0 LAFM can be used Allowed for Mailbox-0 LAFM can be used
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
No No
No No
Yes Yes
Yes No
* * * *
Setting prohibited Setting prohibited Setting prohibited Mailbox inactive (Initial value)
Notes: *
In order to support automatic retransmission, RTR shall be "0" when MBC = B'001 and ATX = 1. When ATX = 1 is used the filter for IDE must not be used
DLC[3:0] (Data Length Code): These bits encode the number of data bytes from 0,1, 2, ... 8 that will be transmitted in a data frame. Please note that when a remote frame request is transmitted the DLC value to be used must be the same as the DLC of the data frame that is requested.
DLC[3] 0 0 0 0 0 0 0 0 1 DLC[2] 0 0 0 0 1 1 1 1 x DLC[1] 0 0 1 1 0 0 1 1 x DLC[0] 0 1 0 1 0 1 0 1 x Description Data Length = 0 byte (Initial value) Data Length = 1 byte Data Length = 2 bytes Data Length = 3 bytes Data Length = 4 bytes Data Length = 5 bytes Data Length = 6 bytes Data Length = 7 bytes Data Length = 8 bytes
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.3.3
Local Acceptance Filter Mask (LAFM)
This area is used as Local Acceptance Filter Mask (LAFM) for receive boxes. LAFM: When MBC is set to B'001, B'010, B'011, this field is used as LAFM Field. The LAFM is comprised of two 16-bit read/write areas as follows. It allows a Mailbox to accept more than one identifier.
15 Address IDE_ H'104 + n x 32 LAFM 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0
Register Name MB[n].LAFMH MB[n].LAFML
Acces Size Word/LW
Feld Name LAFM Field
STDID_LAFM[10:0] EXTID_LAFM[15:0]
EXTID_ LAFM[17:16]
H'106 + n x 32
Word
Note: n = 0 to 15 (mailbox number)
Figure 19.4 Acceptance Filter If a bit is set in the LAFM, then the corresponding bit of a received CAN identifier is ignored when the RCAN-ET searches a Mailbox with the matching CAN identifier. If the bit is cleared, then the corresponding bit of a received CAN identifier must match to the STDID/IDE/EXTID set in the mailbox to be stored. The structure of the LAFM is same as the message control in a Mailbox. If this function is not required, it must be filled with '0'. Important: RCAN-ET starts to find a matching identifier from Mailbox-15 down to Mailbox-0. As soon as RCAN-ET finds one matching, it stops the search. The message will be stored or not depending on the NMC and RXPR/RFPR flags. This means that, even using LAFM, a received message can only be stored into 1 Mailbox. Important: When a message is received and a matching Mailbox is found, the whole message is stored into the Mailbox. This means that, if the LAFM is used, the STDID, RTR, IDE and EXTID may differ to the ones originally set as they are updated with the STDID, RTR, IDE and EXTID of the received message. STD_LAFM[10:0] -- Filter mask bits for the CAN base identifier [10:0] bits.
STD_LAFM[10:0] 0 1 Description Corresponding STD_ID bit is cared Corresponding STD_ID bit is "don't cared"
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
EXT_LAFM[17:0] -- Filter mask bits for the CAN Extended identifier [17:0] bits.
EXT_LAFM[17:0] 0 1 Description Corresponding EXT_ID bit is cared Corresponding EXT_ID bit is "don't cared"
IDE_LAFM -- Filter mask bit for the CAN IDE bit.
IDE_LAFM 0 1 Description Corresponding IDE_ID bit is cared Corresponding IDE_ID bit is "don't cared"
19.3.4
Message Data Fields
Storage for the CAN message data that is transmitted or received. MSG_DATA[0] corresponds to the first data byte that is transmitted or received. The bit order on the CAN bus is bit 7 through to bit 0.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.4
RCAN-ET Control Registers
The following sections describe RCAN-ET control registers. The address is mapped as follow. Important: These registers can only be accessed in Word size (16-bit). Table 19.5 RCAN-ET Control Registers Configuration
Description Master Control Register General Status Register Baud Rate Configuration Register 1 Baud Rate Configuration Register 0 Interrupt Request Register Interrupt Mask Register Error Counter Register Address 000 002 004 006 008 00A 00C Name MCR GSR BCR1 BCR0 IRR IMR TEC/REC Access Size (bits) Word Word Word Word Word Word Word
19.4.1
Master Control Register (MCR)
The Master Control Register (MCR) is a 16-bit read/write register that controls RCAN-ET. * MCR (Address = H'000)
Bit: 15 14 13
--
12
--
11
--
10
9
TST[2:0]
8
7
6
5
4
--
3
--
2
1
0
MCR15 MCR14
MCR7 MCR6 MCR5
MCR2 MCR1 MCR0
Initial value: 1 R/W: R/W
0 R/W
0 R
0 R
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
0 R/W
0 R/W
1 R/W
Bit 15 -- ID Reorder (MCR15): This bit changes the order of STDID, RTR, IDE and EXTID of both message control and LAFM.
Bit15: MCR15 0 1 Description RCAN-ET is the same as HCAN2 RCAN-ET is not the same as HCAN2 (Initial value)
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
MCR15 (ID Reorder) = 0 Address H'100 + n x 32 H'102 + n x 32 H'104 + n x 32 H'106 + n x 32
0
15
0
14
13
12
11
10
9
STDID[10:0]
8
7
6
5
4
3
RTR
2
IDE
1
0
Access Size Word/LW
Feld Name Control 0
EXTID[17:16]
EXTID[15:0] STDID_LAFM[10:0] EXTID_LAFM[15:0] 0
IDE_ LAFM EXTID_LAFM [17:16]
Word Word/LW LAFM Field Word
MCR15 (ID Reorder) = 1 Address H'100 + n x 32 H'102 + n x 32 H'104 + n x 32 H'106 + n x 32 Note: n = 0 to 15 (mailbox number)
IDE_ LAFM
15
IDE
14
RTR
13
0
12
11
10
9
8
7
STDID[10:0]
6
5
4
3
2
1
0
Access Size Word/LW
Feld Name Control 0
EXTID[17:16]
EXTID[15:0] 0 0 STDID_LAFM[10:0] EXTID_LAFM[15:0]
EXTID_LAFM [17:16]
Word Word/LW LAFM Field Word
Figure 19.5 ID Reorder This bit can be modified only in reset mode. Bit 14 -- Auto Halt Bus Off (MCR14): If both this bit and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters BusOff.
Bit14: MCR14 0 1 Description RCAN-ET remains in BusOff for normal recovery sequence (128 x 11 Recessive Bits) (Initial value) RCAN-ET moves directly into Halt Mode after it enters BusOff if MCR6 is set.
This bit can be modified only in reset mode. Bit 13 -- Reserved. The written value should always be '0' and the returned value is '0'. Bit 12 -- Reserved. The written value should always be '0' and the returned value is '0'. Bit 11 -- Reserved. The written value should always be '0' and the returned value is '0'.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Bit 10 - 8 -- Test Mode (TST[2:0]): This bit enables/disables the test modes. Please note that before activating the Test Mode it is requested to move RCAN-ET into Halt mode or Reset mode. This is to avoid that the transition to Test Mode could affect a transmission/reception in progress. For details, please refer to section 19.6.2, Test Mode Settings. Please note that the test modes are allowed only for diagnosis and tests and not when RCAN-ET is used in normal operation.
Bit10: TST2 0 0 0 0 1 1 1 1 Bit9: TST1 0 0 1 1 0 0 1 1 Bit8: TST0 0 1 0 1 0 1 0 1 Description Normal mode (initial value) Listen-only mode (receive-only mode) Self test mode 1 (external) Self test mode 2 (internal) Write error counter Error passive mode Setting prohibited Setting prohibited
Bit 7 -- Auto-wake Mode (MCR7): MCR7 enables or disables the Auto-wake mode. If this bit is set, the RCAN-ET automatically cancels the sleep mode (MCR5) by detecting CAN bus activity (dominant bit). If MCR7 is cleared the RCAN-ET does not automatically cancel the sleep mode. RCAN-ET cannot store the message that wakes it up. Note: MCR7 cannot be modified while in sleep mode.
Bit7: MCR7 0 1 Description Auto-wake by CAN bus activity disabled (Initial value) Auto-wake by CAN bus activity enabled
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Bit 6 -- Halt during Bus Off (MCR6): MCR6 enables or disables entering Halt mode immediately when MCR1 is set during Bus Off. This bit can be modified only in Reset or Halt mode. Please note that when Halt is entered in Bus Off the CAN engine is also recovering immediately to Error Active mode.
Bit6: MCR6 0 1 Description Don't enter Halt mode during Bus Off but wait up to end of recovery sequence (Initial value) Enter Halt mode immediately during Bus Off if MCR[1] or MCR[14] are asserted.
Bit 5 -- Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while RCAN-ET is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep mode. This mode will be exited in two ways: 1. by writing a '0' to this bit position, 2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus. If Auto wake up mode is disabled, RCAN-ET will ignore all CAN bus activities until the sleep mode is terminated. When leaving this mode the RCAN-ET will synchronise to the CAN bus (by checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2 method is used, RCAN-ET will miss the first message to receive. CAN transceivers stand-by mode will also be unable to cope with the first message when exiting stand by mode, and the S/W needs to be designed in this manner. In sleep mode only the following registers can be accessed: MCR, GSR, IRR and IMR. Important: RCAN-ET is required to be in Halt mode before requesting to enter in Sleep mode. That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts are cleared RCAN-ET must leave the Halt mode and enter Sleep mode simultaneously (by writing MCR[5] = 1 and MCR[1] = 0 at the same time).
Bit 5: MCR5 0 1 Description RCAN-ET sleep mode released (Initial value) Transition to RCAN-ET sleep mode enabled
Bit 4 -- Reserved. The written value should always be '0' and the returned value is '0'.
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Bit 3 -- Reserved. The written value should always be '0' and the returned value is '0'. Bit 2 -- Message Transmission Priority (MCR2): MCR2 selects the order of transmission for pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-15 as the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for transmission). If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE bit + EXTID (if IDE = 1) + RTR bit) with the lowest digital value and is transmitted first. The internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same way as the arbitration on the CAN Bus between two CAN nodes starting transmission at the same time). This bit can be modified only in Reset or Halt mode.
Bit 2: MCR2 0 1 Description Transmission order determined by message identifier priority (Initial value) Transmission order determined by mailbox number priority (Mailbox-15 Mailbox-1)
Bit 1--Halt Request (MCR1): Setting the MCR1 bit causes the CAN controller to complete its current operation and then enter Halt mode (where it is cut off from the CAN bus). The RCAN-ET remains in Halt Mode until the MCR1 is cleared. During the Halt mode, the CAN Interface does not join the CAN bus activity and does not store messages or transmit messages. All the user registers (including Mailbox contents and TEC/REC) remain unchanged with the exception of IRR0 and GSR4 which are used to notify the halt status itself. If the CAN bus is in idle or intermission state regardless of MCR6, RCAN-ET will enter Halt Mode within one Bit Time. If MCR6 is set, a halt request during Bus Off will be also processed within one Bit Time. Otherwise the full Bus Off recovery sequence will be performed beforehand. Entering the Halt Mode can be notified by IRR0 and GSR4. If both MCR14 and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters BusOff. In the Halt mode, the RCAN-ET configuration can be modified with the exception of the Bit Timing setting, as it does not join the bus activity. MCR[1] has to be cleared by writing a '0' in order to re-join the CAN bus. After this bit has been cleared, RCAN-ET waits until it detects 11 recessive bits, and then joins the CAN bus.
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Note: After issuing a Halt request the CPU is not allowed to set TXPR or TXCR or clear MCR1 until the transition to Halt mode is completed (notified by IRR0 and GSR4). After MCR1 is set this can be cleared only after entering Halt mode or through a reset operation (SW or HW). Note: Transition into or recovery from Halt mode, is only possible if the BCR1 and BCR0 registers are configured to a proper Baud Rate.
Bit 1: MCR1 0 1 Description Clear Halt request (Initial value) Halt mode transition request
Bit 0 -- Reset Request (MCR0): Controls resetting of the RCAN-ET module. When this bit is changed from '0' to '1' the RCAN-ET controller enters its reset routine, re-initialising the internal logic, which then sets GSR3 and IRR0 to notify the reset mode. During a re-initialisation, all user registers are initialised. RCAN-ET can be re-configured while this bit is set. This bit has to be cleared by writing a '0' to join the CAN bus. After this bit is cleared, the RCAN-ET module waits until it detects 11 recessive bits, and then joins the CAN bus. The Baud Rate needs to be set up to a proper value in order to sample the value on the CAN Bus. After Power On Reset, this bit and GSR3 are always set. This means that a reset request has been made and RCAN-ET needs to be configured. The Reset Request is equivalent to a Power On Reset but controlled by Software.
Bit 0: MCR0 0 1 Description Clear Reset Request CAN Interface reset mode transition request (Initial value)
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19.4.2
General Status Register (GSR)
The General Status Register (GSR) is a 16-bit read-only register that indicates the status of RCAN-ET. * GSR (Address = H'002)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 4 3 2 1 0 GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 0 R 0 R 1 R 1 R 0 R 0 R
Bits 15 to 6: Reserved. The written value should always be '0' and the returned value is '0'. Bit 5 -- Error Passive Status Bit (GSR5): Indicates whether the CAN Interface is in Error Passive or not. This bit will be set high as soon as the RCAN-ET enters the Error Passive state and is cleared when the module enters again the Error Active state (this means the GSR5 will stay high during Error Passive and during Bus Off). Consequently to find out the correct state both GSR5 and GSR0 must be considered.
Bit 5: GSR5 0 1 Description RCAN-ET is not in Error Passive or in Bus Off status (Initial value) [Reset condition] RCAN-ET is in Error Active state RCAN-ET is in Error Passive (if GSR0 = 0) or Bus Off (if GSR0 = 1) [Setting condition] When TEC 128 or REC 128 or if Error Passive Test Mode is selected
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Bit 4 -- Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep state or not. Please note that the clearing time of this flag is not the same as the setting time of IRR12. Please note that this flag reflects the status of the CAN engine and not of the full RCAN-ET IP. RCAN-ET exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits sleep mode only after two additional transmission clocks on the CAN Bus.
Bit 4: GSR4 0 1 Description RCAN-ET is not in the Halt state or Sleep state (Initial value) Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1) [Setting condition] If MCR1 is set and the CAN bus is either in intermission or idle or MCR5 is set and RCAN-ET is in the halt mode or RCAN-ET is moving to Bus Off when MCR14 and MCR6 are both set
Bit 3 -- Reset Status Bit (GSR3): Indicates whether the RCAN-ET is in the reset state or not.
Bit 3: GSR3 0 1 Description RCAN-ET is not in the reset state Reset state (Initial value) [Setting condition] After an RCAN-ET internal reset (due to SW or HW reset)
Bit 2 -- Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if the RCAN-ET is in Bus Off or transmitting a message or an error/overload flag due to error detected during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK is set at the 7th bit of End Of Frame. GSR2 is set at the 3rd bit of intermission if there are no more messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset or halt transition.
Bit 2: GSR2 0 1 Description RCAN-ET is in Bus Off or a transmission is in progress [Setting condition] Not in Bus Off and no transmission in progress (Initial value)
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Bit 1--Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning.
Bit 1: GSR1 0 1 Description [Reset condition] When (TEC < 96 and REC < 96) or Bus Off (Initial value) [Setting condition] When 96 TEC < 256 or 96 REC < 256
Note: REC is incremented during Bus Off to count the recurrences of 11 recessive bits as requested by the Bus Off recovery sequence. However the flag GSR1 is not set in Bus Off. Bit 0--Bus Off Flag (GSR0): Flag that indicates that RCAN-ET is in the bus off state.
Bit 0: GSR0 0 1 Description [Reset condition] Recovery from bus off state or after a HW or SW reset (Initial value) [Setting condition] When TEC 256 (bus off state)
Note: Only the lower 8 bits of TEC are accessible from the user interface. The 9th bit is equivalent to GSR0.
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19.4.3
Bit Configuration Register (BCR0, BCR1)
The bit configuration registers (BCR0 and BCR1) are 2 x 16-bit read/write register that are used to set CAN bit timing parameters and the baud rate pre-scaler for the CAN Interface. The Time quanta is defined as:
Timequanta = 2 x BRP fclk
Where: BRP (Baud Rate Pre-scaler) is the value stored in BCR0 incremented by 1 and fclk is the used peripheral bus frequency. * BCR1 (Address = H'004)
Bit: 15 14 13 12 11 -- 0 R/W 0 R 10 9 TSG2[2:0] 0 R/W 0 R/W 0 R/W 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 BSP 0 R/W TSG1[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W SJW[1:0] 0 R/W 0 R/W
Please refer to the table below for TSG1 and TSG2 setting. Bits 15 to 12 -- Time Segment 1 (TSG1[3:0] = BCR1[15:12]): These bits are used to set the segment TSEG1 ( = PRSEG + PHSEG1) to compensate for edges on the CAN Bus with a positive phase error. A value from 4 to 16 time quanta can be set.
Bit 15: Bit 14: Bit 13: Bit 12: TSG1[3] TSG1[2] TSG1[1] TSG1[0] Description 0 0 0 0 0 : : 1 0 0 0 0 1 : : 1 0 0 1 1 0 : : 1 0 1 0 1 0 : : 1 Setting prohibited (Initial value) Setting prohibited Setting prohibited PRSEG + PHSEG1 = 4 time quanta PRSEG + PHSEG1 = 5 time quanta : : PRSEG + PHSEG1 = 16 time quanta
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Bit 11: Reserved. The written value should always be '0' and the returned value is '0'. Bits 10 to 8 -- Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the segment TSEG2 ( = PHSEG2) to compensate for edges on the CAN Bus with a negative phase error. A value from 2 to 8 time quanta can be set as shown below.
Bit 10: Bit 9: Bit 8: TSG2[2] TSG2[1] TSG2[0] Description 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Setting prohibited (Initial value) PHSEG2 = 2 time quanta (conditionally prohibited) See the table below for TSG1 and TSG2 setting. PHSEG2 = 3 time quanta PHSEG2 = 4 time quanta PHSEG2 = 5 time quanta PHSEG2 = 6 time quanta PHSEG2 = 7 time quanta PHSEG2 = 8 time quanta
Bits 7 and 6: Reserved. The written value should always be '0' and the returned value is '0'. Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the synchronisation jump width.
Bit 5: SJW[1] 0 0 1 1 Bit 4: SJW[0] 0 1 0 1 Description Synchronisation Jump width = 1 time quantum (Initial value) Synchronisation Jump width = 2 time quanta Synchronisation Jump width = 3 time quanta Synchronisation Jump width = 4 time quanta
Bits 3 to 1: Reserved. The written value should always be '0' and the returned value is '0'.
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Bit 0 -- Bit Sample Point (BSP = BCR1[0]): Sets the point at which data is sampled. Three-time sampling is only available when the BRP is programmed to be greater than 4.
Bit 0: BSP 0 1 Description Bit sampling at one point (end of time segment 1) (Initial value) Bit sampling at three points (rising edge of the last three clock cycles of PHSEG1)
* BCR0 (Address = H'006)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 BRP[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bits 8 to 15 : Reserved. The written value should always be '0' and the returned value is '0'. Bits 7 to 0--Baud Rate Pre-scale (BRP[7:0] = BCR0 [7:0]): These bits are used to define the peripheral bus clock periods contained in a Time Quantum.
Bit 7: BRP[7] Bit 6: BRP[6] Bit 5: BRP[5] Bit 4: BRP[4] Bit 3: BRP[3] Bit 2: BRP[2] Bit 1: BRP[1] Bit 0: BRP[0]
Description
0 0 0 : : 1
0 0 0 : : 1
0 0 0 : : 1
0 0 0 : : 1
0 0 0 : : 1
0 0 0 : : 1
0 0 1 : : 1
0 1 0 : : 1
2 x peripheral bus clock (Initial value) 4 x peripheral bus clock 6 x peripheral bus clock 2 x (register value+1) x peripheral bus clock 512 x peripheral bus clock
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* Requirements of Bit Configuration Register
1-bit time (8 to 25 quanta) SYNC_SEG PRSEG PHSEG1 TSEG1 1 4-16
PHSEG2
TSEG2 2-8 Quantum
SYNC_SEG: Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: PHSEG1: Segment for compensating for physical delay between networks. Buffer segment for correcting phase drift (positive). (This segment is extended when synchronisation (resynchronisation) is established.) Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronisation (resynchronisation) is established) TSG1 + 1 TSG2 + 1
PHSEG2:
TSEG1: TSEG2:
The RCAN-ET Bit Rate Calculation is:
Bit Rate = fclk 2 x (BRP + 1) x (TSEG1 + TSEG2 + 1)
where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1 and TSG2 register values.
fCLK = Peripheral Clock
BCR Setting Constraints
TSEG1min > TSEG2 SJWmax (SJW = 1 to 4)
8 TSEG1 + TSEG2 + 1 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed) TSEG2 2
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These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows that there is no allowed combination of TSEG1 and TSEG2. Table 19.6 TSG and TSEG Setting
001 2 TSG1 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TSEG1 4 5 6 7 8 9 10 11 12 13 14 15 16 No 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 1-3 No 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 No No 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 No No No 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 No No No No 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 No No No No No 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 010 3 011 4 100 5 101 6 110 7 111 8 TSG2 TSEG2
Example 1: To have a Bit rate of 500 Kbps with a frequency of fclk = 40 MHz it is possible to set: BRP = 3, TSEG1 = 6, TSEG2 = 3. Then the configuration to write is BCR1 = H'5200 and BCR0 = H'0003. Example 2: To have a Bit rate of 250 Kbps with a frequency of fclk = 35 MHz it is possible to set: BRP = 4, TSEG1 = 8, TSEG2 = 5. Then the configuration to write is BCR1 = H'7400 and BCR0 = H'0004.
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19.4.4
Interrupt Request Register (IRR)
The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the various interrupt sources. * IRR (Address = H'008)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 6 5 4 3 2 1 0 IRR13 IRR12 0 R/W 0 R/W IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 R/W
Bits 15 to 14: Reserved. Bit 13 - Message Error Interrupt (IRR13): This interrupt indicates that: * A message error has occurred when in test mode. * Note: If a Message Overload condition occurs when in Test Mode, then this bit will not be set. When not in test mode this interrupt is inactive.
Bit 13: IRR13 0 1 Description message error has not occurred in test mode (Initial value) [Clearing condition] Writing 1 [Setting condition] message error has occurred in test mode
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Bit 12 - Bus Activity while in Sleep Mode (IRR12): IRR12 indicates that a CAN bus activity is present. While the RCAN-ET is in sleep mode and a dominant bit is detected on the CAN bus, this bit is set. This interrupt is cleared by writing a '1' to this bit position. Writing a '0' has no effect. If auto wakeup is not used and this interrupt is not requested it needs to be disabled by the related interrupt mask register. If auto wake up is not used and this interrupt is requested it should be cleared only after recovering from sleep mode. This is to avoid that a new falling edge of the reception line causes the interrupt to get set again. Please note that the setting time of this interrupt is different from the clearing time of GSR4.
Bit 12: IRR12 0 1 Description bus idle state (Initial value) [Clearing condition] Writing 1 CAN bus activity detected in RCAN-ET sleep mode [Setting condition] dominant bit level detection on the CRx line while in sleep mode
Bits 11 to 10: Reserved Bit 9 - Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has been received but the existing message in the matching Mailbox has not been read as the corresponding RXPR or RFPR is already set to '1' and not yet cleared by the CPU. The received message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message Control) bit. This bit is cleared when all bit in UMSR (Unread Message Status Register) are cleared (by writing '1') or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set . It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position has no effect.
Bit 9: IRR9 0 Description No pending notification of message overrun/overwrite [Clearing condition] Clearing of all bit in UMSR/setting MBIMR for all UMSR set (initial value) 1 A receive message has been discarded due to overrun condition or a message has been overwritten [Setting condition] Message is received while the corresponding RXPR and/or RFPR = 1 and MBIMR = 0
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Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for transmission has been successfully sent (corresponding TXACK flag is set) or has been successfully aborted (corresponding ABACK flag is set). The related TXPR is also cleared and this mailbox is now ready to accept a new message data for the next transmission. In effect, this bit is set by an OR'ed signal of the TXACK and ABACK bits not masked by the corresponding MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and ABACK bits are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position has no effect.
Bit 8: IRR8 0 Description Messages set for transmission or transmission cancellation request NOT progressed. (Initial value) [Clearing Condition] All the TXACK and ABACK bits are cleared/setting MBIMR for all TXACK and ABACK set 1 Message has been transmitted or aborted, and new message can be stored [Setting condition] When one of the TXPR bits is cleared by completion of transmission or completion of transmission abort, i.e., when a TXACK or ABACK bit is set (if MBIMR = 0).
Bit 7 - Overload Frame (IRR7): Flag indicating that the RCAN-ET has detected a condition that should initiate the transmission of an overload frame. Note that on the condition of transmission being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7 will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0' has no effect.
Bit 7: IRR7 0 1 Description [Clearing condition] Writing 1 (Initial value) [Setting conditions] Overload condition detected
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Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when RCAN-ET enters the Bus-off state or when RCAN-ET leaves Bus-off and returns to Error-Active. The cause therefore is the existing condition TEC 256 at the node or the end of the Bus-off recovery sequence (128 x 11 consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit remains set even if the RCAN-ET node leaves the bus-off condition, and needs to be explicitly cleared by S/W. The S/W is expected to read the GSR0 to judge whether RCAN-ET is in the busoff or error active status. It is cleared by writing a '1' to this bit position even if the node is still bus-off. Writing a '0' has no effect.
Bit 6: IRR6 0 1 Description [Clearing condition] Writing 1 (Initial value) Enter Bus off state caused by transmit error or Error Active state returning from Bus-off [Setting condition] When TEC becomes 256 or End of Bus-off after 128x 11 consecutive recessive bits or transition from Bus Off to Halt
Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge whether RCAN-ET is in Error Passive or Bus Off status.
Bit 5: IRR5 0 1 Description [Clearing condition] Writing 1 (Initial value) Error passive state caused by transmit/receive error [Setting condition] When TEC 128 or REC 128 or Error Passive test mode is used
Bit 4 - Receive Error Counter Warning Interrupt Flag (IRR4): This bit becomes set if the receive error counter (REC) reaches a value greater than 95 when RCAN-ET is not in the Bus Off status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
Bit 4: IRR4 0 1 Description [Clearing condition] Writing 1 (Initial value) Error warning state caused by receive error [Setting condition] When REC 96 and RCAN-ET is not in Bus Off
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Bit 3 - Transmit Error Counter Warning Interrupt Flag (IRR3): This bit becomes set if the transmit error counter (TEC) reaches a value greater than 95. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
Bit 3: IRR3 0 1 Description [Clearing condition] Writing 1 (Initial value) Error warning state caused by transmit error [Setting condition] When TEC 96
Bit 2 - Remote Frame Request Interrupt Flag (IRR2): Flag indicating that a remote frame has been received in a mailbox. This bit is set if at least one receive mailbox, with related MBIMR not set, contains a remote frame transmission request. This bit is automatically cleared when all bits in the Remote Frame Receive Pending Register (RFPR), are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Bit 2: IRR2 0 1 Description [Clearing condition] Clearing of all bits in RFPR (Initial value) at least one remote request is pending [Setting condition] When remote frame is received and the corresponding MBIMR = 0
Bit 1 - Data Frame Received Interrupt Flag (IRR1): IRR1 indicates that there are pending Data Frames received. If this bit is set at least one receive mailbox contains a pending message. This bit is cleared when all bits in the Data Frame Receive Pending Register (RXPR) are cleared, i.e. there is no pending message in any receiving mailbox. It is in effect a logical OR of the RXPR flags from each configured receive mailbox with related MBIMR not set. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Bit 1: IRR1 0 1 Description [Clearing condition] Clearing of all bits in RXPR (Initial value) Data frame received and stored in Mailbox [Setting condition] When data is received and the corresponding MBIMR = 0
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Bit 0 - Reset/Halt/Sleep Interrupt Flag (IRR0): This flag can get set for three different reasons. It can indicate that: 1. Reset mode has been entered after a SW (MCR0) or HW reset 2. Halt mode has been entered after a Halt request (MCR1) 3. Sleep mode has been entered after a sleep request (MCR5) has been made while in Halt mode. The GSR may be read after this bit is set to determine which state RCAN-ET is in. Important: When a Sleep mode request needs to be made, the Halt mode must be used beforehand. Please refer to the MCR5 description and figure 19.8. IRR0 is set by the transition from "0" to "1" of GSR3 or GSR4 or by transition from Halt mode to Sleep mode. So, IRR0 is not set if RCAN-ET enters Halt mode again right after exiting from Halt mode, without GSR4 being cleared. Similarly, IRR0 is not set by direct transition from Sleep mode to Halt Request. At the transition from Halt/Sleep mode to Transition/Reception, clearing GSR4 needs (one-bit time - TSEG2) to (one-bit time * 2 - TSEG2). In the case of Reset mode, IRR0 is set, however, the interrupt to the CPU is not asserted since IMR0 is automatically set by initialisation.
Bit 0: IRR0 0 1 Description [Clearing condition] Writing 1 Transition to S/W reset mode or transition to halt mode or transition to sleep mode (Initial value) [Setting condition] When reset/halt/sleep transition is completed after a reset (MCR0 or HW) or Halt mode (MCR1) or Sleep mode (MCR5) is requested
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19.4.5
Interrupt Mask Register (IMR)
The interrupt mask register is a 16-bit register that protects all corresponding interrupts in the Interrupt Request Register (IRR) from generating an output signal on the IRQ. An interrupt request is masked if the corresponding bit position is set to '1'. This register can be read or written at any time. The IMR directly controls the generation of IRQ, but does not prevent the setting of the corresponding bit in the IRR. * IMR (Address = H'00A)
Bit: 15 14 13 12 11 10 9 8
IMR8
7
IMR7
6
IMR6
5
IMR5
4
IMR4
3
IMR3
2
IMR2
1
IMR1
0
IMR0
IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9
Initial value: 1 R/W: R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 15 to 0: Maskable interrupt sources corresponding to IRR[15:0] respectively. When a bit is set, the interrupt signal is not generated, although setting the corresponding IRR bit is still performed.
Bit[15:0]: IMRn 0 1 Description Corresponding IRR is not masked (IRQ is generated for interrupt conditions) Corresponding interrupt of IRR is masked (Initial value)
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.4.6
Transmit Error Counter (TEC) and Receive Error Counter (REC)
The Transmit Error Counter (TEC) and Receive Error Counter (REC) is a 16-bit read/(write) register that functions as a counter indicating the number of transmit/receive message errors on the CAN Interface. The count value is stipulated in the CAN protocol specification Refs. [2], [3], [4] and [5]. When not in (Write Error Counter) test mode this register is read only, and can only be modified by the CAN Interface. This register can be cleared by a Reset request (MCR0) or entering to bus off. In Write Error Counter test mode (i.e. TST[2:0] = B'100), it is possible to write to this register. The same value can only be written to TEC/REC, and the value written into TEC is set to TEC and REC. When writing to this register, RCAN-ET needs to be put into Halt Mode. This feature is only intended for test purposes. * TEC/REC (Address = H'00C)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * It is only possible to write the value in test mode when TST[2:0] in MCR is B'100. REC is incremented during Bus Off to count the recurrences of 11 recessive bits as requested by the Bus Off recovery sequence.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5
RCAN-ET Mailbox Registers
The following sections describe RCAN-ET Mailbox registers that control/flag individual Mailboxes. The address is mapped as follows. Important: LongWord access is carried out as two consecutive Word accesses. Table 19.7 RCAN-ET Mailbox Registers
Description Transmit Pending 1 Transmit Pending 0 Address H'020 H'022 H'024 H'026 H'028 Transmit Cancel 0 H'02A H'02C H'02E H'030 Transmit Acknowledge 0 H'032 H'034 H'036 H'038 Abort Acknowledge 0 H'03A H'03C H'03E H'040 Data Frame Receive Pending 0 H'042 H'044 H'046 H'048 Remote Frame Receive Pending 0 H'04A H'04C H'04E H'050 RFPR0 Word RXPR0 Word ABACK0 Word TXACK0 Word TXCR0 Name TXPR1 TXPR0 Access Size (bits) LW
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Description Mailbox Interrupt Mask Register 0
Address H'052 H'054 H'056 H'058
Name MBIMR0
Access Size (bits) Word
Unread Message Status Register 0 H'05A H'05C H'05E
UMSR0
Word
19.5.1
Transmit Pending Register (TXPR0, TXPR1)
The concatenation of TXPR0 and TXPR1 is a 32-bit register that contains any transmit pending flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as two consecutive word accesses.
16-bit peripheral bus 16-bit peripheral bus
Consecutive access Temp Temp
TXPR1 H'020
TXPR0 H'022
TXPR1 H'020
TXPR0 H'022
Data is stored into Temp instead of TXPR1.
Lower word data is stored into TXPR0. TXPR1 is always H'0000.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

16-bit peripheral bus 16-bit peripheral bus
Consecutive access Always H'0000 TXPR1 H'020 Temp Temp
TXPR0 H'022
TXPR1 H'020
TXPR0 H'022
TXPR0 is stored into Temp, when TXPR1 (= H'0000) is read.
Temp is read instead of TXPR0.
The TXPR1 register cannot be modified and it is always fixed to '0'. The TXPR0 controls Mailbox-15 to Mailbox-1. The CPU may set the TXPR bits to affect any message being considered for transmission by writing a '1' to the corresponding bit location. Writing a '0' has no effect, and TXPR cannot be cleared by writing a '0' and must be cleared by setting the corresponding TXCR bits. TXPR may be read by the CPU to determine which, if any, transmissions are pending or in progress. In effect there is a transmit pending bit for all Mailboxes except for the Mailbox-0. Writing a '1' to a bit location when the mailbox is not configured to transmit is not allowed. The RCAN-ET will clear a transmit pending flag after successful transmission of its corresponding message or when a transmission abort is requested successfully from the TXCR. The TXPR flag is not cleared if the message is not transmitted due to the CAN node losing the arbitration process or due to errors on the CAN bus, and RCAN-ET automatically tries to transmit it again unless its DART bit (Disable Automatic Re-Transmission) is set in the Message-Control of the corresponding Mailbox. In such case (DART set), the transmission is cleared and notified through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit within the Abort Acknowledgement Register (ABACK). If the status of the TXPR changes, the RCAN-ET shall ensure that in the identifier priority scheme (MCR2 = 0), the highest priority message is always presented for transmission in an intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus. Please refer to section 19.6, Application Note, for details.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
When the RCAN-ET changes the state of any TXPR bit position to a '0', an empty slot interrupt (IRR8) may be generated. This indicates that either a successful or an aborted mailbox transmission has just been made. If a message transmission is successful it is signalled in the TXACK register, and if a message transmission abortion is successful it is signalled in the ABACK register. By checking these registers, the contents of the Message of the corresponding Mailbox may be modified to prepare for the next transmission. * TXPR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXPR1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Any write operation is ignored. Read value is always H'0000. Long word access is mandatory when reading or writing TXPR1/TXPR0. Writing any value to TXPR1 is allowed, however, write operation to TXPR1 has no effect. Writing to the bit 0 in TXPR0 has no effect. * TXPR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 -- TXPR0[15:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * it is possible only to write a '1' for a Mailbox configured as transmitter. Bit 15 to 1 -- Indicates that the corresponding Mailbox is requested to transmit a CAN Frame. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively. When multiple bits are set, the order of the transmissions is governed by the MCR2 - CAN-ID or Mailbox number.
Bit[15:1]:TXPR0 0 Description Transmit message idle state in corresponding mailbox (Initial value) [Clearing Condition] Completion of message transmission or message transmission abortion (automatically cleared) 1 Transmission request made for corresponding mailbox
Bit 0-- Reserved: This bit is always '0' as this is a receive-only Mailbox. Writing a '1' to this bit position has no effect. The returned value is '0'.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.2
Transmit Cancel Register 0 (TXCR0)
TXCR0 is a 16-bit read/conditionally-write registers. The TXCR0 controls Mailbox-15 to Mailbox-1.This register is used by the CPU to request the pending transmission requests in the TXPR to be cancelled. To clear the corresponding bit in the TXPR the CPU must write a '1' to the bit position in the TXCR. Writing a '0' has no effect. When an abort has succeeded the CAN controller clears the corresponding TXPR + TXCR bits, and sets the corresponding ABACK bit. However, once a Mailbox has started a transmission, it cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN controller clears the corresponding TXPR + TXCR bit, and sets the corresponding TXACK bit, however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN controller clears the corresponding TXPR + TXCR bit, and sets the corresponding ABACK bit. If an attempt is made by the CPU to clear a mailbox transmission that is not transmit-pending it has no effect. In this case the CPU will be not able at all to set the TXCR flag. * TXCR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 -- TXCR0[15:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only writing a '1' to a Mailbox that is requested for transmission and is configured as transmit. Bit 15 to 1 -- Requests the corresponding Mailbox, that is in the queue for transmission, to cancel its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1]) respectively.
Bit[15:1]:TXCR0 0 Description Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing Condition] Completion of transmit message cancellation (automatically cleared) 1 Transmission cancellation request made for corresponding mailbox
Bit 0 -- This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has no effect and always read back as a '0'.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.3
Transmit Acknowledge Register 0 (TXACK0)
The TXACK0 is a 16-bit read/conditionally-write registers. This register is used to signal to the CPU that a mailbox transmission has been successfully made. When a transmission has succeeded the RCAN-ET sets the corresponding bit in the TXACK register. The CPU may clear a TXACK bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. * TXACK0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 -- TXACK0[15:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a '1' to clear. Bit 15 to 1 -- Notifies that the requested transmission of the corresponding Mailbox has been finished successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit[15:1]:TXACK0 0 1 Description [Clearing Condition] Writing '1' (Initial value) Corresponding Mailbox has successfully transmitted message (Data or Remote Frame) [Setting Condition] Completion of message transmission for corresponding mailbox
Bit 0 -- This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has no effect and always read back as a '0'.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.4
Abort Acknowledge Register 0 (ABACK0)
The ABACK0 is a 16-bit read/conditionally-write registers. This register is used to signal to the CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded the RCAN-ET sets the corresponding bit in the ABACK register. The CPU may clear the Abort Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. An ABACK bit position is set by the RCAN-ET to acknowledge that a TXPR bit has been cleared by the corresponding TXCR bit. * ABACK0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 -- ABACK0[15:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a '1' to clear. Bit 15 to 1 -- Notifies that the requested transmission cancellation of the corresponding Mailbox has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit[15:1]:ABACK0 Description 0 1 [Clearing Condition] Writing '1' (Initial value) Corresponding Mailbox has cancelled transmission of message (Data or Remote Frame) [Setting Condition] Completion of transmission cancellation for corresponding mailbox
Bit 0 -- This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has no effect and always read back as a '0'.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.5
Data Frame Receive Pending Register 0 (RXPR0)
The RXPR0 is a 16-bit read/conditionally-write registers. The RXPR is a register that contains the received Data Frames pending flags associated with the configured Receive Mailboxes. When a CAN Data Frame is successfully stored in a receive mailbox the corresponding bit is set in the RXPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox Configuration) to receive Data Frames. When a RXPR bit is set, it also sets IRR1 (Data Frame Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR1 is not set. Please note that these bits are only set by receiving Data Frames and not by receiving Remote frames. * RXPR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR0[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a '1' to clear. Bit 15 to 0 -- Configurable receive mailbox locations corresponding to each mailbox position from 15 to 0 respectively.
Bit[15:0]: RXPR0 0 1 Description [Clearing Condition] Writing '1' (Initial value) Corresponding Mailbox received a CAN Data Frame [Setting Condition] Completion of Data Frame receive on corresponding mailbox
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.6
Remote Frame Receive Pending Register 0 (RFPR0)
The RFPR0 is a 16-bit read/conditionally-write registers. The RFPR is a register that contains the received Remote Frame pending flags associated with the configured Receive Mailboxes. When a CAN Remote Frame is successfully stored in a receive mailbox the corresponding bit is set in the RFPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. In effect there is a bit position for all mailboxes. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a RFPR bit is set, it also sets IRR2 (Remote Frame Request Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Please note that these bits are only set by receiving Remote Frames and not by receiving Data frames. * RFPR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR0[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a '1' to clear. Bit 15 to 0 -- Remote Request pending flags for mailboxes 15 to 0 respectively.
Bit[15:0]: RFPR0 0 1 Description [Clearing Condition] Writing '1' (Initial value) Corresponding Mailbox received Remote Frame [Setting Condition] Completion of remote frame receive in corresponding mailbox
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.7
Mailbox Interrupt Mask Register 0 (MBIMR0)
The MBIMR1 and MBIMR0 are 16-bit read/write registers. The MBIMR only prevents the setting of IRR related to the Mailbox activities, that are IRR[1] - Data Frame Received Interrupt, IRR[2] - Remote Frame Request Interrupt, IRR[8] - Mailbox Empty Interrupt, and IRR[9] - Message OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the corresponding bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and IRR[9]) but does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR. Similarly when a mailbox has been configured for transmission, a mask prevents the generation of an Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or abortion of transmission (IRR[8]), however, it does not prevent the RCAN-ET from clearing the corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does not prevent the RCAN-ET from clearing the corresponding TXPR/TXCR bit + setting the ABACK bit for abortion of the transmission. A mask is set by writing a '1' to the corresponding bit position for the mailbox activity to be masked. At reset all mailbox interrupts are masked. * MBIMR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBIMR0[15:0] Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
Bit 15 to 0 -- Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0 respectively.
Bit[15:0]: MBIMR0 Description 0 1 Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.8
Unread Message Status Register 0 (UMSR0)
This register is a 16-bit read/conditionally write register and it records the mailboxes whose contents have not been accessed by the CPU prior to a new message being received. If the CPU has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox is received, the corresponding UMSR bit is set to '1'. This bit may be cleared by writing a '1' to the corresponding bit location in the UMSR. Writing a '0' has no effect. If a mailbox is configured as transmit box, the corresponding UMSR will not be set. * UMSR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR0[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 15 to 0 -- Indicate that an unread received message has been overwritten or overrun condition has occurred for Mailboxes 15 to 0.
Bit[15:0]: UMSR0 0 1 Description [Clearing Condition] Writing '1' (initial value) Unread received message is overwritten by a new message or overrun condition [Setting Condition] When a new message is received before RXPR or RFPR is cleared
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.6
19.6.1
Application Note
Configuration of RCAN-ET
RCAN-ET is considered in configuration mode or after a H/W (Power On Reset)/ S/W (MCR[0]) reset or when in Halt mode. In both conditions RCAN-ET cannot join the CAN Bus activity and configuration changes have no impact on the traffic on the CAN Bus. (1) After a reset request
The following sequence must be implemented to configure the RCAN-ET after (S/W or H/W) reset. After reset, all the registers are initialized, therefore, RCAN-ET needs to be configured before joining the CAN bus activity. Please read the notes carefully.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Power On/SW Reset*1
Configuration Mode GSR[3] = 0? MCR[0] = 1 (automatically in hardware reset only) Yes No*3
IRR[0] = 1, GSR[3] = 1 (automatically) RCAN-ET is in Tx_Rx Mode clear IRR[0] Bit Set TXPR to start transmission or stay idle to receive
Configure MCR[15] Transmission_Reception (Tx_Rx) Mode Clear Required IMR Bits Detect 11 recessive bits and Join the CAN bus activity Mailbox Setting (STD-ID, EXT-ID, LAFM, DLC, RTR, IDE, MBC, MBIMR, DART, ATX, NMC, Message-Data)*2
Receive*4 Set Bit Timing (BCR)
Transmit*4
Clear MCR[0]
Notes: 1. 2. 3. 4.
SW reset could be performed at any time by setting MCR[0] = 1. Mailboxes are comprised of RAMs, therefore, please initialize all the mailboxes enabled by MBC. It takes approximately 25 peripheral bus cycles for GSR[3] to be cleared to 0. If there is no TXPR set, RCAN-ET will receive the next incoming message. If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus. If it loses the arbitration, it will become a receiver.
Figure 19.6 Reset Sequence
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
(2)
Halt mode
When RCAN-ET is in Halt mode, it cannot take part to the CAN bus activity. Consequently the user can modify all the requested registers without influencing existing traffic on the CAN Bus. It is important for this that the user waits for the RCAN-ET to be in halt mode before to modify the requested registers - note that the transition to Halt Mode is not always immediate (transition will occurs when the CAN Bus is idle or in intermission). After RCAN-ET transit to Halt Mode, GSR4 is set. Once the configuration is completed the Halt request needs to be released. RCAN-ET will join CAN Bus activity after the detection of 11 recessive bits on the CAN Bus. (3) Sleep mode
When RCAN-ET is in sleep mode the clock for the main blocks of the IP is stopped in order to reduce power consumption. Only the following user registers are clocked and can be accessed: MCR, GSR, IRR and IMR. Interrupt related to transmission (TXACK and ABACK) and reception (RXPR and RFPR) cannot be cleared when in sleep mode (as TXACK, ABACK, RXPR and RFPR are not accessible) and must to be cleared beforehand. The following diagram shows the flow to follow to move RCAN-ET into sleep mode.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
(4)
CAN sleep mode
Sleep Mode Sequence flow
Halt Request
Write MCR[1] = 1 : Hardware operation : Manual operation
GSR[4] = 1? Yes IRR[0] = 1 Write IRR[0] = 1
No
User monitor
IRR[0] = 0 Sleep Request Write MCR[1] = 0 & MCR[5] = 1
IRR[0] = 1 Write IRR[0] = 1
IRR0 = 0
Sleep Mode
CAN Bus Activity Yes IRR[12] = 1
No
CLK is STOP
Only MCR, GSR, IRR, IMR can be accessed.
MCR[7] = 1? Yes
No Write IRR[12] = 1
IRR[12] = 0 MCR[5] = 0 Write IRR[12] = 1 Write MCR[5] = 0
IRR[12] = 0
GSR4 = 0? Yes Transmission/Reception Mode
No User monitor
Figure 19.7 Halt Mode/Sleep Mode
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Figure 19.8 - Halt Mode/Sleep Mode shows allowed state transition. * Don't set MCR5 (Sleep Mode) without entering Halt Mode. * After setting MCR1, make sure that GSR4 is set and the RCAN-ET has entered Halt Mode before clearing MCR1.
Power On/SW Reset
Reset
clear MCR0 and GSR3 = 0 Clear MCR1 and MCR5 Set MCR1*3 Transmission Reception Clear MCR5*1
Halt Request
Clear MCR5 Set MCR1*4
Except Transmitter/Receiver/BusOff, if MCR6 = 0 BusOff or except Transmitter/Receiver, if MCR6 = 1
Halt Mode Set MCR5 Clear MCR1*2
Sleep Mode
Notes: 1. MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if MCR7 is set or by writing "0". 2. MCR1 is cleared in SW. Clearing MCR1 and setting MCR5 have to be carried out by the same instruction. 3. MCR1 must not be cleared in SW, before GSR4 is set. MCR1 can be set automatically in HW when RCAN-ET moves to Bus Off and MCR14 and MCR6 are both set. 4. When MCR5 is cleared and MCR1 is set at the same time, RCAN-ET moves to Halt Request. Right after that, it moves to Halt Mode with no reception/transmission.
Figure 19.8 Halt Mode/Sleep Mode
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
The following table shows conditions to access registers. Table 19.8 Conditions to Access Registers
RCAN-ET Registers MCR Status Mode GSR Reset Yes IRR IMR Yes Yes Yes Yes Yes BCR Yes No* No* No* No
1
MBIMR Yes Yes Yes Yes No
mailbox mailbox mailbox (ctrl1) Flag_register (ctrl0, LAFM) (data) Yes Yes Yes Yes No Yes No* No* Yes No
1
Yes Yes* Yes*
2
Yes
2
Transmission Yes Reception Halt Request Halt Sleep Yes Yes Yes
Yes* Yes* Yes No
No* No* Yes No
1
Yes* Yes*
2
1
1
2
2
1
2
1
Notes: 1. No hardware protection 2. When TXPR is not set.
19.6.2
Test Mode Settings
The RCAN-ET has various test modes. The register TST[2:0] (MCR[10:8]) is used to select the RCAN-ET test mode. The default (initialized) settings allow RCAN-ET to operate in Normal mode. The following table is examples for test modes. Test Mode can be selected only while in configuration mode. The user must then exit the configuration mode (ensuring BCR0/BCR1 is set) in order to run the selected test mode. Table 19.9 Test Mode Settings
Bit10: TST2 0 0 0 0 1 1 1 1 Bit9: TST1 0 0 1 1 0 0 1 1 Bit8: TST0 0 1 0 1 0 1 0 1 Description Normal mode (initial value) Listen-only mode (receive-only mode) Self test mode 1 (external) Self test mode 2 (internal) Write error counter Error passive mode Setting prohibited Setting prohibited
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
* Normal Mode RCAN-ET operates in the normal mode. * Listen-Only Mode: ISO-11898 requires this mode for baud rate detection. The Error Counters are cleared and disabled so that the TEC/REC does not increase the values, and the CTx Output is disabled so that RCAN-ET does not generate error frames or acknowledgment bits. IRR13 is set when a message error occurs. * Self Test Mode 1 RCAN-ET generates its own Acknowledge bit, and can store its own messages into a reception mailbox (if required). The CRx/CTx pins must be connected to the CAN bus. * Self Test Mode 2 RCAN-ET generates its own Acknowledge bit, and can store its own messages into a reception mailbox (if required). The CRx/CTx pins do not need to be connected to the CAN bus or any external devices, as the internal CTx is looped back to the internal CRx. CTx pin outputs only recessive bits and CRx pin is disabled. * Write Error Counter TEC/REC can be written in this mode. RCAN-ET can be forced to become an Error Passive mode by writing a value greater than 127 into the Error Counters. The value written into TEC is used to write into REC, so only the same value can be set to these registers. Similarly, RCAN-ET can be forced to become an Error Warning by writing a value greater than 95 into them. * Error Passive mode RCAN-ET needs to be in Halt Mode when writing into TEC/REC (MCR1 must be "1" when writing to the Error Counter). Furthermore this test mode needs to be exited prior to leaving Halt mode.Error Passive Mode: RCAN-ET can be forced to enter Error Passive mode. Note: the REC will not be modified by implementing this Mode. However, once running in Error Passive Mode, the REC will increase normally should errors be received. In this Mode, RCAN-ET will enter BusOff if TEC reaches 256 (Dec). However when this mode is used RCAN-ET will not be able to become Error Active. Consequently, at the end of the Bus Off recovery sequence, RCAN-ET will move to Error Passive and not to Error Active When message error occurs, IRR13 is set in all test modes.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.6.3 (1)
Message Transmission Sequence
Message Transmission Request
The following sequence is an example to transmit a CAN frame onto the bus. As described in the previous register section, please note that IRR8 is set when one of the TXACK or ABACK bits is set, meaning one of the Mailboxes has completed its transmission or transmission abortion and is now ready to be updated for the next transmission, whereas, the GSR2 means that there is currently no transmission request made (No TXPR flags set).
RCAN-ET is in Normal Mode (MBC[n] = 0)
Mailbox[n] is ready to be updated for next transmission
Update Message Data of Mailbox[n]
Clear TXACK[n]
Yes
Write '1' to the TXPR[n] bit at any desired time
TXACK[n] set?
No
Monitor for the next interrupt
Internal Arbitration 'n' Highest Priority?
Yes
No
Yes No
IRR8 set?
Monitor for the next interrupt
Transmission Start CAN Bus Arbitration Acknowledge Bit CAN Bus
Note: n = 0 to 15 (mailbox number)
Figure 19.9 Transmission Request (2) Internal Arbitration for Transmission
The following diagram explains how RCAN-ET manages to schedule transmission-requested messages in the correct order based on the CAN identifier. 'Internal arbitration' picks up the highest priority message amongst transmit-requested messages.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Transmission Frame-1 CAN bus state RCAN-ET scheduler state Scheduler start point TXPR/TXCR/ Error/Arb-Lost Set Point Bus Idle SOF Message EOF Interm SOF
Reception Frame-2 Message
Transmission Frame-3 EOF Interm SOF
CTx/CRx Arb for Frame-3
CTx Arb for CTx/CRx Arb for Frame-1 Frame-1
CTx Arb for Frame-3
CTx/CRx Arb for Frame-3/2
CTx Arb for Frame-3
1-1
1-2
2-1
2-2
3-1
3-2
Interm: SOF: EOF: Message:
Intermission Field Start Of Frame End Of Frame Arbitration + Control + Data + CRC + Ack Field
Figure 19.10 Internal Arbitration for transmission The RCAN-ET has two state machines. One is for transmission, and the other is for reception. 1-1: When a TXPR bit(s) is set while the CAN bus is idle, the internal arbitration starts running immediately and the transmission is started. 1-2: Operations for both transmission and reception starts at SOF. Since there is no reception frame, RCAN-ET becomes transmitter. 2-1: At crc delimiter, internal arbitration to search next message transmitted starts. 2-2: Operations for both transmission and reception starts at SOF. Because of a reception frame with higher priority, RCAN-ET becomes receiver. Therefore, Reception is carried out instead of transmitting Frame-3. 3-1: At crc delimiter, internal arbitration to search next message transmitted starts. 3-2: Operations for both transmission and reception starts at SOF. Since a transmission frame has higher priority than reception one, RCAN-ET becomes transmitter. Internal arbitration for the next transmission is also performed at the beginning of each error delimiter in case of an error is detected on the CAN Bus. It is also performed at the beginning of error delimiters following overload frame. As the arbitration for transmission is performed at CRC delimiter, in case a remote frame request is received into a Mailbox with ATX = 1 the answer can join the arbitration for transmission only at the following Bus Idle, CRC delimiter or Error Delimiter. Depending on the status of the CAN bus, following the assertion of the TXCR, the corresponding Message abortion can be handled with a delay of maximum 1 CAN Frame.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.6.4
Message Receive Sequence
The diagram below shows the message receive sequence.
CAN Bus
End Of Arbitration Field RCAN-ET IDLE
End Of Frame
Valid CAN-ID Received n=n-1 Loop (n = 15; n 0; n = n - 1)
Valid CAN Frame Received
Exit Interrpt Service Routine Compare ID with Mailbox[N] + LAFM[N] (if MBC is config to receive) Yes No No Yes N = 0? RXPR[N] (RFPR[N]) Already Set? Yes Read Mailbox[N] MSG OverWrite or OverRun? (NMC) OverRun
* Reject Message * Set UMSR * Set IRR9 (if MBIMR[N] = 0) * Generate Interrupt Signal (if IMR9 = 0) * Set RXPR[N] (RFPR[N])*1
Clear by clear UMSR[N]*2
Clear by clear UMSR[N]*2
ID Matched? Yes
Write 1 to RXPR[N] No
Write 1 to RFPR[N]
Store Mailbox-Number[N] and go back to idle state
Read Mailbox[N]
OverWrite
Read RXPR[N] = 1
Read RFPR[N] = 1
* Store Message by Overwriting * Set UMSR * Set IRR9 (if MBIMR[N] = 0) * Generate Interrupt Signal (if IMR9 = 0) * Set RXPR[N] (RFPR[N]) * Set IRR1 (IRR2) (if MBIMR[N] = 0) * Generate Interrupt Signal (if IMR1 (IMR2) = 0)
Yes IRR[1] set? No
* Store Message *Set RXPR[N] (RFPR[N]) *Set IRR1 (IRR2) (if MBIMR[N] = 0) *Generate Interrupt Signal (if IMR1 (IMR2) = 0)
Read IRR
Intrrupt signal
Intrrupt signal
Intrrupt signal
CPU received interrupt due to CAN Message Reception Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even thuotgh the message has not been updated. 2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/ RFPR[N]/UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Figure 19.11 Message receive sequence
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
When RCAN-ET recognises the end of the Arbitration field while receiving a message, it starts comparing the received identifier to the identifiers set in the Mailboxes, starting from Mailbox-15 down to Mailbox-0. It first checks the MBC if it is configured as a receive box, and reads LAFM, and reads the CAN-ID of Mailbox-15 (if configured as receive) to finally compare them to the received ID. If it does not match, the same check takes place at Mailbox-14 (if configured as receive). Once RCAN-ET finds a matching identifier, it stores the number of Mailbox-[n] into an internal buffer, stops the search, and goes back to idle state, waiting for the EndOfFrame (EOF) to come. When the 6th bit of EOF is notified by the CAN Interface logic, the received message is written or abandoned, depending on the NMC bit. No modification of configuration during communication is allowed. Entering Halt Mode is one of ways to modify configuration. If it is written into the corresponding Mailbox, including the CAN-ID, i.e., there is a possibility that the CAN-ID is overwritten by a different CAN-ID of the received message due to the LAFM used. This also implies that, if the identifier of a received message matches to ID + LAFM of 2 or more Mailboxes, the higher numbered Mailbox will always store the relevant messages and the lower numbered Mailbox will never receive messages. Therefore, the settings of the identifiers and LAFMs need to be carefully selected. With regards to the reception of data and remote frames described in the above flow diagram the clearing of the UMSR flag after the reading of IRR is to detect situations where a message is overwritten by a new incoming message stored in the same mailbox while the interrupt service routine is running. If during the final check of UMSR a overwrite condition is detected the message needs to be discarded and read again. Please note that in the case a received remote frame is overwritten by a data frame, both the remote frame request interrupt (IRR2) and data frame received interrupt (IRR1) and also the Receive Flags (RXPR and RFPR) are set. In an analogous way, the overwriting of a data frame by a remote frame, leads to setting both IRR2 and IRR1. In the Overrun Mode (NMC = '0'), only the first Mailbox will cause the flags to be asserted. So, if a Data Frame is initially received, then RXPR and IRR1 are both asserted. If a Remote Frame is then received before the Data Frame has been read, then RFPR and IRR2 are NOT set. In this case UMSR of the corresponding Mailbox will still be set.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.6.5
Reconfiguration of Mailbox
When re-configuration of Mailboxes is required, the following procedures should be taken. (1) Change configuration of transmit box
Two cases are possible. * Change of ID, RTR, IDE, LAFM, Data, DLC, NMC, ATX, DART This change is possible only when MBC = B'000. Confirm that the corresponding TXPR is not set. The configuration (except MBC bit) can be changed at any time. * Change from transmit to receive configuration (MBC) Confirm that the corresponding TXPR is not set. The configuration can be changed only in Halt or reset state. Please note that it might take longer for RCAN-ET to transit to halt state if it is receiving or transmitting a message (as the transition to the halt state is delayed until the end of the reception/transmission), and also RCAN-ET will not be able to receive/transmit messages during the Halt state. In case RCAN-ET is in the Bus Off state the transition to halt state depends on the configuration of the bit 6 of MCR and also bit and 14 of MCR. (2) Change configuration (ID, RTR, IDE, LAFM, Data, DLC, NMC, ATX, DART) of receive box or Change receive box to transmit box
The configuration can be changed only in Halt Mode. RCAN-ET will not lose a message if the message is currently on the CAN bus and RCAN-ET is a receiver. RCAN-ET will be moving into Halt Mode after completing the current reception. Please note that it might take longer if RCAN-ET is receiving or transmitting a message (as the transition to the halt state is delayed until the end of the reception/transmission), and also RCAN-ET will not be able to receive/transmit messages during the Halt Mode. In case RCAN-ET is in the Bus Off state the transition to halt mode depends on the configuration of the bit 6 and 14 of MCR.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Method by Halt Mode RCAN-ET is in Tx_Rx Mode
Set MCR[1] (Halt Mode)
Is RCAN-ET Transmitter, Receiver or Bus Off? No Generate interrupt (IRR0)
Finish current session Yes
Read IRR0 & GSR4 as '1'
RCAN-ET is in Halt Mode
Change ID or MBC of Mailbox
Clear MCR1
RCAN-ET is in Tx_Rx Mode The shadowed boxes need to be done by S/W (host processor)
Figure 19.12 Change ID of Receive Box or Change Receive Box to Transmit Box
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.7
Interrupt Sources
Table 19.10 lists the RCAN-ET interrupt sources. With the exception of the reset processing interrupt (IRR0) by a power-on reset, these sources can be masked. Masking is implemented using the mailbox interrupt mask register 0 (MBIMR0) and interrupt mask register (IMR). For details on the interrupt vector of each interrupt source, see section 6, Interrupt Controller (INTC). Table 19.10 RCAN-ET Interrupt Sources
Channel 0 Interrupt ERS_0 Description Error Passive Mode (TEC 128 or REC 128) Bus Off (TEC 256)/Bus Off recovery Error warning (TEC 96) Error warning (REC 96) OVR_0 Message error detection Reset/halt/CAN sleep transition Overload frame transmission Unread message overwrite (overrun) Detection of CAN bus operation in CAN sleep mode SLE_0 RM1_0*2 RM0_0*
2
Interrupt Flag IRR5 IRR6 IRR3 IRR4 IRR13*1 IRR0 IRR7 IRR9 IRR12 IRR8 IRR1*3 IRR2*3
DTC Activation Not possible
Message transmission/transmission disabled (slot empty) Data frame reception/ Remote frame reception
Possible
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Channel 1
Interrupt ERS_1
Description Error Passive Mode (TEC 128 or REC 128) Bus Off (TEC 256)/Bus Off recovery Error warning (TEC 96) Error warning (REC 96)
Interrupt Flag IRR5 IRR6 IRR3 IRR4 IRR13*1 IRR0 IRR7 IRR9 IRR12 IRR8 IRR1*3 IRR2*3
DTC Activation Not possible
OVR_1
Message error detection Reset/halt/CAN sleep transition Overload frame transmission Unread message overwrite (overrun) Detection of CAN bus operation in CAN sleep mode
SLE_1 RM1_1*2 RM0_1*
2
Message transmission/transmission disabled (slot empty) Data frame reception/ Remote frame reception
Possible
Notes: 1. Available only in Test Mode. 2. RM0 is an interrupt generated by the remote request pending flag for mailbox 0 (RFPR0[0]) or the data frame receive flag for mailbox 0 (RXPR0[0]). RM1 is an interrupt generated by the remote request pending flag for mailbox n (RFPR0[n]) or the data frame receive flag for mailbox n (RXPR0[n]) (n = 1 to 15). 3. IRR1 is a data frame received interrupt flag for mailboxes 0 to 15, and IRR2 is a remote frame request interrupt flag for mailboxes 0 to 15.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.8
CAN Bus Interface
A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Renesas HA13721 transceiver IC and its compatible products are recommended. As the CRx and CTx pins use 3 V, an external level shifter is necessary. Figure 19.13 shows a sample connection diagram.
120
This LSI Vcc HA13721 MODE CRx CTx 3V5V Level shifter Rxd Txd NC Vcc CANH CANL GND
CAN bus
120 Note: NC: No Connection
Figure 19.13 High-Speed Interface Using HA13721
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.9
19.9.1
Usage Notes
Module Standby Mode
The standby control register 2 (STBCR2) controls the supply of clocks to RCAN-ET. As an initial value, the clock to RCAN-ET is halted. Registers should be accessed after the module stop mode is released. 19.9.2 Reset
Two types of resets are supported for RCAN-ET. * Hardware reset RCAN-ET is initialized by a power-on reset, deep standby mode, or software standby mode. * Software reset The MCR0 bit in the master control register (MCR) initializes registers other than MCR and CAN communication functions. As the IRR0 bit in the interrupt request register (IRR) is initialized and set to 1 at a reset, it should be cleared to 0 in the configuration mode shown in the reset sequence diagram. The area except for the message control field 1 (CONTROL1) of Mailbox is consisted of RAM, and not initialized at a reset. After a power-on reset, all the Mailboxes should be initialized in the configuration mode shown in the reset sequence diagram. 19.9.3 CAN Sleep Mode
The supply of main clocks in the modules is stopped in CAN sleep mode. Therefore, registers other than MCR, GSR, IRR, and IMR should not be accessed in CAN sleep mode. 19.9.4 Register Access
When the CAN bus receive frame is being stored in the Mailbox with the CAN communication functions of RCAN-ET, accessing the Mailbox area generates 0 to 5 peripheral bus cycles as a wait.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.9.5
Interrupts
As shown in table 19.2, the Mailbox 0 receive interrupt enables the DMAC activation. When an interrupt is specified as to be activated by the Mailbox 0 receive interrupt and cleared by the interrupt source at the DMA transfer, up to the message control field 1 (CONTROL1) of Mailbox 0 should be read using the block transfer mode.
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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Section 20 IEBus Controller (IEB) [R5S72612] [R5S72613]
This LSI has an on-chip one-channel IEBus controller (IEB). The Inter Equipment Bus (IEBus)* is a small-scale digital data transfer system for inter-equipment data transfer. This LSI does not have an on-chip IEBus driver/receiver, so it is necessary to mount a dedicated driver/receiver externally. In addition, as the IERxD and IETxD pins need 3V to operate, a dedicated external level shifter is necessary. Note: * The Inter Equipment Bus (IEBus) is a trademark of NEC Electronics Corporation.
20.1
Features
* IEBus protocol control (layer 2) supported Half-duplex asynchronous communications Multi-master system Broadcast communications function Selectable mode (three types) with different transfer speeds * On-chip buffers for data transmission and reception Transmission and reception buffers: 128 bytes each Up to 128 bytes of consecutive transmit/reception (maximum number of transfer bytes in mode 2) * Operating frequency 6 MHz, 6.29 MHz (IEB uses clocks of P or AUDIO_X1*/AUDIO_X2*.) 12 MHz, 12.58 MHz (IEB uses 1/2 divided clocks of P or AUDIO_X1*/AUDIO_X2*.) 18 MHz, 18.87 MHz (IEB uses 1/3 divided clocks of P or AUDIO_X1*/AUDIO_X2*.) 24 MHz, 25.16 MHz (IEB uses 1/4 divided clocks of P or AUDIO_X1*/AUDIO_X2*.) 30 MHz, 31.45 MHz (IEB uses 1/5 divided clocks of P or AUDIO_X1*/AUDIO_X2*.) 36 MHz, 37.74 MHz (IEB uses 1/6 divided clocks of P or AUDIO_X1*/AUDIO_X2*.) Note: * Available as the IEB clock input only when not used as the clock input for SSI audio * Module standby mode can be set.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.1.1
IEBus Communications Protocol
An overview of the IEBus is provided below. * Communications method: Half-duplex asynchronous communications * Multi-master system All units connected to the IEBus can transfer data to other units. * Broadcast communications function (one-to-many communications) Group broadcast communications: Broadcast communications to group unit General broadcast communications: Broadcast communications to all units * Mode is selectable (three modes with different transfer speeds) Table 20.1 Mode Types
Mode 0 1 2 IEB*1 = 6, 12, 18, 24, 30, 36*2 MHz About 3.9 kbps About 17 kbps About 26 kbps IEB*1 = 6.29, 12.58, 18.87, 25.16, 31.45, 37.74*2 MHz About 4.1 kbps About 18 kbps About 27 kbps Maximum Number Of Transfer Bytes (byte/frame) 16 32 128
Notes: 1. Peripheral clock (P), or clocks for AUDIO_X1 and AUDIO_X2 2. Oscillation frequency when this LSI is used
* Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) Priority of bus mastership is as follows. Broadcast communications (one-to-many communications) have priority over normal communications (one-to-one communications). A smaller master address has priority. * Communications scale Number of units: Up to 50 Cable length: Up to 150 m (when using a twisted-pair cable) Note: The communications scale of the actual system depends on the characteristics of the externally mounted IEBus driver/receiver and the cable used.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(1)
Determination of Bus Mastership (Arbitration)
A unit connected to the IEBus performs an operation to get the bus to control other units. This operation is called arbitration. In arbitration, when multiple units start transferring simultaneously, the bus mastership is given to one unit among them. Only one unit can obtain bus mastership through arbitration, so the following priority for bus mastership is determined. (a) Priority according to communications type
Broadcast communications (one-to-many communications) has priority over normal communications (one-to-one communications). (b) Priority according to master address
The unit with the smallest master address has priority among units of the same communications type. Example: The master address is configured with 12 bits. A unit with H'000 has the highest priority, while a unit with H'FFF has the lowest priority. Note: When a unit loses in arbitration, the unit can automatically enter retransfer mode (0 to 7 retransfer times can be selected by the RN bit in IEMCR).
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(2)
Communications Mode
The IEBus has three communications modes with different transfer speeds. Table 20.2 shows the transfer speed in each communications mode and the maximum number of transfer bytes in one communications frame. Table 20.2 Transfer Speed and Maximum Number of Transfer Bytes in Each Communications Mode
Maximum Number Communications of Transfer Bytes (bytes/frame) Mode 0 1 2 Notes: 16 32 128 Effective Transfer Speed*1 (kbps) IEB* = 6, 12, 18, 24, 30, 36*3 MHz About 3.9 About 17 About 26
2
IEB*2 = 6.29, 12.58, 18.87, 25.16, 31.45, 37.74*3 MHz About 4.1 About 18 About 27
Each unit connected to the IEBus should select a communications mode prior to performing communications. Note that correct communications is not guaranteed if the master and slave units do not adopt the same communications mode. In the case of communications between a unit with = 6 MHz and a unit with = 6.29 MHz, correct communications are not possible even if the same communications mode is adopted. Communications must be done with the same oscillation frequency. 1. Effective transfer speed when the maximum number of transfer bytes is transmitted. 2. Peripheral clock (P), or clocks for AUDIO_X1 and AUDIO_X2 3. Oscillation frequency when this LSI is used
(3)
Communications Address
In the IEBus, a specific 12-bit communications address is allocated to each individual unit. A communications address is configured as follows. * Upper four bits: group number (number identifying a group to which the unit belongs) * Lower eight bits: unit number (number identifying individual units in a group)
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(4)
Broadcast Communications
In normal transfer, a single master unit communicates with a single slave unit, so one-to-one transfer or reception takes place. In broadcast communications, a single master unit communicates with multiple slave units. Since there are multiple slave units, no acknowledgements are returned from the slave units during communications. A broadcast bit decides whether broadcast or normal communications is done. (For details of the broadcast bit, see section 20.1.2 (1) (b), Broadcast Bit. There are two types of broadcast communications. (a) Group broadcast communications
Broadcast communications is aimed at units with the same group number, meaning that those units have the same upper four bits of the communications address. (b) General broadcast communications
Broadcast communications is aimed at all units regardless of group number. Group broadcast and general broadcast communications are identified by a slave address. (For details on the slave address, see section 20.1.2 (3), Slave Address Field.)
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.1.2
Communications Protocol
Figure 20.1 shows an IEBus transfer signal format. Communications data is transferred as a series of signals referred to as a communications frame. The number of data which can be transmitted in a single communications frame and the transfer speed differ according to the communications mode.
(When IEB = 6, 12, 18, 24, 30, or 36 MHz) Field name Number of bits Transfer time Mode 0 Mode 1 Mode 2 Approximately 7330 s Approximately 2090 s Approximately 1590 s P: Parity bit (1 bit) A: Acknowledge bit (1 bit) When A = 0: ACK When A = 1: NAK N: Number of bytes Note: The value of acknowledge bit is ignored in broadcast communications. Approximately 1590 x N s Approximately 410 x N s Approximately 300 x N s Header 1 1
Master address field
12
1 P
Slave address field 12 11
Slave address
Control field 4
Control bits
1
1
Message length field 8 11
Message length bits
Data field 8
Data bits
1
1
8
Data bits
1
1
Start Broad- Master bit cast address
bit
PA
PA
PA
PA
PA
Figure 20.1 Transfer Signal Format (1) Header
A header is comprised of a start bit and a broadcast bit. (a) Start Bit
The start bit is a signal to inform other units of the start of data transfer. A unit attempting to start data transfer outputs a low-level signal (the start bit) for a specified period and then outputs the broadcast bit. If another unit is already outputting a start bit when a unit attempts to output a start bit, the unit waits for completion of the start bit from the other unit without outputting its own start bit, and then outputs the broadcast bit synchronized with the completion timing. Other units enter the receive state after detecting the start bit.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(b)
Broadcast Bit
The broadcast bit is a bit to identify the type of communications: broadcast or normal. When this bit is cleared to 0, it indicates broadcast communications. When it is set to 1, it indicates normal communications. Broadcast communications includes group broadcast and general broadcast, which are identified by a value of the slave address. (For details of the slave address, see section 20.1.2 (3), Slave Address Field.) Since multiple slave units are communications destination units, in the case of broadcast communications, the acknowledge bit is not returned from each field described in (2) and below. When more than one unit starts to transfer a communications frame with the same timing, broadcast communications has priority over normal communications, and arbitration occurs. (2) Master Address Field
The master address field is a field for transmitting the unit address (master address) to other units. The master address field is comprised of master address bits and a parity bit. The master address consists of 12 bits and the MSB is output first. When more than one unit start to transfer broadcast bits having the same value with the same timing, arbitration is decided by the master address field. In the master address field, self-output data and data on the bus are compared for every one-bit transfer. If the self-output master address and data on the bus are different, the unit that loses arbitration will stop its transfer and enter the receive state. Since the IEBus is configured with wired AND, the unit having the smallest master address of the units in arbitration (arbitration master) wins in arbitration. Finally, only a single unit remains in the transfer state as a master unit after outputting a 12-bit master address. Next, this master unit outputs a parity bit*, defines the master address for other units, and then enters the slave address field output state. Note: * Since even parity is used, when the number of one bit in the master address is odd, the parity bit is 1.
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Section 20 IEBus
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Controller (IEB) [R5S72612] [R5S72613]
(3)
Slave Address Field
The slave address field is a field to transmit an address (the slave address) of a unit (the slave unit) to be transmitted. The slave address field is comprised of slave address bits, a parity bit, and an acknowledge bit. The slave address consists of 12 bits and the MSB is output first. The parity bit is output after the 12-bit slave address is transmitted to avoid receiving the slave address accidentally. The master unit then detects the acknowledgement from the slave unit to confirm that the slave unit exists on the bus. When the acknowledgement is detected, the master unit enters the control field output state. However, the master unit enters the control field output state without detecting the acknowledgement in broadcast communications. The slave unit returns an acknowledgement when the slave addresses match and the parities of the master and slave addresses are correct. When the parity of either the master or slave address is incorrect, the slave unit decides that the master or slave address was not correctly received and does not return the acknowledgement. In this case, the master unit enters the waiting (monitor) state and communications ends. In the case of broadcast communications, the slave address is used to identify the type of broadcast communications (group or general) as follows: * When the slave address is H'FFF: General broadcast communications * When the slave address is other than H'FFF: Group broadcast communications Note: The group number is the upper 4-bit value of the slave address in group broadcast communications. (4) Control Field
The control field is a field for transmitting the type and direction of the following data field. The control field is comprised of control bits, a parity bit, and an acknowledge bit. The control bits consist of four bits and the MSB is output first. The parity bit is output following the control bits. When the parity is correct, and the slave unit can implement the function required from the master unit, the slave unit returns an acknowledgement and enters the message length field output state. However, if the slave unit cannot implement the requirements from the master unit even though the parity is correct, or if the parity is not correct, the slave unit does not return an acknowledgement and returns to the waiting (monitor) state.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
The master unit enters the subsequent message length field output state after confirming the acknowledgement. When the acknowledgement is not confirmed, the master unit enters the waiting (monitor) state, and communications ends. However, in the case of broadcast communications, the master unit enters the following message length field output state without confirming the acknowledgement. For details of the contents of the control bit, see table 20.4. (5) Message Length Field
The message length field is a field for specifying the number of transfer bytes. The message length field is comprised of message length bits, a parity bit, and an acknowledge bit. The message length has eight bits and the MSB is output first. Table 20.3 shows the number of transfer bytes. Table 20.3 Contents of Message Length bits
Message Length bits (Hexadecimal) H'01 H'02 : H'FF H'00 Number of Transfer Bytes 1 byte 2 bytes : 255 bytes 256 bytes
Note: If a number greater than the maximum number of transfer bytes in one frame is specified, communications are done in multiple frames depending on the communications mode. In this case, the message length bits indicate the number of remaining communications data after the first transfer. In this LSI, the message length bits must be smaller than the maximum number of transfer bytes in one frame. Set these within the ranges shown below. Mode 0: 1 to 16 bytes Mode 1: 1 to 32 bytes Mode 2: 1 to 128 bytes
This field operation differs depending on the value of bit 3 in the control field: master transmission (the bit 3 of the control bits is 1) or master reception (the bit 3 of the control bits is 0).
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Section 20 IEBus
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Controller (IEB) [R5S72612] [R5S72613]
(a)
Master Transmission
The master unit outputs the message length bits and the parity bit. When the parity is even, the slave unit returns an acknowledgement and enters the following data field. Note that the slave unit does not return an acknowledgement in broadcast communications. When the parity is odd, the slave unit decides that the message length field is not correctly received, does not return an acknowledgement, and returns to the waiting (monitor) state. In this case, the master unit also returns to the waiting state and communications end. (b) Master Reception
The slave unit outputs the message length bits and parity bit. When even parity is confirmed, the master unit returns an acknowledgement. When the parity is not correct, the master unit decides that the message length bits are not correctly received, does not return an acknowledgement, and returns to the waiting state. In this case, the slave unit also returns to the waiting state and communications end. (6) Data Field
The data field is a field for data transmission/reception to and from the slave unit. The master unit transmits/receives data to and from the slave unit using the data field. The data field is comprised of data bits, a parity bit, and an acknowledge bit. The data bits consist of eight bits and the MSB is output first. The parity and acknowledge bits are output following the data bits from the master unit and slave unit, respectively. Broadcast communications are performed only for the transmission of the master unit. In this case, the acknowledge bit is ignored. Operations in master transmission and master reception are described below.
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Section 20 IEBus
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Controller (IEB) [R5S72612] [R5S72613]
(a)
Master Transmission
The master unit transmits the data bits and parity bit to the slave unit to write data from the master unit to the slave unit. The slave unit receives the data bits and parity bit, and returns an acknowledgement if the parity bit is even and the receive buffer is empty. If the parity bit is odd or the receive buffer is not empty, the slave unit does not accept the corresponding data and does not return an acknowledgement. When the slave unit does not return an acknowledgement, the master unit retransmits the data. This operation is repeated until either an acknowledgement from the slave unit is detected or the maximum number of data transfer bytes is reached. When the parity is even and the acknowledgement is output from the slave unit, the master unit transmits the subsequent data if data remains and the maximum number of transfer bytes are not exceeded. In the case of broadcast communications, the slave unit does not return the acknowledgement, and the master unit transfers data byte by byte. (b) Master Reception
The master unit outputs synchronous signals corresponding to all data bits to be read from the slave unit. The slave unit outputs the data bits and parity bit on the bus in accordance with the synchronous signals from the master unit. The master unit reads the parity bit output from the slave unit, and checks the parity. If the parity is not even, or the receive buffer is not empty, the master unit rejects acceptance of the data, and does not return the acknowledgement. The master unit reads the same data repeatedly if the number of data does not exceed the maximum number of transfer bytes in one frame. If the parity is even and the receive buffer is empty, the master unit accepts data and returns an acknowledgement. The master unit reads in the subsequent data if the number of data does not exceed the maximum number of transfer bytes in one frame.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(7)
Parity bit
The parity bit is used to confirm that transfer data occurs with no errors. The parity bit is added to respective data of the master address, slave address, control, message length, and data bits. Even parity is used. When the number of bits having the value 1 is odd, the parity bit is 1. When the number of bits having the value 1 is even, the parity bit is 0. (8) Acknowledge bit
In normal communications (single unit to single unit communications), the acknowledge bit is added in the following positions to confirm that data is correctly accepted. * * * * At the end of the slave address field At the end of the control field At the end of the message length field At the end of the data field
The acknowledge bit is defined below. * 0: indicates that the transfer data is acknowledged. (ACK) * 1: indicates that the transfer data is not acknowledged. (NAK) Note that the acknowledge bit is ignored in the case of broadcast communications. (a) Acknowledge bit at the End of the Slave Address Field
The acknowledge bit at the end of the slave address field becomes NAK in the following cases and transfer is stopped. * When the parity of the master address or slave address bits is incorrect * When a timing error (an error in bit format) occurs * When there is no slave unit
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(b)
Acknowledge bit at the End of the Control Field
The acknowledge bit at the end of the control field becomes NAK in the following cases and transfer is stopped. * When the parity of the control bits is incorrect * When the bit 3 of the control bits is 1 (data write) although the slave receive buffer* is not empty * When the control bits are set to data read (H'3, H'7) although the slave transmit buffer* is empty * When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or H'F in the control bits although the slave unit has been locked * When the control bits are the locked address read (H'4, H'5) although the unit is not locked * When a timing error occurs * When the control bits are undefined Note: See section 20.1.3 (1), Slave Status Read (Control Bits: H'0, H'6). (c) Acknowledge Bit at the End of the Message Length Field
The acknowledge bit at the end of the message length field becomes NAK in the following cases and transfer is stopped. * When the parity of the message length bits is incorrect * When a timing error occurs (d) Acknowledge Bit at the End of the Data Field
The acknowledge bit at the end of the data field becomes NAK in the following cases and transfer is stopped. * When the parity of the data bits is incorrect* * When a timing error occurs after the previous transfer of the acknowledge bit * When the receive buffer becomes full and cannot accept further data* Note: * In this case, the data field is transferred repeatedly until the number of data reaches the maximum number of transfer bytes if the number of data does not exceed the maximum number of transfer bytes in one frame.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.1.3
Transfer Data (Data Field Contents)
The data field contents are specified by the control bits. Table 20.4 Control Bit Contents
Setting Value H'0 H'1 H'2 H'3 H'4 H'5 H'6 H'7 H'8 H'9 H'A H'B H'C H'D H'E H'F Bit 3*1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function*2 Reads slave status (SSR) Undefined. Setting prohibited. Undefined. Setting prohibited. Reads data and locks Reads locked address (lower 8 bits) Reads locked address (upper 4 bits) Reads slave status (SSR) and unlocks Reads data Undefined. Setting prohibited. Undefined. Setting prohibited. Writes command and locks Writes data and locks Undefined. Setting prohibited. Undefined. Setting prohibited. Writes command Writes data
Notes: 1. Depending on the value of bit 3 (MSB), the transfer directions of the message length bits in the following message length field and data in the data field vary. When bit 3 is 1: Data is transferred from the master unit to the slave unit. When bit 3 is 0: Data is transferred from the slave unit to the master unit. 2. H'3, H'6, H'A, and H'B are control bits to specify lock setting and cancellation. When the undefined values of H'1, H'2, H'8, H'9, H'C, and H'D are transmitted, the acknowledge signal is not returned.
When the control bits received from another unit which locked are not included in table 20.5, the slave unit which has been locked by the master unit does not accept the control bits and does not return the acknowledge bit.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Table 20.5 Control Field for Locked Slave Unit
Setting Value H'0 H'4 H'5 Bit 3 0 0 0 Bit 2 0 1 1 Bit 1 0 0 0 Bit 0 0 0 1 Function Reads slave status Reads locked address (upper 8 bits) Reads locked address (lower 4 bits)
(1)
Slave Status Read (Control Bits: H'0, H'6)
The master unit can decide the reason the slave unit does not return the acknowledgement (ACK) by reading the slave status (H'0, H'6). The slave status indicates the result of the last communications that the slave unit performed. All slave units can provide slave status information. Figure 20.2 shows the bit configuration of the slave status.
MSB Bit 7 Bit Bit 7, bit 6 Bit 6 Bit 5 Value 00 01 10 11 Bit 5 Bit 4*2 Bit 3 Bit 2 Bit 1*3 Bit 0*4 0 0 1 0 0 1 0 1 0 1 Bit 4 Description Mode 0 Mode 1 Mode 2 For future use Fixed 0 Slave transmission halted Slave transmission enabled Fixed 0 Unit is unlocked Unit is locked Slave receive buffer is empty Slave receive buffer is not empty Slave transmit buffer is empty Slave transmit buffer is not empty Indicates the highest mode supported by a unit. *1 Bit 3 Bit 2 Bit 1 Bit 0 LSB
Notes:
1. Since this LSI can support up to mode 2, bits 6 and 7 are fixed to 10. 2. The value of bit 4 can be selected by the STE bit in the IEBus master unit address register 1 (IEAR1). 3. The slave receive buffer is a buffer which is accessed during data write (control bits: H'A, H'B, H'E, H'F). In this LSI, the slave receive buffer corresponds to the IEBus receive buffer register (IERB001 to IERB128); and bit 1 is the value of the RXBSY flag in the IEBus receive status register (IERSR). 4. The slave transmit buffer is a buffer which is accessed during data read (control bits: H'3, H'7). In this LSI, the slave transmit buffer corresponds to the IEBus transmit buffer register (IETB001 to IETB128) and bit 0 is the value of the SRQ bit in the IEBus general flag registers (IEFLG).
Figure 20.2 Bit Configuration of Slave Status (SSR)
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(2)
Data Command Transfer (Control Bits: Read (H'3, H'7), Write (H'A, H'B, H'E, H'F))
In the case of data read (H'3, H'7), data in the data buffer of the slave unit is read in the master unit. In the case of data write (H'B or H'F) or command write (H'A or H'E), data received in the slave unit is processed in accordance with the operation specification of the slave unit. Notes: 1. The user can select data and commands freely in accordance with the system. 2. H'3, H'A, or H'B may lock depending on the communications condition and status. (3) Locked Address Read (Control Bits: H4, H5)
In the case of the locked address read (H'4 or H'5), the address (12 bits) of the master unit which issues the lock instruction is configured in bytes as shown in figure 20.3.
SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P
Figure 20.3 Locked Address Configuration (4) Locking/Unlocking (Control Bits: Setting (H'3, H'A, H'B), Cancellation: (H'6))
The lock function is used for message transfer over multiple communications frames. A locked unit receives data only from the unit which locked it. Locking and unlocking are described below. (a) Locking
When an acknowledge bit of 0 in the message length field is transmitted/received with the control bits (H'3, H'A, H'B) indicating the lock operation, and then the communications frame is completed before completion of data transmission/reception for the number of bytes specified by the message length bits, the slave unit is locked by the master unit. In this case, the bit (bit 2) relevant to locking in the byte data indicating the slave status is set to 1. Lock is set only when the number of data exceeds the maximum number of transfer bytes in one frame. Lock is not set by other error terminations.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
(b)
Unlocking
When the control bits indicate the lock (H'3, H'A, or H'B) or unlock (H'6) operation and the byte data for the number of bytes specified by the message length bits are transmitted/received in a single communications frame, the slave unit is unlocked by the master unit. In this case, the bit (bit 2) relevant to locking in the byte indicating the slave status is cleared to 0. Note that locking and unlocking are not done in broadcast communications. Note: * There are three ways to cause a locked unit to unlock itself. * Perform a power-on reset * Put the unit in deep standby mode * Issue an unlock command through the IEBus command register (IECMR) Note that the LCK flag in IEFLG can be used to check whether the unit is locked or unlocked. 20.1.4 Bit Format
Figure 20.4 shows the bit format (conceptual diagram) configuring the IEBus communications frame.
Logic 1 Logic 0
Preparation period Synchronous period
Data period
Halt period
Active low: Logic 1 = low level and logic 0 = high level Active high: Logic 1 = high level and logic 0 = low level
Figure 20.4 IEBus Bit Format (Conceptual Diagram) Each period of the bit format for use of active high signals is described below. * * * * Preparation period: first logic 1 period (high level) Synchronous period: subsequent logic 0 period (low level) Data period: period indicating bit value (logic 1: high level, logic 0: low level) Halt period: last logic 1 period (high level)
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
For use of active low signals, levels are reversed from the active high signals. The synchronous and data periods have approximately the same length. The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit). 20.1.5 Configuration
Figure 20.5 shows the entire block configuration and table 20.6 lists the functions of each block.
Transmit data buffer
Transmit controller
Peripheral bus
Peripheral bus interface
Register
IEBbus interface
IEBus
Receive controller
Receive data buffer
Figure 20.5 IEB Block Diagram
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Table 20.6 Functions of Each Block
Block Internal bus interface Function Internal bus interface * * IEBus interface * * Register Data width: 8 bits IEB register access
Interface conforms to IEBus specifications Outputs data from transmit controller to IEBus in IEBus specification bit format Picks out frame data in IEBus specification bit format to transfer to receive controller
IEB control register * * Register to control IEB Readable/writable from internal bus
Transmit controller
Transmits data in transmit buffer to IEBus * * Generates transmit frame combining header information in register and data in transmit buffer to transmits Detects transmit error
Receive controller
Stores data from IEBus in receive buffer * * Stores header information and data in received frame in register and receive buffer, respectively Detects receive error
Transmit data buffer
Buffer for data transmission * * Buffer that stores data to be transmitted to IEBus Buffer size: 128 bytes
Receive data buffer
Buffer for data reception * * Buffer that stores data received from IEBus Buffer size: 128 bytes
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.2
Input/Output Pins
Table 20.7 shows the IEB pin configuration. Table 20.7 Pin Configuration
Name IEB receive data pin IEB transmit data pin Abbreviation I/O IERxD IETxD I O Function Receive data input pin Transmit data output pin
20.3
Register Descriptions
The IEB has the following registers. Each register, in principle, has 8-bit width and is accessed in 8 bits. Table 20.8 Register Configuration
Register Name IEBus control register IEBus command register IEBus master control register IEBus master unit address register 1 IEBus master unit address register 2 IEBus slave address setting register 1 IEBus slave address setting register 2 IEBus transmit message length register IEBus reception master address register 1 IEBus reception master address register 2 Abbreviation IECTR IECMR IEMCR IEAR1 IEAR2 IESA1 IESA2 IETBFL IEMA1 IEMA2 R/W R/W W R/W R/W R/W R/W R/W R/W R R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'FFFF1000 H'FFFF1001 H'FFFF1002 H'FFFF1003 H'FFFF1004 H'FFFF1005 H'FFFF1006 H'FFFF1007 H'FFFF1009 H'FFFF100A Access Size 8 8 8 8 8 8 8 8 8 8
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Section 20 IEBus
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Controller (IEB) [R5S72612] [R5S72613]
Register Name
Abbreviation
R/W R R R R R R/(W)* R/W R/(W)* R/W R/W W R
Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Undefined Undefined
Address H'FFFF100B H'FFFF100C H'FFFF100E H'FFFF100F H'FFFF1010 H'FFFF1011 H'FFFF1012 H'FFFF1014 H'FFFF1015 H'FFFF1018
Access Size 8 8 8 8 8 8 8 8 8 8
IEBus receive control field register IERCTL IEBus receive message length register IEBus lock address register 1 IEBus lock address register 2 IEBus general flag register IEBus transmit status register IEBus transmit interrupt enable register IEBus receive status register IEBus receive interrupt enable register IEBus clock select register IEBus transmit data buffer registers 001 to 128 IEBus receive data buffer registers 001 to 128 Note: * IERBFL IELA1 IELA2 IEFLG IETSR IEIET IERSR IEIER IECKSR IETB001 to IETB128 IERB001 to IERB128
H'FFFF1100 to 8 H'FFFF117F H'FFFF1200 to 8 H'FFFF127F
Only 1 can be written to clear the flag.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.1
IEBus Control Register (IECTR)
IECTR is used to control the IEB operation. IECTR is initialized by a power-on reset or in deep standby.
Bit: 7 -- Initial value: R/W: 0 R 6 IOL 0 R/W 5 DEE 0 R/W 4 -- 0 R 3 RE 0 R/W 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6
IOL
0
R/W
Input/Output Level Selects input/output pin level (polarity) for the IERxD and IETxD pins. 0: Pin input/output is set to active low. (Logic 1 is low level and logic 0 is high level.) 1: Pin input/output is set to active high. (Logic 1 is high level and logic 0 is low level.)
5
DEE
0
R/W
Broadcast Receive Error Interrupt Enable If this bit is set to 1, a reception error interrupt occurs when the receive buffer is not in the receive enabled state during broadcast reception (when the RE bit is not set to 1 or the RXBSY flag is set.). At this time, the master address is stored in IEBus reception master address register 1 and 2. While this bit is 0, a reception error interrupt does not occur when the receive buffer is not in the receive enabled state, and the reception stops and enters the wait state. The master address is not saved. 0: A broadcast receive error is not generated up to the control field. 1: A broadcast receive error is generated up to the control field.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 4
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
3
RE
0
R/W
Receive Enable Enables/disables IEB reception. This bit must be set at the initial setting before frame reception. 0: Reception is disabled. 1: Reception is enabled.
2 to 0
0
R
Reserved These bits are always read as 0. The write value should always be 0.
20.3.2
IEBus Command Register (IECMR)
IECMR issues commands to control IEB communications. Since this register is a write-only register, the read value is undefined. IECMR is initialized by a power-on reset or in deep standby.
Bit: 7 -- Initial value: R/W: 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 0 W 2 1 CMD 0 W 0 W 0
Bit 7 to 3
Bit Name
Initial Value All 0
R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 2 to 0
Bit Name CMD
Initial Value 000
R/W W
Description Command Bits These bits issue a command to control IEB communications. When the CMX flag in IEFLG is set after the command issuance, the command is indicated to be in execution. When the CMX flag becomes 0, the operation state is entered. 000: No operation. Operation is not affected. 001: Unlock (required from other units)* 011: Stops master communications* 100: Undefined bits*
4 2 1
010: Requires communications as the master
101: Requires data transfer from the slave 110: Stops data transfer from the slave* 111: Undefined bits*
4 3
Notes: 1. Do not execute this command in slave communications. 2. This command is valid during master communications (MRQ = 1). In other states, this command issuance is ignored. If this command is issued in master communications, the communications controller immediately enters the wait state. At this time, the issued master transmission request ends (MRQ = 0). 3. This command is valid during slave communications (SRQ = 1). In other states, this command issuance is ignored. Once this command is issued in slave transmission, the SRQ flag is 0 before slave transmission. Therefore, a transmit request from the master is not responded to. If a transmit request is issued during slave transmission, the transmission stops and the wait state is entered (SRQ = 0). 4. Undefined bits. Issuing this command does not affect operation.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.3
IEBus Master Control Register (IEMCR)
IEMCR sets the communication conditions for master communications. IEMCR is initialized by a power-on reset or in deep standby.
Bit: 7 SS Initial value: 0 R/W: R/W 0 R/W 6 5 RN 0 R/W 0 R/W 0 R/W 4 3 2 CTL 0 R/W 0 R/W 0 R/W 1 0
Bit 7
Bit Name SS
Initial Value 0
R/W R/W
Description Broadcast/Normal Communications Select Selects broadcast or normal communications for master communications. 0: Broadcast communications for master communications 1: Normal communications for master communications
6 to 4
RN
000
R/W
Retransmission Counts Set the number of times retransmission is done when arbitration is lost in master communications. If arbitration is lost, the TXEAL flag in IETSR is set and transmission ends. 000: 0 001: 1 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 3 to 0
Bit Name CTL*
1
Initial Value 0000
R/W R/W
Description Control bits Set the control bits in the control field for master transmission. 0000: Reads slave status 0001: Undefined* 0010: Undefined*
3 3 2
0011: Reads data and locks*
0100: Reads locked address (lower 8 bits) 0101: Reads locked address (upper 4 bits) 0110: Reads slave status and unlocks* 0111: Reads data 1000: Undefined* 1001: Undefined*
3 3 2 2
1010: Writes command and locks* 1011: Writes data and locks* 1100: Undefined* 1101: Undefined*
3 3 2
1110: Writes command 1111: Writes data Notes: 1. CTL3 decides the data transfer direction of the message length bits in the message length field and data bits in the data field: CTL3 = 1: Transfer is from master unit to slave unit CTL3 = 0: Transfer is from slave unit to master unit 2. Control bits to lock and unlock 3. Setting prohibited.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.4
IEBus Master Unit Address Register 1 (IEAR1)
IEAR1 sets the lower four bits of the master unit address and communications mode. In master communications, the master unit address becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field. IEAR1 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 IMD 0 R/W 0 R/W 0 R/W 2 1 -- 0 R 0 STE 0 R/W
IARL4 Initial value: 0 R/W: R/W 0 R/W 0 R/W
Bit 7 to 4
Bit Name IARL4
Initial Value 0000
R/W R/W
Description Lower 4 Bits of IEBus Master Unit Address Set the lower 4 bits of the master unit address. This register becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field
3, 2
IMD
00
R/W
IEBus Communications Mode Set IEBus communications mode. 00: Communications mode 0 01: Communications mode 1 10: Communications mode 2 11: Setting prohibited
1
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 901 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 0
Bit Name STE
Initial Value 0
R/W R/W
Description Slave Transmission Setting Sets bit 4 in the slave status register. Transmitting the slave status register informs the master unit that the slave transmission enabled state is entered by setting this bit to 1. Note that this bit only sets the slave status register value and does not directly affect slave transmission. 0: Bit 4 in the slave status register is 0 (slave transmission stop state) 1: Bit 4 in the slave status register is 1 (slave transmission enabled state)
20.3.5
IEBus Master Unit Address Register 2 (IEAR2)
IEAR2 sets the upper eight bits of the master unit address. In master communications, this register becomes the master address field value. In slave communications, this register is compared with the received slave address field. IEAR2 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 IARU8 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
Bit 7 to 0
Bit Name IARU8
Initial Value All 0
R/W R/W
Description Upper 8 Bits of IEBus Master Unit Address Set the upper 8 bits of the master unit address. This register becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field
Rev. 2.00 Sep. 07, 2007 Page 902 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.6
IEBus Slave Address Setting Register 1 (IESA1)
IESA1 sets the lower four bits of the communications destination slave unit address. IESA1 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 ISAL4 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 4 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 7 to 4
Bit Name ISAL4
Initial Value 0000
R/W R/W
Description Lower 4 Bits of IEBus Slave Address These bits set the lower 4 bits of the communication destination slave unit address
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
20.3.7
IEBus Slave Address Setting Register 2 (IESA2)
IESA2 sets the upper eight bits of the communications destination slave unit address. IESA2 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 ISAU8 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
Bit 7 to 0
Bit Name ISAU8
Initial Value All 0
R/W R/W
Description Upper 8 Bits of IEBus Slave Address Set upper 8 bits of the communications destination slave unit address
Rev. 2.00 Sep. 07, 2007 Page 903 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.8
IEBus Transmit Message Length Register (IETBFL)
IETBFL sets the message length for master or slave transmission. IETBFL is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 TBFL Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
Bit 7 to 0
Bit Name TBFL
Initial Value All 0
R/W R/W
Description Transmit Message Length Set the message length for master transmission. Set the message length that does not exceed the maximum transmit bytes in communications mode. H'01: 1 byte H'02: 2 bytes : H'7F: 127 bytes H'80: 128 bytes H'81: Undefined* : H'FF: Undefined* H'00: Undefined*
Note:
*
Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 904 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.9
IEBus Reception Master Address Register 1 (IEMA1)
IEMA1 indicates the lower four bits of the communication destination master unit address in slave/broadcast reception. IEMA1 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 IMAL4 Initial value: R/W: 0 R 0 R 0 R 0 R 4 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 7 to 4
Bit Name IMAL4
Initial Value 0000
R/W R
Description Lower Four Bits of IEBus Reception Master Address Indicates the lower four bits of the communication destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag. If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is not in the receive enabled state at control field reception, a receive error interrupt is generated and the lower four bits of the master address are stored in IEMA1.
3 to 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 905 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.10 IEBus Reception Master Address Register 2 (IEMA2) IEMA2 indicates the upper eight bits of the communications destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag in IERSR. If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer is not in the receive enabled state at control field reception, a receive error interrupt is generated and the upper eight bits of the master address are stored in IEMA2. This register cannot be modified by a write. IEMA2 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 2 1 0
IMAU8 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name IMAU8
Initial Value All 0
R/W R
Description Upper Eight Bits of IEBus Reception Master Address Indicates the upper eight bits of the communications destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag. If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is not in the receive enabled state at control field reception, a receive error interrupt is generated and the upper eight bits of the master address are stored in IEMA2.
Rev. 2.00 Sep. 07, 2007 Page 906 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.11 IEBus Receive Control Field Register (IERCTL) IERCTL indicates the control field value in slave/broadcast reception. This register is enabled when slave/broadcast receive starts, and the contents are changed at the time of setting the RXS flag in IERSR. This register cannot be modified. IERCTL is initialized by a power-on reset or in deep standby.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 0 R 3 2 RCTL 0 R 0 R 0 R 1 0
Bit 7 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
RCTL
0000
R
IEBus Receive Control Field Indicates the control field value in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag.
Rev. 2.00 Sep. 07, 2007 Page 907 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.12 IEBus Receive Message Length Register (IERBFL) IERBFL indicates the message length field in slave/broadcast reception. This register is enabled when slave/broadcast receive starts, and the contents are changed at the time of setting the RXS flag in IERSR. This register cannot be modified. IERBFL is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 RBFL Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 2 1 0
Bit 7 to 0
Bit Name RBFL
Initial Value All 0
R/W R
Description IEBus Receive Message Length Indicates the contents of the message length field in slave/broadcast reception.
20.3.13
IEBus Lock Address Register 1 (IELA1)
IELA1 specifies the lower eight bits of a locked address when a unit is locked. IELA1 is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 3 ILAL8 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 2 1 0
Bit 7 to 0
Bit Name ILAL8
Initial Value All 0
R/W R
Description Lower Eight Bits of IEBus Lock Address Indicates the lower eight bits of the master unit address when a unit is locked. These bits are valid only when the LCK bit in IEFLG is set.
Rev. 2.00 Sep. 07, 2007 Page 908 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.14 IEBus Lock Address Register 2 (IELA2) IELA2 specifies the upper four bits of a locked address when a unit is locked. IELA2 is initialized by a power-on reset or in deep standby.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 0 R 3 2 1 0
ILAU4 0 R 0 R 0 R
Bit 7 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
3 to 0
ILAU4
0000
R
Upper Four Bits of IEBus Locked Address Stores the upper four bits of the master unit address when a unit is locked. These bits are valid only when the LCK bit in IEFLG is set
Rev. 2.00 Sep. 07, 2007 Page 909 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.15 IEBus General Flag Register (IEFLG) IEFLG indicates the IEB command execution status, lock status and slave address match, and broadcast reception detection. IEFLG is initialized by a power-on reset or in deep standby.
Bit: 7 6 5 4 SRE 0 R 3 LCK 0 R 2 -- 0 R 1 RSS 0 R 0 GG 0 R
CMX MRQ SRQ Initial value: R/W: 0 R 0 R 0 R
Bit 7
Bit Name CMX
Initial Value 0
R/W R
Description Command Execution Status Indicates the command execution status. 0: Command execution is completed 1: A command is being executed [Setting condition] * When a master communications request or slave transmit request command is issued while the MRQ, SRQ, or SRE flag is set When a command execution has been completed
[Clearing condition] * 6 MRQ 0 R Master Communications Request Indicates whether the unit is in the communications request state as a master unit. 0: The unit is not in the communications request state as a master unit 1: The unit is in the communications request state as a master unit [Setting condition] * When the CMX flag is cleared to 0 after the master communications request command is issued When the master communications have been completed
[Clearing condition] *
Rev. 2.00 Sep. 07, 2007 Page 910 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 5
Bit Name SRQ
Initial Value 0
R/W R
Description Slave Transmission Request Indicates whether the unit is in the transmit request state as a slave unit. 0: The unit is not in the transmit request state as a slave unit 1: The unit is in the transmit request state as a slave unit [Setting condition] * When the CMX flag is cleared to 0 after the slave transmit request command is issued. When a slave transmission has been completed.
[Clearing condition] * 4 SRE 0 R Slave Receive Status Indicates the execution status in slave/broadcast reception. 0: Slave/broadcast reception is not being executed 1: Slave/broadcast reception is being executed [Setting condition] * When the slave/broadcast reception is started while the RE bit in IECTR is set to 1. When the slave/broadcast reception has been completed.
[Clearing condition] *
Rev. 2.00 Sep. 07, 2007 Page 911 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 3
Bit Name LCK
Initial Value 0
R/W R
Description Lock Status Indication Set to 1 when a unit is locked by a lock request from the master unit. IELA1 and IELA2 values are valid only when this flag is set to 1. 0: A unit is unlocked 1: A unit is locked [Setting condition] * When data for the number of bytes specified by the message length is not received after the control bits that make the unit locked are received from the master unit. (The LCK flag is set to 1 only when the message length exceeds the maximum number of transfer bytes in one frame. This flag is not set by completion of other errors.) When an unlock condition is satisfied or when an unlock command is issued.
[Clearing condition] * 2 0 R
Reserved This bit is always read as 0. The write value should always be 0.
1
RSS
0
R
Receive Broadcast Bit Status Indicates the received broadcast bit value. This flag is valid when the slave/broadcast reception is started. (This flag is changed at the time of setting the RXS flag.) The previous value remains unchanged until the next slave/broadcast reception is started. 0: Received broadcast bit is 0 1: Received broadcast bit is 1
Rev. 2.00 Sep. 07, 2007 Page 912 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 0
Bit Name GG
Initial Value 0
R/W R
Description General Broadcast Reception Acknowledgement Set to 1 when the slave address is acknowledged as H'FFF in broadcast reception. Like the receive broadcast bit, this flag is valid when the slave/broadcast reception is started. (This flag is changed at the time of setting the RXS flag in IERSR.) The previous value remains unchanged until the next slave/broadcast reception is started. This flag is cleared to 0 in slave normal reception. 0: (1) A unit is in slave reception (2) When H'FFF is not acknowledged in the slave address field in broadcast reception 1: When H'FFF is acknowledged in the slave address field in broadcast reception
20.3.16 IEBus Transmit Status Register (IETSR) IETSR detects events such as transmit start, transmit normal completion, and transmit error end. Each status flag in IETSR corresponds to a bit in the IEBus transmit interrupt enable register (IEIET) that enables or disables each interrupt. This register is cleared by writing 1 to each bit. IETSR is initialized by a power-on reset or in deep standby.
Bit: 7 -- Initial value: R/W: 0 R 6
TXS
5
TXF
4 -- 0 R
3
TXE AL
2
TXE TTME
1
TXE RO
0
TXE ACK
0 0 R/(W)* R/(W)*
0 0 0 0 R/(W)* R/(W)*R/(W)* R/(W)*
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 913 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 6
Bit Name TXS
Initial Value 0
R/W R/(W)*
Description Transmit Start Indicates that the IEB starts transmission. [Setting condition] * During master transmission, the arbitration is won and the master address field transmission is completed When 1 is written
[Clearing condition] * 5 TXF 0 R/(W)* Transmit Normal Completion Indicates that data for the number of bytes specified by the message length bits has been transmitted with no error. [Setting condition] * When data for the number of bytes specified by the message length bits has been transmitted normally When 1 is written
[Clearing condition] * 4 0 R Reserved This bit is always read as 0. The write value should always be 0. 3 TXEAL 0 R/(W)* Arbitration Loss The IEB retransmits from the start bit for the number of times specified by the RN bit in IEMCR if the arbitration has been lost in master communications. If the arbitration has been lost for the specified number of times, the TXEAL is set to enter the wait state. If the arbitration has been won within retransmit for the specified number of times, this flag is not set to 1. This flag is set only when the arbitration has been lost and the wait state is entered. [Setting condition] * When the arbitration has been lost during data transmission and the transmission has been terminated When 1 is written
[Clearing condition] *
Rev. 2.00 Sep. 07, 2007 Page 914 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 2
Bit Name TXETTME
Initial Value 0
R/W R/(W)*
Description Transmit Timing Error Set to 1 if data is not transmitted at the timing specified by the IEB protocol during data transmission. The IEB sets this bit and enters the wait state. [Setting condition] * When a timing error occurs during data transmission When 1 is written
[Clearing condition] * 1 TXERO 0 R/(W)* Overflow of Maximum Number of Transmit Bytes in One Frame Indicates that the maximum number of bytes defined by the communications mode have been transmitted because a NAK has been received from the receive unit and retransmit has been performed, or that transmission has not been completed because the message length value exceeds the maximum number of transmit bytes in one frame. The IEB sets this bit and enters the wait state. [Setting condition] * When the transmit has not been completed although the maximum number of bytes defined by the communications mode have been transmitted When 1 is written
[Clearing condition] *
Rev. 2.00 Sep. 07, 2007 Page 915 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 0
Bit Name TXEACK
Initial Value 0
R/W R/(W)*
Description Acknowledge Bit Status Indicates the data received in the acknowledge bit of the data field. * Acknowledge bit other than in the data field The IEB terminates the transmission and enters the wait state if a NAK is received. In this case, this bit is set to 1. * Acknowledge bit in the data field The IEB retransmits data up to the maximum number of bytes defined by the communications mode until an ACK is received from the receive unit if a NAK is received from the receive unit during data field transmission. In this case, when an ACK is received from the receive unit during retransmission, this flag is not set and transmission will be continued. When transmission is terminated without receiving an ACK, this flag is set to 1. Note: This flag is invalid in broadcast communications. [Setting condition] * * When the acknowledge bit of 1 (NAK) is detected When 1 is written [Clearing condition]
Note:
*
only 1 can be written to clear the flag.
Rev. 2.00 Sep. 07, 2007 Page 916 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.17 IEBus Transmit Interrupt Enable Register (IEIET) IEIET enables/disables interrupts for sources such as transmit start, transmit normal completion, and transmit error completion in IETSR. IEIET is initialized by a power-on reset or in deep standby.
Bit: 7 -- Initial value: R/W: 0 R 6
TXSE
5
TXFE
4 -- 0 R
3
2
1
0
TX TXE TX TXE EALE TTMEE EROE ACKE
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6
TXSE
0
R/W
Transmit Start Interrupt Enable Enables/disables a transmit start (TXS) interrupt. 0: Disables a transmit start (TXS) interrupt 1: Enables a transmit start (TXS) interrupt
5
TXFE
0
R/W
Transmit Normal Completion Interrupt Enable Enables/disables a transmit normal completion (TXF) interrupt. 0: Disables a transmit normal completion (TXF) interrupt 1: Enables a transmit normal completion (TXF) interrupt
4
0
R
Reserved This bit is always read as 0. The write value should always be 0.
3
TXEALE
0
R/W
Arbitration Loss Interrupt Enable Enables/disables an arbitration loss (TXEAL) interrupt. 0: Disables an arbitration loss (TXEAL) interrupt 1: Enables an arbitration loss (TXEAL) interrupt
Rev. 2.00 Sep. 07, 2007 Page 917 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 2
Bit Name
Initial Value
R/W R/W
Description Transmit Timing Error Interrupt Enable Enables/disables a transmit timing error (TXETTMEE) interrupt. 0: Disables a transmit timing error (TXETTMEE) interrupt 1: Enables a transmit timing error (TXETTMEE) interrupt
TXETTMEE 0
1
TXEROE
0
R/W
Overflow of Maximum Number of Transmit Bytes in One Frame Interrupt Enable Enables/disables an overflow of the maximum number of transmit bytes in one frame (TXEROE) interrupt. 0: Disables an overflow of the maximum number of transmit bytes in one frame (TXEROE) interrupt 1: Enables an overflow of the maximum number of transmit bytes in one frame (TXEROE) interrupt
0
TXEACKE
0
R/W
Acknowledge Bit Interrupt Enable Enables/disables an acknowledge bit (TXEACKE) interrupt. 0: Disables an acknowledge bit (TXEACKE) interrupt 1: Enables an acknowledge bit (TXEACKE) interrupt
Rev. 2.00 Sep. 07, 2007 Page 918 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.18 IEBus Receive Status Register (IERSR) IERSR detects receive busy, receive start, receive normal completion, or receive completion with an error. Each status flag in IERSR corresponds to a bit in the IEIER that enables/disables each interrupt. This register is cleared by writing 1 to each bit. IERSR is initialized by a power-on reset or in deep standby.
Bit: 7
RX BSY
6
RXS
5
RXF
4
RX EDE
3
2
1
0
RX EPE
RX RXE RX EOVE RTME EDLE
Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Bit 7
Bit Name RXBSY
Initial Value 1
R/W R/(W)*
Description Receive Busy Indicates that the receive data is stored in the receive data buffer (IERB001 to IERB128). Clear this bit after reading out all data. The next receive data cannot be received while this bit is set. [Setting condition] * When all receive data has been written to the receive data buffer. When 1 is written
[Clearing condition] * 6 RXS 0 R/(W)* Receive Start Detection Indicates that the IEB starts reception. [Setting condition] * When the data from the master unit to message length field has been received correctly in slave reception When 1 is written
[Clearing condition] *
Rev. 2.00 Sep. 07, 2007 Page 919 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 5
Bit Name RXF
Initial Value 0
R/W R/(W)*
Description Receive Normal Completion Indicates that data for the number of bytes specified by the message length bits has been received normally. [Setting condition] * When data for the number of bytes specified by the message length bits has been received normally. [Clearing condition] * When 1 is written Broadcast Receive Error Indicates that data could not be received because the receive buffer is not in the receive enabled state (when the RE bit is not set to 1 or the RXBSY flag is set.) during receiving control field broadcast reception. This bit functions when the DEE bit in IECTR is set to 1. [Setting condition] * When data could not be received during broadcast reception. [Clearing condition] * When 1 is written Receive Overrun Flag Used to indicate the overrun during data reception. The IEB sets this flag when the IEB receives the next byte data while the receive data has not been read (the RXBSY flag is not cleared). If this case, the IEB assumes that an overrun error has occurred and returns a NAK to the communications destination unit. The communications destination unit retransmits data up to the maximum number of transmit bytes. The IEB, however, returns a NAK when the RXBSY flag remains set. If the RXBSY flag is cleared to 0, the IEB returns an ACK, and receives the next data. In broadcast reception, if the RXBSY flag is set during data receive start, the IEB immediately enters the wait state. This flag becomes enabled only after the receive start flag (RXS) is set. [Setting condition] * When the next byte data is received while the RXBSY flag is not cleared. [Clearing condition] * When 1 is written
4
RXEDE
0
R/(W)*
3
RXEOVE
0
R/(W)*
Rev. 2.00 Sep. 07, 2007 Page 920 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 2
Bit Name RXERTME
Initial Value 0
R/W R/(W)*
Description Receive Timing Error Set to 1 if data is not received at the time specified by the IEB protocol during data reception. The IEB sets this bit and enters the wait state. This flag is enabled only after the receive start flag (RXS) is set. If this error occurs before the receive start flag (RXS) is set, the IEB stops communication and enters the wait state. This bit is not set in this case. [Setting condition] * * When a timing error occurs during data reception When 1 is written [Clearing condition]
1
RXEDLE
0
R/(W)*
Overflow of Maximum Number of Receive Bytes in One Frame Indicates that the data reception has not finished within the maximum number of bytes defined by the communications mode because of a parity error or overrun error causing the retransfer of data, or that reception has not been completed because the message length value exceeds the maximum number of receive bytes in one frame. The IEB sets the RXEDLE flag and enters the wait state. This flag is enabled only after the receive start flag (RXS) is set. If this error occurs before the receive start flag is set, the IEB stops communication and enters the wait state. This bit is not set in this case. [Setting condition] * When the reception has not been completed within the maximum number of bytes defined by communications mode. When 1 is written
[Clearing condition] *
Rev. 2.00 Sep. 07, 2007 Page 921 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 0
Bit Name RXEPE
Initial Value 0
R/W R/(W)*
Description Parity Error Indicates that a parity error has occurred during data field reception. If a parity error occurs before data field reception, the IEB immediately enters the wait state and the RXEPE flag is not set. If a parity error occurs when the maximum number of receive bytes in one frame have not been received, the RXEPE flag is not set yet. When a parity error occurs, the IEB returns a NAK to the communications destination unit via the acknowledge bit. In this case, the communications destination unit continues retransfer up to the maximum number of receive bytes in one frame and if the reception has been completed normally by clearing the parity error, the RXEPE flag is not set. If the parity error is not cleared when the reception is terminated before receiving data for the number of bytes specified by the message length, the RXEPE flag is set. In broadcast reception, if a parity error occurs during data field reception, the IEB enters the wait state immediately after setting the RXEPE flag. This flag is enabled only after the receive start flag (RXS) is set. If this error occurs before the receive start flag is set, the IEB stops communication and enters the wait state. This bit is not set in this case. [Setting condition] * When the parity bit of the last data of the data field is not correct after the maximum number of receive bytes have been received When 1 is written
[Clearing condition] * Note: * only 1 can be written to clear the flag.
Rev. 2.00 Sep. 07, 2007 Page 922 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.19 IEBus Receive Interrupt Enable Register (IEIER) IEIER enables/disables interrupts for sources such as IERSR receive busy, receive start, receive normal completion, and receive error completion. IEIER is initialized by a power-on reset or in deep standby.
Bit: 7
RX BYSE
6
RX SE
5
RX FE
4
3
2
1
0
RX EPEE
RX RXE RXE RXE EDEE OVEE RTMEE DLEE
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name RXBSYE
Initial Value 0
R/W R/W
Description Receive Busy Interrupt Enable Enables/disables a receive busy interrupt (RXBSY) 0: Disables a receive busy (RXBSY) interrupt 1: Enables a receive busy (RXBSY) interrupt
6
RXSE
0
R/W
Receive Start Interrupt Enable Enables/disables a receive start (RXS) interrupt 0: Disables a receive start (RXS) interrupt 1: Enables a receive start (RXS) interrupt
5
RXFE
0
R/W
Receive Normal Completion Enable Enables/disables a receive normal completion (RXF) interrupt 0: Disables a receive normal completion (RXF) interrupt 1: Enables a receive normal completion (RXF) interrupt
4
RXEDEE
0
R/W
Broadcast Receive Error Interrupt Enable Enables/disables a broadcast receive error (RXEDE) interrupt 0: Disables a broadcast receive error (RXEDE) interrupt 1: Enables a broadcast receive error (RXEDE) interrupt
Rev. 2.00 Sep. 07, 2007 Page 923 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 3
Bit Name RXEOVEE
Initial Value 0
R/W R/W
Description Overrun Control Flag Interrupt Enable Enables/disables an overrun control flag (RXEOVE) interrupt 0: Disables an overrun control flag (RXEOVE) interrupt 1: Enables an overrun control flag (RXEOVE) interrupt
2
RXERTMEE
0
R/W
Receive Timing Error Interrupt Enable Enables/disables a receive timing error (RXERTME) interrupt. 0: Disables a receive timing error (RXERTME) interrupt 1: Enables a receive timing error (RXERTME) interrupt
1
RXEDLEE
0
R/W
Overflow of Maximum Number of Receive Bytes in One Frame Interrupt Enable Enables/disables an overflow of the maximum number of receive bytes in one frame (RXEDLE) interrupt 0: Disables an overflow of the maximum number of receive bytes in one frame (RXEDLE) interrupt 1: Enables an overflow of the maximum number of receive bytes in one frame (RXEDLE) interrupt
0
RXEPEE
0
R/W
Parity Error Interrupt Enable Enables/disables a parity error (RXEPE) interrupt 0: Disables a parity error (RXEPE) interrupt 1: Enables a parity error (RXEPE) interrupt
20.3.20 IEBus Clock Selection Register (IECKSR) IECKSR is an 8-bit readable/writable register that specifies the clock used in the IEB. IECKSR can be read from or written to even when the IEB module is stopped. IECKSR is initialized by a power-on reset or in deep standby mode.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 CKS3 0 R/W 3 -- 0 R 0 R/W 2 1 CKS[2:0] 0 R/W 0 R/W 0
Rev. 2.00 Sep. 07, 2007 Page 924 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
Bit 7 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4
CKS3
0
R/W
Input Clock Selection 3*1*2 Specifies the clock the IEB uses 0: Peripheral clock (P) 1: AUDIO_X1, AUDIO_X2
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2 to 0
CKS[2:0]
000
R/W
Input Clock Selection 2 to 0*1 Specifies the division ratio for the clock IEB uses 000: IEB uses the clock of IEB specified by CKS3 (IEB = 6 MHz, 6.29 MHz) 001: IEB uses the 1/2 divided clock of IEB specified by CKS3 (IEB = 12 MHz, 12.58 MHz) 010: IEB uses the 1/3 divided clock of IEB specified by CKS3 (IEB = 18 MHz, 18.87 MHz) 011: IEB uses the 1/4 divided clock of IEB specified by CKS3 (IEB = 24 MHz, 25.16 MHz) 100: IEB uses the 1/5 divided clock of IEB specified by CKS3 (IEB = 30 MHz, 31.45 MHz) 101: IEB uses the 1/6 divided clock of IEB specified by CKS3 (IEB = 36 MHz, 37.74 MHz) 110: Setting prohibited 111: Setting prohibited
Notes: 1. Do not change the setting of CKS3 to CKS0 while IEBus is in transmit/receive operation 2. After the MSTP4 bit in STBCR2 is cleared to 0 to start the operation of the IEB with the CKS3 bit set to 1 (the AUDIO_X1 and AUDIO_X2 clocks are used), do not set the MSTP4 bit to 1 (clock supply to the IEB except IECKSR is stopped). As for the setting of the STBCR2 register, see section 27, Power-Down Modes.
Rev. 2.00 Sep. 07, 2007 Page 925 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128) IETB001 to IETB128 are 128-byte (8 x 128) buffers to which data to be transmitted during master transmission is written. IETB001 to IETB128 are initialized by a power-on reset or in deep standby. The initial values are undefined.
Bit: 7 6 5 4 TBn Initial value: R/W: -- W* -- W* -- W* -- W* -- -- -- -- W* W* W* W* W* 3 2 1 0
[Legend] n = 0011 to 128
Bit 7 to 0
Bit Name TBn
Initial Value
R/W
Description IEBus Transmit Data Buffer Data to be transmitted in the data field during master transmission is written to TB001 to TB128. Data is written starting with TB001 for the start 1-byte data, followed by TB002 and TB003 and so on according to the transmission order, and TB128 stores the last data.
Undefined W*
Note:
*
Writing to these bits during master transmission (MRQ in IEFLG is 1) is prohibited.
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128) IERB001 to IERB128 are 128-byte (8 x 128) buffers to which data to be transmitted during slave transmission is written. IERB001 to IERB128 are initialized by a power-on reset or in deep standby. The initial values are undefined.
Bit: 7 6 5 4 RBn Initial value: R/W: -- R* -- R* -- R* -- R* -- R* -- R* -- R* -- R* 3 2 1 0
[Legend] n = 0011 to 128
Bit 7 to 0
Bit Name RBn
Initial Value
R/W
Description IEBus Receive Data Buffer Data in RB001 to RB128 can be read when the RXBSY bit in IERSR is set to 1. Data read from RB001 to RB128 is the field data during slave receive. Receive data is written starting with RB001 for the start 1-byte data, followed by RB002 and RB003 and so on, and RB128 stores the last data.
Undefined R*
Note:
*
Reading these bits during slave reception (SRE in IEFLG is 1 and RXBSY in IERSR is 0) is prohibited. (Read value is undefined.)
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.4
20.4.1
Data Format
Transmission Format
Figure 20.6 shows the relationship between the transfer format and each register during the IEBus data transmission.
[In master transmission] Communications frame Master address Slave address Control bits
Message length bits
Data bits
Register
IEAR1, IEAR2
IESA1, IESA2
IEMCR
IETBFL
IETB001 to IETB128
[In slave transmission] Communications frame Master address Slave address Control bits
Message length bits
Data bits
(*2) Register Notes: 1. 2. 3. (*1) IEAR1, IEAR2 (*3) IETBFL
IETB001 to IETB128
In slave transmission, the received master address is not saved. If the unit is locked, address comparison performed. The received slave address is compared with IEAR1 and IEAR2, and if these addresses match, operation continues. In slave transmission, the received control bits are not saved. The received control bits are decoded to decide the subsequent operation.
Figure 20.6 Relationship between Transfer Format and Each Register during IEBus Data Transmission
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.4.2
Reception Format
Figure 20.7 shows the relationship between the transfer format and each register during the IEBus data reception.
[In slave reception] Communications frame Master address Slave address Control bits
Message length bits
Data bits
(*) Register IEMA1, IEMA2 IEAR1, IEAR2 IERCTL IERBFL
IERB001 to IERB128
Note: * Received slave address is compared with IEAR1 and IEAR2. If they match, the subsequent operations are performed.
[In master reception] Communications frame Master address Slave address Control bits
Message length bits
Data bits
Register
IEAR1, IEAR2
IESA1, IESA2
IEMCR
IERBFL
IERB001 to IERB128
Figure 20.7 Relationship between Transfer Format and Each Register during IEBus Data Reception
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.5
20.5.1
Software Control Flows
Initial Setting
Figure 20.8 shows the flowchart for the initial setting.
Start
[PDCR4 register in PFC setting1] IERxD, IETxD pins enable
[STBCR2 register setting2] Module stop release
[IECTR register setting] Pin porarity setting Receive enable
[IECKSR register setting] Selection of clock supplied to IEB
[IEAR1, IEAR2 register setting] Transmission mode Master address
[IEIET, IEIER register setting] Interrupt enable
End
Notes: 1. 2.
As for setting of PDCR4 register in PFC, see section 25, Pin Function Controller (PFC). As for setting of STBCR2 register, see section 27, Power-Down Modes.
Figure 20.8 Flowchart for Initial Setting
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.5.2
Master Transmission
Figure 20.9 shows the flowchart for master transmission.
Start
Initial setting
[IESA1, IESA2 register setting] Slave address
[IECMR register setting] Master communications request command
[IEMCR register setting] Broadcast/normal selection Retransfer counts Control bits
Transmit error interrupt (TXE***) Transmit start interrupt
Transmit start interrupt (TXS) [IETBFL register setting] Message length bits Interrupt processing IETSR[TXS] clear
[IETB001 to IETB128 setting] Transmit data
Transmit completion interrupt
Transmit error interrupt (TXE***)
Transmit completion interrupt (TXF) Interrupt processing IETSR[TXF] clear Interrupt processing IETSR[TXE***] clear
End
Figure 20.9 Flowchart for Master Transmission
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.5.3
Slave Reception
Figure 20.10 shows the flowchart for slave reception.
Start
Initial setting
Receive start interrupt
Receive error interrupt (RXE***)
Receive start interrupt (RXS) Interrupt processing IERSR[RXS] clear
Receive completion interrupt
Receive error interrupt (RXE***)
Receive completion interrupt (RXF) Interrupt processing IERSR[RXF] clear Receive data read (IERB001 to IERB128) IERSR[RXBSY] clear Interrupt processing IERSR[RXE***] clear
End
Figure 20.10 Flowchart for Slave Reception
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.5.4
Master Reception
Figure 20.11 shows the flowchart for master reception.
Start
Initial setting
[IESA1, IESA2 register setting] Slave address
[IECMR register setting] Master communications request command
[IEMCR register setting] Broadcast/normal selection Retransfer counts Control bits
Receive start interrupt
Receive error interrupt (RXE***)
Receive start interrupt (RXS) Interrupt processing IERSR[RXS] clear
Receive completion interrupt
Receive error interrupt (RXE***)
Receive completion interrupt (RXF) Interrupt processing IERSR[RXF] clear Receive data read (IERB001 to IERB128) IERSR[RXBSY] clear Interrupt processing IETSR[TXE***] clear IERSR[RXE***] clear
End
Figure 20.11 Flowchart for Master Reception
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.5.5
Slave Transmission
Figure 20.12 shows the flowchart for slave transmission.
Start
Initial setting
[IETBFL register setting] Message length bits
[IECMR register setting] Slave communications request command
[IETB001 to IETB128 setting] Transmit data Transmit start interrupt
Transmit error interrupt (TXE***)
Transmit start interrupt (TXS) Interrupt processing IETSR[TXS] clear
Transmit completion interrupt
Transmit error interrupt (TXE***)
Transmit completion interrupt (TXF) Interrupt processing IETSR[TXF] clear Interrupt processing IETSR[TXE***] clear
End
Figure 20.12 Flowchart for Slave Transmission
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.6
20.6.1
Operation Timing
Master Transmit Operation
Figure 20.13 shows the timing for master transmit operation.
Slave reception DL Dn-1 Dn HD MA SA CT Master transmission DL D1 D2 Dn-1 Dn
IECMR IEFLG CMX MRQ
Master transmission request
SRQ SRE IETSR TXS TXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field
Figure 20.13 Master Transmit Operation Timing
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.6.2
Slave Receive Operation
Figure 20.14 shows the timing for slave receive operation.
Broadcast reception DL IEFLG RSS CMX MRQ SRQ SRE Dn-1 Dn HD MA SA CT Slave reception DL D1 D2 Dn-1 Dn
IERSR RXS RXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field
Figure 20.14 Slave Receive Operation Timing
Rev. 2.00 Sep. 07, 2007 Page 936 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.6.3
Master Receive Operation
Figure 20.15 shows the timing for master receive operation.
Slave reception DL Dn-1 Dn HD MA SA CT Master reception DL D1 D2 Dn-1 Dn
IECMR IEFLG CMX MRQ SRQ
Master transmission request
SRE IETSR RXS RXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field
Figure 20.15 Master Receive Operation Timing
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.6.4
Slave Transmit Operation
Figure 20.16 shows the timing for slave transmit operation.
Slave reception DL Dn-1 Dn HD MA SA CT Slave transmission DL D1 D2 Dn-1 Dn
IECMR IEFLG CMX
Slave transmission request
MRQ SRQ SRE IERSR RXS RXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field
Figure 20.16 Slave Transmit Operation Timing
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.7
Interrupt Sources
IEB interrupt sources include the following: * * * * * * * * * * * * * * Transmit start (TXS) Transmit normal completion (TXF) Arbitration loss (TXEAL) Transmit timing error (TXETTME) Overflow of the maximum number of transmit bytes in one frame (TXERO) Acknowledge bits (TXEACK) Receive busy (RXBSY) Receive start (RXS) Receive normal completion (RXF) Broadcast Receive Error (RXEDE) Receive overrun flag (RXEOVE) Receive timing error (RXERTME) Overflow of the maximum number of receive bytes in one frame (RXEDLE) Parity error (RXEPE)
Each source has bits corresponding to the IEBus transmit interrupt enable register (IEIET) and the IEBus receive interrupt enable register (IEIER) and can enable/disable interrupts. Each source also has status flags corresponding to the IEBus transmit status register (IETSR) and IEBus receive status register (IERSR). Reading the status flags enables determination of the interrupt sources. Figure 20.17 shows the relations between the IEB interrupt sources.
Rev. 2.00 Sep. 07, 2007 Page 939 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
IETSR TXS IEIET TXSE TXF TXFE TXEAL TXEALE TXETTME TXETTMEE TXERO TXEROE TXEACK TXEACKE
CPU IEB interrupts
IERSR RXBSY IEIER RXBSYE RXS RXSE RXF RXFE RXEDE RXDEE RXEOVE RXEOVEE RXERTME RXERTMEE RXEDLE RXEDLEE RXEPE RXEPEE
Figure 20.17 Relations between IEB Interrupt Sources
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Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
20.8
20.8.1
Usage Notes
Notes when the Communications have not been Completed within the Maximum Number of Transmit Bytes
(1)
Data Transmission
During the data transmission, when the maximum number of bytes defined by the communications mode have been transmitted because a NAK has been received from the receive unit, or when transmission has not been completed within the maximum number of transmit bytes because the message length value exceeds it, the IEB sets the error flag of IETSR and enters the wait state. In this case, the IEB transmits data for the maximum number of transmit bytes + one byte. Then, if a NAK has been received in an acknowledge bit of data for the maximum number of transmit bytes + one byte, the TXERO flag is set. If an ACK is received, the TXF flag is set. Figure 20.18 shows the operation timing when the transmission has not been completed within the maximum number of transmit bytes.
HD: MA: SA: CT: DL: Dn: Master transmission HD IETSR TXER0 MA SA CT DL D1 D2 Dn-1 Dn Dn+1 Header Master address field Slave address field Control field Message length field Data field (n = Max. no. of transfer bytes)
NAK is received in Dn + 1
IETSR TXF
ACK is received in Dn + 1
Figure 20.18 Operation Timing when Transmission has not been Completed within Maximum Number of Transmit Bytes (2) Data Reception
During the data reception, when reception has not been completed within the maximum number of bytes defined by the communications mode because of a parity error or overrun error causing the retransfer of data, or when reception has not been completed because the message length value exceeds the maximum number of receive bytes, the IEB sets the error flag of IERSR and enters
Rev. 2.00 Sep. 07, 2007 Page 941 of 1312 REJ09B0320-0200
Section 20 IEBus
TM
Controller (IEB) [R5S72612] [R5S72613]
the wait state. In this case, the IEB waits for data for the maximum number of receive bytes + one byte. Then, if data for the maximum number of receive bytes + one byte is not received, a receive timing error is detected and the RXERTME flag is set. In this case, the RXEDLE flag is not set. The RXEDLE flag is set when data for the maximum number of receive bytes + one byte is received. The IEB also waits for data for the maximum number of receive bytes + one byte, when the maximum number of receive bytes have been received but the parity error is not cleared. If data for the maximum number of receive bytes + one byte is not received, the RXERTME flag is set. In this case, the RXEPE flag is not set. The RXEPE flag is set when data for the maximum number of receive bytes + one byte is received. Figure 20.19 shows the operation timing when the reception has not been completed within the maximum number of receive bytes.
HD: MA: SA: CT: DL: Dn: Slave reception HD IERSR RXERTME MA SA CT DL D1 D2 Dn-1 Dn Dn+1 Header Master address field Slave address field Control field Message length field Data field (n = Max. no. of transfer bytes)
Dn + 1 is not received
IERSR RXEDLE
Dn + 1 is received
IERSR RXEPE
Dn + 1 is received
Figure 20.19 Operation Timing when Reception has not been Completed within Maximum Number of Receive Bytes
Rev. 2.00 Sep. 07, 2007 Page 942 of 1312 REJ09B0320-0200
Section 21 CD-ROM Decoder (ROM-DEC)
Section 21 CD-ROM Decoder (ROM-DEC)
The CD-ROM decoder (ROM-DEC) decodes streams of data transferred from the CD-DSP. When the medium is CD-DA*1, the data stream is not input to the CD-ROM decoder because it consists of PCM data. In the case of CD-ROM*2, the stream of data is input and the CD-ROM decoder performs sync code detection and maintenance, descrambling, ECC correction, and EDC checking, and outputs the resulting stream of data. However, since the stream received by the CD-ROM decoder is assumed to consist of data from a CD-ROM transferred via the SSI, the decoder does not bother with the subcodes defined in the CD-DA standard. Notes: 1. Compliant with JIS S 8605 (Red Book) 2. Compliant with JIS X 6281 (Yellow Book)
21.1
Features
* Sync-code detection and maintenance Detects sync codes from the CD-ROM and is capable of providing sync-code maintenance (automatic interpolation of sync codes) when the sync code cannot be detected because of defects such as scratches on the disc. Supported maintenance modes are automatic sync maintenance mode, external sync mode, interpolated sync mode, and interpolated sync plus external sync mode. * Descrambling * ECC support P-parity-based correction, Q-parity-based correction, PQ correction, and QP correction are available. PQ correction and QP correction can be applied repeatedly up to three times. This, however, depends on the speed of the CD. For example, three iterations are possible when the CD-ROM decoder is operating at 60 MHz with a double-speed CD drive. Two buffers are provided due to the need for ECC correction. This allows parallel operation, where ECC correction is performed in one buffer while the data stream is being received in the other. * EDC checking The EDC is checked before and after correction based on the ECC. Furthermore, an operating mode is available in which, if the result of pre-correction EDC checking indicates no errors, ECC correction is not performed regardless of the result of syndrome calculation.
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Section 21 CD-ROM Decoder (ROM-DEC)
* Data buffering control The CD-ROM decoder outputs data to the buffer area in a specific format where the sync code is at the head of the data for each sector. 21.1.1 Formats Supported by ROM-DEC
The CD-ROM decoder of this LSI supports the five formats shown in figure 21.1.
Sync (12 bytes) Sync (12 bytes) Sync (12 bytes) Sync (12 bytes) Sync (12 bytes) Header (4 bytes) Header (4 bytes) Header (4 bytes) Header (4 bytes) Header (4 bytes) Sub-header (8 bytes) Sub-header (8 bytes)
Mode0
All 0
Mode1
Data (2048 bytes)
EDC (4 bytes)
0 (8 bytes)
P-parity (172 bytes)
Q-parity (104 bytes)
Mode2 (not XA) Mode2 Form1 Mode2 Form2
Data (2336 bytes)
Data (2048 bytes)
EDC (4 bytes)
P-parity (172 bytes)
Q-parity (104 bytes) EDC (4 bytes)
Data (2324 bytes)
Figure 21.1 Formats Supported by ROM-DEC
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Section 21 CD-ROM Decoder (ROM-DEC)
21.2
Block Diagrams
Figure 21.2 is a block diagram of the CD-ROM decoder functions of this LSI and the bus bridge for connection to the peripheral bus, that is, of the elements required to implement the CD-ROM decoder function.
SH-2A CPU Peripheral bus controller
Bus bridge (peripheral bus ROM-DEC bus) Stream data Register data Stream data
EDC
Memory (2 buffers for ECC)
EDC
Descrambler
Memory control
Sync code detection/ maintenance
Mode determination ECC control Syndrome calculator
Timing generation Core of CD-ROM decoder
INTC interrupt and DMAC activation control
INTC DMAC
Figure 21.2 ROM-DEC Block Diagram The core of the CD-ROM decoder executes a series of processing required for CD-ROM decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based correction), and EDC checking. The core includes sufficient memory to hold two sectors.
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Stream data output control
Stream data input control
Section 21 CD-ROM Decoder (ROM-DEC)
Input data come from the peripheral bus and output data go out via the peripheral bus along a single line each, but the bus bridge logic sets up branches for the register access port and stream data port. The stream data from the CD-DSP are transferred via the SSI to the stream data input control block. They are then subjected to descrambling, ECC correction, and EDC checking as they pass through the CD-ROM decoder. After these processes, data from one sector are obtained. The data are subsequently transferred to the stream-data buffer via the stream-data output control block. Data can be transferred by either the DMAC or the CPU. Figure 21.3 is a block diagram of the bus-bridge logic. Since the input stream is transferred over the SSI, transfer is relatively slow. On the other hand, data from the output stream can be transferred at high speeds because they are already in the core of the CD-ROM decoder. Since the data for output are buffered in SDRAM or other memory, they must be transferred at high speeds in order to reduce the busy rate of the SDRAM. For this reason, the data for the output stream are read out before the CD-ROM decoder receives an output stream data read request from the peripheral bus. This allows the accumulation of streaming data in the registers of the bus bridge, so that the data are ready for immediate output to the peripheral bus upon a request from the peripheral bus. Accordingly, the reception of a request to read from registers other than the stream-data registers after the stream data has already been read out and stored in the register of the bus bridge is possible. To cope with this, the CD-ROM decoder is provided with separate intermediary registers for the output stream-data register and the other registers.
Input data from the peripheral bus Data for output to the peripheral bus
Buffer control signal for the output stream-data section
Input stream data
Register data (write)
Register data (read)
Output stream data
Output stream-data control signal
Figure 21.3 Schematic Diagram of the Bus Bridge
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Section 21 CD-ROM Decoder (ROM-DEC)
Figure 21.4 is a schematic diagram of the stream-data input control block. The stream-data input controller contains logic that controls the stream of input data and a register that is used to change the control mode of the CD-ROM decoder. The SSI mode used to transfer the stream data may affect the order (through the endian setting) or lead to padding before the data is transferred. To handle the different arrangements of data appropriately, the stream-data input control block includes a register for changing the operating mode and generates signals to control the core of the CD-ROM decoder. The data-pending registers for the input stream consists of two 16-bit registers. The data-pending registers are controlled according to the mode set in the control register. For example, controlling the order in which 16-bit data is supplied to the core of the CD-ROM decoder (sending the second 16-bytes first or vice versa). It is also possible to stop the supply of padding data to the core of the CD-ROM decoder.
Input stream data Register data
Register access controller
Select
16 bits
16 bits
Input stream controller
Figure 21.4 Schematic Diagram of the Stream-Data Input Control Block
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Core of CD-ROM decoder
Section 21 CD-ROM Decoder (ROM-DEC)
Figure 21.5 is a schematic diagram of the stream-data output control block. On recognizing that one sector of CD-ROM data is ready in the core of the CD-ROM decoder, this block ensures that the output stream-data register in the bus bridge section is empty and then starts to acquire the data for output from the core of the CD-ROM decoder
Input stream-data control signal
Output stream data
Core of CD-ROM decoder
Output stream-data protocol controller
Figure 21.5 Schematic Diagram of the Stream-Data Output Control Block This block has functions related to INTC interrupts and DMAC activation control such as suspending and masking of interrupts, turning interrupt flags off after they are read, asserting the activation signal to the DMAC, and negating the activation signal according to the detected amount of data that has been transferred.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3
Register Descriptions
The ROM-DEC has the following registers. Table 21.1 Register Configuration
Name ROM-DEC enable control register Sync code-based synchronization control register Decoding mode control register EDC/ECC check control register Automatic decoding stop control register Decoding option setting control register Abbreviation CROMEN CROMSY0 CROMCTL0 CROMCTL1 CROMCTL3 CROMCTL4 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R Initial Value H'00 H'89 H'82 H'D1 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'E8000000 H'E8000001 H'E8000002 H'E8000003 H'E8000005 H'E8000006 H'E8000007 H'E8000008 H'E8000009 H'E800000B H'E800000C H'E800000D H'E800000E H'E8000014 H'E8000015 H'E8000016 H'E8000018 H'E8000019 H'E800001A H'E800001B Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
HEAD20 to HEAD22 representation control CROMCTL5 register Sync code status register Post-ECC header error status register Post-ECC subheader error status register Header/subheader validity check status register Mode determination and link sector detection status register ECC/EDC error status register Buffer status register Decoding stoppage source status register Buffer overflow status register Pre-ECC correction header: minutes data register Pre-ECC correction header: seconds data register Pre-ECC correction header: frames (1/75 second) data register Pre-ECC correction header: mode data register CROMST0 CROMST1 CROMST3 CROMST4 CROMST5 CROMST6 CBUFST0 CBUFST1 CBUFST2 HEAD00 HEAD01 HEAD02 HEAD03
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Section 21 CD-ROM Decoder (ROM-DEC)
Name Pre-ECC correction subheader: file number (byte 16) data register Pre-ECC correction subheader: channel number (byte 17) data register Pre-ECC correction subheader: sub-mode (byte 18) data register Pre-ECC correction subheader: data type (byte 19) data register Pre-ECC correction subheader: file number (byte 20) data register Pre-ECC correction subheader: channel number (byte 21) data register Pre-ECC correction subheader: sub-mode (byte 22) data register Pre-ECC correction subheader: data type (byte 23) data register Post-ECC correction header: minutes data register Post-ECC correction header: seconds data register Post-ECC correction header: frames (1/75 second) data register Post-ECC correction header: mode data register Post-ECC correction subheader: file number (byte 16) data register Post-ECC correction subheader: channel number (byte 17) data register Post-ECC correction subheader: sub-mode (byte 18) data register Post-ECC correction subheader: data type (byte 19) data register Post-ECC correction subheader: file number (byte 20) data register
Abbreviation SHEAD00 SHEAD01 SHEAD02 SHEAD03 SHEAD04 SHEAD05 SHEAD06 SHEAD07 HEAD20 HEAD21 HEAD22 HEAD23 SHEAD20 SHEAD21 SHEAD22 SHEAD23 SHEAD24
R/W R R R R R R R R R R R R R R R R R
Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
Address H'E800001C H'E800001D H'E800001E H'E800001F H'E8000020 H'E8000021 H'E8000022 H'E8000023 H'E8000024 H'E8000025 H'E8000026 H'E8000027 H'E8000028 H'E8000029 H'E800002A H'E800002B H'E800002C
Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
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Section 21 CD-ROM Decoder (ROM-DEC)
Name Post-ECC correction subheader: channel number (byte 21) data register Post-ECC correction subheader: sub-mode (byte 22) data register Post-ECC correction subheader: data type (byte 23) data register Automatic buffering setting control register Automatic buffering start sector setting: minutes control register Automatic buffering start sector setting: seconds control register Automatic buffering start sector setting: frames control register ISY interrupt source mask control register CD-ROM decoder reset control register CD-ROM decoder reset status register SSI data control register Interrupt flag register Interrupt source mask control register Buffer control register CD-ROM decoder stream data input register CD-ROM decoder stream data input register CD-ROM decoder stream data input register CD-ROM decoder stream data input register CD-ROM decoder stream data output register CD-ROM decoder stream data output register
Abbreviation SHEAD25 SHEAD26 SHEAD27 CBUFCTL0 CBUFCTL1 CBUFCTL2 CBUFCTL3 CROMST0M ROMDECRST RSTSTAT SSI INTHOLD INHINT RINGBUFCTL STRMDIN0 STRMDIN1 STRMDIN2 STRMDIN3 STRMDOUT0 STRMDOUT1
R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value H'00 H'00 H'00 H'04 H'00 H'00 H'00 H'00 H'00 H'00 H'18 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
Address H'E800002D H'E800002E H'E800002F H'E8000040 H'E8000041 H'E8000042 H'E8000043 H'E8000045 H'E8000100 H'E8000101 H'E8000102 H'E8000108 H'E8000109 H'E800010C H'E8000200 H'E8000201 H'E8000202 H'E8000203 H'E8000204 H'E8000205
Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Read: 16 Write: 32
16
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.1
ROM-DEC Enable Control Register (CROMEN)
CROMEN enables subcode processing and CD-ROM decoding, and stops CD-ROM decoding forcibly.
Bit: 7 6 5 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W
SUBC_ CROM_ CROM_ EN EN STP
Initial value: 0 R/W: R/W
0 R/W
0 R/W
Bit 7
Bit Name SUBC_EN
Initial Value 0
R/W R/W
Description Subcode Processing Enable This bit should be set and cleared simultaneously with CROM_EN. It is automatically cleared when decoding is automatically stopped due to an abnormal condition or when CROM_STP = 1
6
CROM_EN
0
R/W
CD-ROM Decoding Enable When this bit is set to 1, CD-ROM decoding starts after detection of a valid sync code. When the bit is cleared to 0, decoding stops on completion of the processing for the sector currently being decoded. This bit is automatically cleared when the automatic decode-stopping function woks or when CROM_STP = 1.
5
CROM_STP 0
R/W
Forcible Stop of CD-ROM Decoding When this bit is set to 1, CD-ROM decoding is stopped immediately and the SUBC_EN and CROM_EN bits are automatically reset to 0. Before decoding can resume, this bit must be cleared to 0.
4 to 0
All 0
R/W
Reserved These bits are always read as 0.The write value should always be 0.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.2
Sync Code-Based Synchronization Control Register (CROMSY0)
CROMSY0 selects the sync code maintenance function.
Bit: 7
SY_ AUT
6
SY_ IEN
5
SY_ DEN
4 -- 0 R/W
3 -- 1 R/W
2 -- 0 R/W
1 -- 0 R/W
0 -- 1 R/W
Initial value: 1 R/W: R/W
0 R/W
0 R/W
Bit 7
Bit Name SY_AUT
Initial Value 1
R/W R/W
Description Automatic CD-ROM Sync Code Maintenance Mode When this bit is set to 1, automatic sync maintenance (insertion of sync codes) is applied to obtain the CDROM sync codes. While this bit is set, the settings of the SY_IEN and SY_DEN bits are invalid.
6
SY_IEN
0
R/W
Enables the internal sync signal that is produced by the counter in the CD-ROM decoder. When this bit is set while SY_AUT = 0, synchronization of the CD-ROM data is in interpolated mode, i.e. driven by the internal counter.
5
SY_DEN
0
R/W
Selects constant monitoring for the sync code in the input data and bases synchronization solely on detection of the code, regardless of the value of the internal counter. This bit is valid when SY_AUT = 0. Reserved This bit is always read as 0. The write value should always be 0.
4
0
R/W
3
1
R/W
Reserved This bit is always read as 1. The write value should always be 1.
2, 1
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
0
1
R/W
Reserved This bit is always read as 1. The write value should always be 1.
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Section 21 CD-ROM Decoder (ROM-DEC)
Table 21.2 Register Settings for Sync Code Maintenance Modes
SY_AUT 1 0 0 0 0 SY_IEN 0 1 1 0 SY_DEN 1 0 1 0 Operating Mode Automatic sync maintenance mode External sync mode Interpolated sync mode Interpolated sync plus external sync mode Setting prohibited
21.3.3
Decoding Mode Control Register (CROMCTL0)
CROMCTL0 enables/disables the various functions, selects criteria for mode or form determination, and specifies the sector type. The setting of this register becomes valid at the sector-to-sector transition
Bit: 7
MD_ DESC
6 -- 0 R/W
5
4
3
2
1
MD_SEC[2:0]
0
MD_ MD_ MD_ AUTO AUTOS1 AUTOS2
Initial value: 1 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
Bit 7
Bit Name MD_DESC
Initial Value 1
R/W R/W
Description Descrambling Function ON/OFF 0: Descrambling function is off 1: Descrambling function is on
6
0
R/W
Reserved This bit is always read as 0. The write value should always be 0.
5
MD_AUTO
0
R/W
Automatic Mode/Form Detection ON/OFF 0: Off 1: On Detectable formats are Mode 0, Mode 1, Mode 2 (nonXA), Mode 2 Form 1, and Mode 2 Form 2. If the mode and form cannot be detected, the sector is taken to be in the same mode and form as the previous sector. If the mode and form of the first sector after decoding starts is undetectable, the setting of the MD_SEC[2:0] bits is used as the initial value.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 4
Bit Name MD_AUTOS1
Initial Value 0
R/W R/W
Description Criteria for Mode Determination when MD_AUTO = 1 0: Mode determination is done when the sync code is detected 1: Mode determination is always done This bit is only valid when MD_AUTO = 1. If the mode cannot be determined, the mode of the previous sector is used. When this bit is cleared to 0, mode determination is only done when the sync code is detected for the sector.
3
MD_AUTOS2
0
R/W
Criteria for Mode 2 Form Determination when MD_AUTO = 1 0: The sector is assumed to be non-XA if the two form code bytes in the subheader do not match 1: No determination of XA or non-XA for the sector. The first form byte is regarded as valid. However, the two form bytes are compared, and the result is reflected in a status bit. This bit is only valid when MD_AUTO = 1.
2 to 0
MD_SEC[2:0]
010
R/W
Sector Type 000: Setting prohibited 001: Mode 0 010: Mode 1 011: Long (Mode 0, Mode 1, or Mode 2 with no EDC/ECC data) 100: Setting prohibited 101: Mode 2 Form 1 110: Mode 2 Form 2 111: Mode 2 with automatic form detection If the form cannot be determined when set to B'111, it is processed as Mode 2 not XA.
Note: The setting of this register is reapplied on each sector-to-sector transition.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.4
EDC/ECC Check Control Register (CROMCTL1)
CROMCTL1 controls EDC/ECC checking. The setting of this register becomes valid at the sectorto-sector transition
Bit: 7 6 5 4 3 -- 0 R/W 2 -- 0 R/W 1 0
M2F2 MD_DEC[2:0] EDC Initial value: 1 1 0 1 R/W: R/W R/W R/W R/W
MD_PQREP [1:0] 0 1 R/W R/W
Bit 7
Bit Name M2F2EDC
Initial Value 1
R/W R/W
Description For Mode 2 Form 2, disables the EDC function for sectors where all bits of the EDC are 0. When this bit set to 1 and all bits of the EDC for a Mode 2 Form 2 sector are 0, an IERR interrupt is not generated even if the result of EDC checking is 'fail'.
6 to 4
MD_DEC [2:0]
101
R/W
EDC/ECC Checking Mode Select 000: No checking 001: EDC only 010: Q correction + EDC 011: P correction + EDC 100: QP correction + EDC 101: PQ correction + EDC 110: Setting prohibited 111: Setting prohibited
3, 2
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
MD_PQREP [1:0]
01
R/W
Number of correction iterations when PQ- or QPcorrection is specified by MD_DEC[2:0]. 00: Setting prohibited 01: One iteration 10: Two iterations 11: Three iterations
Note: The setting of this register is reapplied on each sector-to-sector transition.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.5
Automatic Decoding Stop Control Register (CROMCTL3)
CROMCTL3 is used to select abnormal conditions on which decoding will be automatically stopped. When decoding is stopped in response to any of the selected conditions, an IBUF interrupt is generated and the condition is indicated in the CBUFST1 register. The setting of this register becomes valid at the sector-to-sector transition
Bit: 7
STP_ ECC
6
STP_ EDC
5 -- 0 R/W
4
STP_ MD
3
STP_ MIN
2 -- 0 R/W
1 -- 0 R/W
0 -- 0 R/W
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5
Bit Name STP_ECC STP_EDC
Initial Value 0 0 0
R/W R/W R/W R/W
Description When this bit is set to 1, decoding is stopped if an error is found to be not correctable by ECC correction. When this bit is set to 1, decoding is stopped if postcorrection EDC checking indicates an error. Reserved This bit is always read as 0. The write value should always be 0.
4
STP_MD
0
R/W
When this bit is set to 1, decoding is stopped if the sector has a mode or form setting that does not match those of the immediately preceding sector. When this bit is set to 1, decoding is stopped if a nonsequential minutes, seconds, or frames (1/75 second) value is encountered. Reserved These bits are always read as 0. The write value should always be 0.
3
STP_MIN
0
R/W
2 to 0
All 0
R/W
Note: The setting of this register is reapplied on each sector-to-sector transition.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.6
Decoding Option Setting Control Register (CROMCTL4)
CROMCTL4 enables/disables buffering control at link block detection, specifies the information indicated by the status register, and controls the ECC correction mode. The setting of this register becomes valid at the sector-to-sector transition
Bit: 7 6 5 4 ER0 SEL 0 R/W 3 NO_ ECC 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W
LINK LINK2 -- OFF Initial value: 0 0 0 R/W: R/W R/W R/W
Bit 7
Bit Name LINKOFF
Initial Value 0
R/W R/W
Description Buffering Control at Link Block Detection 0: On 1: Off When this bit is set to 1, buffering control is not performed when a link block is detected. The link block is processed as normal sectors. However, link-block detection processing does proceed, and the results are reflected in the values of bits 3 to 0 in the CROMST5 register.
6
LINK2
0
R/W
Link Block Detection Condition 0: The block is regarded as a link block when either run-out 1 or 2 and both run-in 3 and 4 have been detected. 1: The block is regarded as a link block when two out of run-out 1 and 2 and "link" have been detected. When this bit is set to 1, buffering control for link blocks is disabled (link blocks are processed as normal sectors). The condition for setting of the LINK_ON bit in CROMST5 is decoding of the link sector.
5
0
R/W
Reserved This bit is always read as 0. The write value should always be 0.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 4
Bit Name ER0SEL
Initial Value 0
R/W R/W
Description CD-ROM Data-Related Status Register Setting Condition 0: Information is on the sector being decoded. 1: Information is on the latest sector that has been buffered. This condition affects the information given by bits 5 to 0 in the CROMST0 register, bits 7 to 1 in the CROMST4 and CROMST5 registers, and HEAD00 to HEAD02.
3
NO_ECC
0
R/W
ECC correction mode when the result of the EDC check before ECC correction was 'pass' When this bit is set to 1, ECC correction is not performed if the result of pre-correction EDC checking is a 'pass', regardless of the results of syndrome calculation.
2 to 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
Note: The setting of this register is reapplied on each sector-to-sector transition.
21.3.7
HEAD20 to HEAD22 Representation Control Register (CROMCTL5)
CROMCTL5 specifies the representation mode for HEAD20 to HEAD22.
Bit: 7 -- Initial value: 0 R/W: R/W 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0
MSF_ LBA_SEL
0 R/W
Bit 7 to 1
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
0
MSF_LBA_ SEL
0
R/W
HEAD20 to HEAD22 Representation Mode 0: BCD M, F, and S values in the header as is 1: Total sector number in HEX
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.8
Sync Code Status Register (CROMST0)
CROMST0 indicates various status information in sync code maintenance modes.
Bit: 7
--
6
-- 0 R
5
ST_ SYIL
4
3
2
ST_ BLKL
1
ST_ SECS
0
ST_ SECL
ST_ ST_ SYNO BLKS
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0 and cannot be modified.
5
ST_SYIL
0
R
Indicates that a sync code was detected at a position where the value in the word counter (used to measure intervals between sync codes) was not correct, but the sync code was ignored and not taken into account in synchronization. This bit is only valid in automatic sync maintenance mode and interpolated sync mode.
4
ST_SYNO
0
R
Indicates that a sync code has not been detected despite the word counter having reached the final value, and synchronization has been continued with the aid of an interpolated sync code. This bit is only valid in automatic sync maintenance mode and interpolated sync mode.
3
ST_BLKS
0
R
Indicates that a sync code was detected at a position where the value in the word counter was not correct, and the sync code was used in synchronization. This bit is only valid in automatic sync maintenance mode and external sync mode.
2
ST_BLKL
0
R
Indicates that a sync code has not been detected despite the word counter having reached the final value, and the period of the sector has been prolonged. This bit is only valid in external sync mode.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 1
Bit Name ST_SECS
Initial Value 0
R/W R
Description Indicates that a sector has been processed as a short sector with the aid of interpolated sync codes. If this bit is set to 1, stop decoding immediately and retry the procedure starting from the sector prior to the currently being decoded sector. Indicates that a sector has been processed as a long sector with the aid of interpolated sync codes. If this bit is set to 1, stop decoding immediately and retry the procedure starting from two sectors prior to the sector currently being decoded.
0
ST_SECL
0
R
21.3.9
Post-ECC Header Error Status Register (CROMST1)
CROMST1 indicates error status in the post-ECC header.
Bit: 7 -- Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3
ER2_ HEAD0
2
ER2_ HEAD1
1
ER2_ HEAD2
0
ER2_ HEAD3
0 R
0 R
0 R
0 R
Bit 7 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0 and cannot be modified.
3 2 1 0
ER2_HEAD0 ER2_HEAD1 ER2_HEAD2 ER2_HEAD3
0 0 0 0
R R R R
Indicates an error status in the minutes field of the header after ECC correction. Indicates an error status in the seconds field of the header after ECC correction. Indicates an error status in the frames (1/75 second) field of the header after ECC correction. Indicates an error status in the mode field of the header after ECC correction.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.10 Post-ECC Subheader Error Status Register (CROMST3) CROMST3 indicates error status in the post-ECC subheader.
Bit: 7 6 5 4 3 2 1
ER2_ HEAD6
0
ER2_ HEAD7
ER2_ ER2_ ER2_ ER2_ ER2_ ER2_ SHEAD0 SHEAD1 SHEAD2 SHEAD3 SHEAD4 HEAD5
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7
Bit Name ER2_SHEAD0
Initial Value 0
R/W R
Description Indicates that the subheader (file number) still has an error after ECC correction. Indicates the error of the SHEAD20 register. Indicates that the subheader (channel number) still has an error after ECC correction. Indicates the error of the SHEAD21 register. Indicates that the subheader (sub-mode) still has an error after ECC correction. Indicates the error of the SHEAD22 register. Indicates that the subheader (data type) still has an error after ECC correction. Indicates the error of the SHEAD23 register. Indicates that the subheader (file number) still has an error after ECC correction. Indicates the error of the SHEAD24 register. Indicates that the subheader (channel number) still has an error after ECC correction. Indicates the error of the SHEAD25 register. Indicates that the subheader (sub-mode) still has an error after ECC correction. Indicates the error of the SHEAD26 register. Indicates that the subheader (data type) still has an error after ECC correction. Indicates the error of the SHEAD27 register.
6
ER2_SHEAD1
0
R
5
ER2_SHEAD2
0
R
4
ER2_SHEAD3
0
R
3
ER2_SHEAD4
0
R
2
ER2_SHEAD5
0
R
1
ER2_SHEAD6
0
R
0
ER2_SHEAD7
0
R
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.11 Header/Subheader Validity Check Status Register (CROMST4) CROMST4 indicates errors relating to the automatic mode determination or form determination for Mode 2.
Bit: 7
NG_MD
6
5
4
3
2
1
0
NG_ NG_ NG_ NG_ NG_ NG_ NG_ MDCMP1 MDCMP2 MDCMP3 MDCMP4 MDDEF MDTIM1 MDTIM2
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7 6
Bit Name NG_MD NG_MDCMP1
Initial Value 0 0
R/W R R
Description Indicates that the sector mode could not be determined according to the automatic mode determination criteria. Indicates a mismatch between the file number bytes (bytes 16 and 20) during the form determination for Mode 2. Indicates a mismatch between the channel number bytes (bytes 17 and 21) during the form determination for Mode 2. Indicates a mismatch between the sub-mode bytes (bytes 18 and 22) during the form determination for Mode 2. Indicates a mismatch between the data-type bytes (bytes 19 and 23) during the form determination for Mode 2. Indicates that the mode and form differ from those of the previous sector. Indicates that the minutes, seconds, or frames (1/75 second) value is out of sequence. In the continuity check for the next and subsequent sectors, the updated values will be used.
5
NG_MDCMP2
0
R
4
NG_MDCMP3
0
R
3
NG_MDCMP4
0
R
2 1
NG_MDDEF NG_MDTIM1
0 0
R R
0
NG_MDTIM2
0
R
Indicates that the minutes, seconds, or frames (1/75 second) value was not a BCD value. Specifically, this bit means that any half-byte was beyond the range for BCD (i.e. was A to F), HEAD01 was greater than H'59, or HEAD02 was greater than H'74. In the continuity check for the next and subsequent sectors, interpolated values will be used.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5) CROMST5 indicates the result of automatic mode determination and link block detection.
Bit: 7 6 5 4
ST_ MDX
3
2
1
0
ST_AMD[2:0] Initial value: R/W: 0 R 0 R 0 R
LINK_ LINK_ LINK_ LINK_ ON DET SDET OUT1
0 R
0 R
0 R
0 R
0 R
Bit 7 to 5
Bit Name ST_AMD [2:0]
Initial Value 000
R/W R
Description Result of Automatic Mode Determination These bits indicate the result of mode determination when the automatic mode determination function is used. 000: Automatic mode determination function is not used 001: Mode 0 010: Mode 1 011: 100: Mode 2 not XA 101: Mode 2 Form 1 110: Mode 2 Form 2 111:
4
ST_MDX
0
R
Indicates that, when the mode has been manually set rather than automatically determined, the mode setting disagrees with the mode as recognized by the logic. In this case, the manually set value takes priority. This bit is set to 1 when a link block was recognized in link block determination. For the criteria for link block determination, refer to the LINK2 bit in the CROMCTL4 register. When this bit is set to 1, buffering control is performed according to the setting of the CBUF_LINK bit in the CBUFCTL0 register.
3
LINK_ON
0
R
2
LINK_DET
0
R
Indicates that a link block (run-out 1 to run-in 4) was detected. Since detection is based on the data before ECC correction, LINK_DET may also be set to 1 if data erroneously happens to contain the same code as a link block.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 1 0
Bit Name LINK_SDET LINK_OUT1
Initial Value 0 0
R/W R R
Description Indicates that a link block was detected within seven sectors after the start of decoding. Indicates that the sector after ECC correction has been identified as a run-out 1 sector. This bit is only valid when an IERR interrupt is not generated (i.e. when ECC correction was successful).
21.3.13 ECC/EDC Error Status Register (CROMST6) CROMST6 indicates ECC processing error or EDC check error before/after ECC correction.
Bit: 7
ST_ ERR
6 -- 0 R
5
4
3
ST_ ECCP
2
ST_ ECCQ
1
ST_ EDC1
0
ST_ EDC2
ST_ ST_ ECCABT ECCNG
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 7 6 5
Bit Name ST_ERR ST_ECCABT
Initial Value 0 0 0
R/W R R R
Description Indicates that the decoded block after ECC correction contains any error (even in a single byte). Reserved This bit is always read as 0 and cannot be modified. Indicates that ECC processing was discontinued. This bit is set to 1 when a transition from sector to sector occurs while ECC correction is in progress. This does not indicate a problem for ECC correction if the BUF_NG bit in the CBUFST2 register is 0 at the same time. Whether or not this is so depends on the timing of the sector transition.
4 3
ST_ECCNG ST_ECCP
0 0
R R
Indicates that error correction was not possible. This bit is also set to 1 on detection of a short sector. Indicates that P-parity errors were not corrected in ECC correction. This bit is only valid when synchronization is normal (the sector is neither short nor long). This bit is set to 1 when the result of syndrome calculation for P parity is non-0.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 2
Bit Name ST_ECCQ
Initial Value 0
R/W R
Description Indicates that Q-parity errors were not corrected in ECC correction. This bit is only valid when synchronization is normal (the sector is neither short nor long). This bit is set to 1 when the result of syndrome calculation for Q parity is non-0.
1
ST_EDC1
0
R
Indicates that the result of the EDC check before ECC correction was 'fail'. This bit is also set to 1 if a short sector is encountered while EDC is enabled.
0
ST_EDC2
0
R
Indicates that the result of the EDC check after ECC correction was 'fail'.
21.3.14 Buffer Status Register (CBUFST0) CBUFST0 indicates that the system is searching for the first sector to be buffered, or that buffering is in progress.
Bit: 7
BUF_ REF
6
BUF_ ACT
5 -- 0 R
4 -- 0 R
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
Initial value: R/W:
0 R
0 R
Bit 7
Bit Name BUF_REF
Initial Value 0
R/W R
Description Indicates that the search for the first sector to be buffered is in progress. This bit is only valid when the automatic buffering function is used (CBUF_AUT = 1).
6 5 to 0
BUF_ACT
0 All 0
R R
Indicates that buffering is in progress. Reserved These bits are always read as 0 and cannot be modified.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.15 Decoding Stoppage Source Status Register (CBUFST1) CBUFST1 indicates that decoding/buffering has been stopped due to some errors. A bit in this register can only be set when the corresponding bit in the CROMCTL3 register is set to 1.
Bit: 7
BUF_ ECC
6
BUF_ EDC
5 -- 0 R
4
BUF_ MD
3
BUF_ MIN
2 -- 0 R
1 -- 0 R
0 -- 0 R
Initial value: R/W:
0 R
0 R
0 R
0 R
Bit 7
Bit Name BUF_ECC
Initial Value 0
R/W R
Description Indicates that decoding and buffering have been stopped because of an error that is not correctable by using the ECC. Indicates that decoding and buffering have been stopped because the post-correction EDC check indicated an error. Reserved This bit is always read as 0 and cannot be modified. Indicates that decoding and buffering have been stopped because the current sector is in a mode or form differing from that of the previous sectors. Indicates that decoding and buffering have been stopped because a non-sequential minutes, seconds, or frames (1/75 second) value has been encountered. Reserved This bit is always read as 0 and cannot be modified.
6
BUF_EDC
0
R
5 4
BUF_MD
0 0
R R
3
BUF_MIN
0
R
2 to 0
All 0
R
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.16 Buffer Overflow Status Register (CBUFST2) CBUFST2 indicates that a sector-to-sector transition occurred before data transfer to the buffer is completed.
Bit: 7 BUF_ NG Initial value: R/W: 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 7
Bit Name BUF_NG
Initial Value 0
R/W R
Description Indicates that a sector-to-sector transition has occurred before the data transfer to the buffer is completed. This bit is set to 1 when the data of a third sector are input while data for the output stream from the CD-ROM decoder remains unread. No interrupt is generated. Once this bit has been set, its value will not recover unless it is reset by the LOGICRST bit in the ROMDECRST register. Reserved These bits are always read as 0 and cannot be modified.
6 to 0
All 0
R
21.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00) HEAD00 indicates the minutes value in the header before ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD00[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD00[7:0]
Initial Value All 0
R/W R
Description Minutes value in the header before ECC correction
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01) HEAD01 indicates the seconds value in the header before ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD01[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD01[7:0]
Initial Value All 0
R/W R
Description Seconds value in the header before ECC correction
21.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02) HEAD02 indicates the frames value (1 frame = 1/75 second) in the header before ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD02[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD02[7:0]
Initial Value All 0
R/W R
Description Frames value in the header before ECC correction
21.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03) HEAD03 indicates the mode value in the header before ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD03[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD03[7:0]
Initial Value All 0
R/W R
Description Mode value in the header before ECC correction
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00) SHEAD00 indicates the file number value in the subheader before ECC correction (byte 16).
Bit: 7 6 5 4 3 2 1 0
SHEAD00[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD00[7:0]
Initial Value All 0
R/W R
Description File number value in the subheader before ECC correction (byte 16) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
21.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01) SHEAD01 indicates the channel number value in the subheader before ECC correction (byte 17).
Bit: 7 6 5 4 3 2 1 0
SHEAD01[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD01[7:0]
Initial Value All 0
R/W R
Description Channel number value in the subheader before ECC correction (byte 17) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02) SHEAD02 indicates the sub-mode value in the subheader before ECC correction (byte 18).
Bit: 7 6 5 4 3 2 1 0
SHEAD02[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD02[7:0]
Initial Value All 0
R/W R
Description Sub-mode value in the subheader before ECC correction (byte 18) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
21.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03) SHEAD03 indicates the data type value in the subheader before ECC correction (byte 19).
Bit: 7 6 5 4 3 2 1 0
SHEAD03[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD03[7:0]
Initial Value All 0
R/W R
Description Data type value in the subheader before ECC correction (byte 19) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.25 Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04) SHEAD04 indicates the file number value in the subheader before ECC correction (byte 20).
Bit: 7 6 5 4 3 2 1 0
SHEAD04[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD04[7:0]
Initial Value All 0
R/W R
Description File number value in the subheader before ECC correction (byte 20) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
21.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05) SHEAD05 indicates the channel number value in the subheader before ECC correction (byte 21).
Bit: 7 6 5 4 3 2 1 0
SHEAD05[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD05[7:0]
Initial Value All 0
R/W R
Description Channel number value in the subheader before ECC correction (byte 21) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06) SHEAD06 indicates the sub-mode value in the subheader before ECC correction (byte 22).
Bit: 7 6 5 4 3 2 1 0
SHEAD06[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD06[7:0]
Initial Value All 0
R/W R
Description Sub-mode value in the subheader before ECC correction (byte 22) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
21.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07) SHEAD07 indicates the data type value in the subheader before ECC correction (byte 23).
Bit: 7 6 5 4 3 2 1 0
SHEAD07[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD07[7:0]
Initial Value All 0
R/W R
Description Data type value in the subheader before ECC correction (byte 23) For sectors not in Mode 2, this register contains the byte of data at the corresponding position.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20) HEAD20 indicates the minutes value in the header after ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD20[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD20[7:0]
Initial Value All 0
R/W R
Description Minutes value in the header after ECC correction When MSF_LBA_SEL = 1, this register indicates the first byte of the total number of sectors calculated from M, S, and F.
21.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21) HEAD21 indicates the seconds value in the header after ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD21[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD21[7:0]
Initial Value All 0
R/W R
Description Seconds value in the header after ECC correction When MSF_LBA_SEL = 1, this register indicates the second byte of the total number of sectors calculated from M, S, and F.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.31 Post-ECC Correction Header: Frames (1/75 Seconds) Data Register (HEAD22) HEAD22 indicates the frames value (1 frame = 1/75 seconds) in the header after ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD22[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD22[7:0]
Initial Value All 0
R/W R
Description Frames value in the header after ECC correction When MSF_LBA_SEL = 1, this register indicates the third byte of the total number of sectors calculated from M, S, and F.
21.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23) HEAD23 indicates the mode value in the header after ECC correction.
Bit: 7 6 5 4 3 2 1 0
HEAD23[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name HEAD23[7:0]
Initial Value All 0
R/W R
Description Mode value in the header after ECC correction
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20) SHEAD20 indicates the file number value in the subheader after ECC correction (byte 16).
Bit: 7 6 5 4 3 2 1 0
SHEAD20[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD20[7:0]
Initial Value All 0
R/W R
Description File number value in the subheader after ECC correction (byte 16)
21.3.34 Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21) SHEAD21 indicates the channel number value in the subheader after ECC correction (byte 17).
Bit: 7 6 5 4 3 2 1 0
SHEAD21[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD21[7:0]
Initial Value All 0
R/W R
Description Channel number value in the subheader after ECC correction (byte 17)
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.35 Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22) SHEAD22 indicates the sub-mode value in the subheader after ECC correction (byte 18).
Bit: 7 6 5 4 3 2 1 0
SHEAD22[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD22[7:0]
Initial Value All 0
R/W R
Description Sub-mode value in the subheader after ECC correction (byte 18)
21.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23) SHEAD23 indicates the data type value in the subheader after ECC correction (byte 19).
Bit: 7 6 5 4 3 2 1 0
SHEAD23[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD23[7:0]
Initial Value All 0
R/W R
Description Data type value in the subheader after ECC correction (byte 19)
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24) SHEAD24 indicates the file number value in the subheader after ECC correction (byte 20).
Bit: 7 6 5 4 3 2 1 0
SHEAD24[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD24[7:0]
Initial Value All 0
R/W R
Description File number value in the subheader after ECC correction (byte 20)
21.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25) SHEAD25 indicates the channel number value in the subheader after ECC correction (byte 21).
Bit: 7 6 5 4 3 2 1 0
SHEAD25[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD25[7:0]
Initial Value All 0
R/W R
Description Channel number value in the subheader after ECC correction (byte 21)
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26) SHEAD26 indicates the sub-mode value in the subheader after ECC correction (byte 22).
Bit: 7 6 5 4 3 2 1 0
SHEAD26[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SHEAD26[7:0]
Initial Value All 0
R/W R
Description Sub-mode value in the subheader after ECC correction (byte 22)
21.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27) SHEAD27 indicates the data type value in the subheader after ECC correction (byte 23).
Bit: 7 6 5 4 3 2 1 0
SHEAD27[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name
Initial Value
R/W R
Description Data type value in the subheader after ECC correction (byte 23)
SHEAD27[7:0] All 0
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.41 Automatic Buffering Setting Control Register (CBUFCTL0)
Bit: 7
CBUF_ AUT
6
CBUF_ EN
5
CBUF_ LINK
4
3
2
CBUF_ TS
1
CBUF_ Q
0 -- 0 R/W
CBUF_MD[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
Bit 7
Bit Name CBUF_AUT
Initial Value 0
R/W R/W
Description Automatic Buffering Function ON/OFF Control When this bit is to be set or cleared while CROM_EN = 1, CBUF_EN should also be set or cleared simultaneously. Otherwise, the validity of the status indications in CBUFST0, CBUFST1 and CBUFST2 cannot be guaranteed. 0: Automatic buffering is OFF 1: Automatic buffering is ON
6
CBUF_EN
0
R/W
Buffering to Buffer RAM Control This bit turns buffering in both automatic and manual buffering modes on and off. In manual buffering mode, set this bit after generation of the ISEC interrupt. This bit is automatically reset when automatic buffering stops. 0: Buffering is OFF 1: Buffering is ON
5
CBUF_LINK
0
R/W
Buffering Control on Link Block Detection 0: Allocates area for seven sectors 1: Data are buffered, skipping the link block
4, 3
CBUF_MD [1:0]
00
R/W
Start-sector detection mode when the automatic buffering function is in use 00: The header values for the previous and current sectors must be in sequence. 01: The header value detected in the current sector must be in sequence with the interpolated value. 10: A current sector with any header value is OK. 11: Start-sector detection is based on the interpolated value even if the current sector is not detected.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 2
Bit Name CBUF_TS
Initial Value 1
R/W R/W
Description CBUFCTL1 to CBUFCTL3 Setting Mode 0: Minutes, seconds, and frames values in BCD 1: Total number of sectors (in hexadecimal)
1
CBUF_Q
0
R/W
Q-channel code buffering data specification in the case of a CRC error in the Q-channel code 0: The values for the last sector for which the CRC returned a correct result are buffered. 1: The erroneous data is buffered as is. Since subcodes are not input with this LSI, always set this bit to 1.
0
0
R/W
Reserved This bit is always read as 0.The write value should always be 0.
21.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1) CBUFCTL1 indicates the minutes value in the header for the first sector to be buffered.
Bit: 7 6 5 4 3 2 1 0
BS_MIN[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name BS_MIN[7:0]
Initial Value All 0
R/W R/W
Description Setting of the minutes value in the header for the first sector to be buffered
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2) CBUFCTL2 indicates the seconds value in the header for the first sector to be buffered.
Bit: 7 6 5 4 3 2 1 0
BS_SEC[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name BS_SEC[7:0]
Initial Value All 0
R/W R/W
Description Setting of the seconds value in the header for the first sector to be buffered
21.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3) CBUFCTL3 indicates the frames (1 frame = 1/75 second) value in the header for the first sector to be buffered.
Bit: 7 6 5 4 3 2 1 0
BS_FRM[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name BS_FRM[7:0]
Initial Value All 0
R/W R/W
Description Setting of the frames (1/75 second) value in the header for the first sector to be buffered
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.45 ISY Interrupt Source Mask Control Register (CROMST0M) CROMST0M masks the ISY interrupt sources specified by the bits in the sync code status register (CROMST0).
Bit: 7 -- Initial value: 0 R/W: R/W 6 -- 0 R/W 5
ST_ SYILM
4
3
2
1
0
ST_ ST_ SYNOM BLKSM
ST_ ST_ ST_ BLKLM SECSM SECLM
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7, 6
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0.The write value should always be 0.
5 4 3 2 1 0
ST_SYILM ST_SYNOM ST_BLKSM ST_BLKLM ST_SECSM ST_SECLM
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
ISY interrupt ST_SYIL (bit 5 in the CROMST0 register) source mask ISY interrupt ST_SYNO (bit 4 in the CROMST0 register) source mask ISY interrupt ST_BLKS (bit 3 in the CROMST0 register) source mask ISY interrupt ST_BLKL (bit 2 in the CROMST0 register) source mask ISY interrupt ST_SECS (bit 1 in the CROMST0 register) source mask ISY interrupt ST_SECL (bit 0 in the CROMST0 register) source mask
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST) ROMDECRST resets the random logic of the CD-ROM decoder, clears the RAM in the CD-ROM decoder, and masks reset of the CD-ROM decoder.
Bit: 7
LOGI CRST
6
RAM RST
5
INHBUS CAN
4 -- 0 R/W
3 -- 0 R/W
2 -- 0 R/W
1 -- 0 R/W
0 -- 0 R/W
Initial value: 0 R/W: R/W
0 R/W
0 R/W
Bit 7 6
Bit Name LOGICRST RAMRST
Initial Value 0 0
R/W R/W R/W
Description CD-ROM Decoder Random Logic Reset Signal A reset signal is output while this bit is set to 1. CD-ROM Decoder RAM Clearing Signal After setting this bit to 1, refer to the RAMCLRST bit in the RSTSTAT register to confirm that RAM clearing is complete.
5
INHBUSCAN
0
R/W
If this bit is set while the bus-canceling signal is asserted, the reset signal for the CD-ROM decoder is masked. Reserved These bits are always read as 0.The write value should always be 0.
4 to 0
All 0
R/W
Note: Before setting LOGICRST to 1, make sure that both the RAMRST and INHBUSCAN bits are clear and then make the setting by writing B'10000000 to this register.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) RSTSTAT indicates that the RAM in the CD-ROM decoder has been cleared.
Bit: 7
RAM CLRST
6 -- 0 R
5 -- 0 R
4 -- 0 R
3 -- 0 R
2 -- 0 R
1 -- 0 R
0 -- 0 R
Initial value: R/W:
0 R
Bit 7
Bit Name RAMCLRST
Initial Value 0
R/W R
Description This bit is set to 1 on the completion of RAM clearing triggered by setting RAMRST to 1. It is cleared by writing a 0 to RAMRST. Reserved These bits are always read as 0 and cannot be modified.
6 to 0
All 0
R
21.3.48 SSI Data Control Register (SSI) SSI provides various settings related to the data stream. For the operation corresponding to the setting of this register, see section 21.4.1, Endian Conversion for Data in the Input Stream.
Bit: 7 6 5 4 3 2 1 -- 0 R/W 0 -- 0 R/W
BYTEND BITEND
BUFEND0[1:0] BUFEND1[1:0]
Initial value: 0 R/W: R/W
0 R/W
0 R/W
1 R/W
1 R/W
0 R/W
Bit 7
Bit Name BYTEND
Initial Value 0
R/W R/W
Description Specifies the endian of input data from the SSI module. When this bit is set to 1, the bytes in STRMDIN0 and STRMDIN1 are swapped, as are those in STRMDIN2 and STRMDIN3.
6
BITEND
0
R/W
Specifies treatment of the bit order of the input data from the SSI module. When this bit is set to 1, the bits within each byte are rearranged to place them in reverse order, bit 0 bit 7 to bit 7 bit 0.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 5, 4
Bit Name BUFEND0 [1:0]
Initial Value 01
R/W R/W
Description These bits select whether to change the order of 16-bit units of data transferred from the SSI module or suppress the stream data. In the SSI module, either "padding mode" or "non-padding mode" is selectable. In non-padding mode, each 32 bits of data transferred from the SSI are CD-ROM data. Since the CD-ROM decoder has two 16-bit input data registers, the order of the 16-bit data can be swapped within the 32 bits. On the other hand, in padding mode each 32 bits of data transferred from the SSI includes padding. Since the padding is without meaning, it should be kept out of the input stream to the decoder. This suppression can be specified by the setting of this register. The CD-ROM decoder handles data as a stream of 16bit data, and this register controls which 16-bit portion of each 32 bits of data transferred from the SSI should be input first. 00: The 16 bits of stream data that would otherwise be processed first is discarded. 01: The higher-order 16 bits of each 32 bits of data received from the SSI are placed first in the stream to the decoder. 10: The lower-order 16 bits of each 32 bits of data received from the SSI are placed first in the stream to the decoder. 11: Setting prohibited. If made, this setting will produce a malfunction.
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Section 21 CD-ROM Decoder (ROM-DEC)
Bit 3, 2
Bit Name BUFEND1 [1:0]
Initial Value 10
R/W R/W
Description These bits select whether to change the order of 16-bit units of data transferred from the SSI module or suppress the stream data. In the SSI module, either "padding mode" or "non-padding mode" is selectable. In non-padding mode, each 32 bits of data transferred from the SSI are CD-ROM data. Since the CD-ROM decoder has two 16-bit input data registers, the order of the 16-bit data can be swapped within the 32 bits. On the other hand, in padding mode each 32 bits of data transferred from the SSI includes padding. Since the padding is without meaning, it should be kept out of the input stream to the decoder. This suppression can be specified by the setting of this register. The CD-ROM decoder handles data as a stream of 16bit data, and this register controls which 16-bit portion of each 32 bits of data transferred from the SSI should be input second. 00: The 16 bits of stream data that would otherwise be processed second is discarded. 01: The higher-order 16 bits of each 32 bits of data received from the SSI are placed second in the stream to the decoder. 10: The higher-order 16 bits of each 32 bits of data received from the SSI are placed second in the stream to the decoder. 11: Setting prohibited. If made, this setting will produce a malfunction.
1, 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.49 Interrupt Flag Register (INTHOLD) INTHOLD consists of various interrupt flags.
Bit: 7 6 5
ISY
4
IERR
3
IBUF
2
IREADY
1 -- 0 R/W
0 -- 0 R/W
ISEC ITARG
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name ISEC
Initial Value R/W 0 R/W
Description ISEC Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it.
6
ITARG
0
R/W
ITARG Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it.
5
ISY
0
R/W
ISY Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it.
4
IERR
0
R/W
IERR Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it.
3
IBUF
0
R/W
IBUF Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it.
2
IREADY
0
R/W
IREADY Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it.
1, 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.50 Interrupt Source Mask Control Register (INHINT) INHINT controls masking of various interrupt requests in the CD-ROM decoder.
Bit: 7 6 5
INH ISY
4
INH IERR
3
INH IBUF
2
1
0
INH INH ISEC ITARG
INH PREINH PREINH IREADY REQDM IREADY
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6
Bit Name INHISEC INHITARG
Initial Value 0 0
R/W R/W R/W
Description ISEC Interrupt Mask When set to 1, masks the generation of ISEC interrupts ITARG Interrupt Mask When set to 1, masks the generation of ITARG interrupts
5 4 3 2
INHISY INHIERR INHIBUF INHIREADY
0 0 0 0
R/W R/W R/W R/W
ISY Interrupt Mask When set to 1, masks the generation of ISY interrupts IERR Interrupt Mask When set to 1, masks the generation of IERR interrupts IBUF Interrupt Mask When set to 1, masks the generation of IBUF interrupts IREADY Interrupt Mask When set to 1, masks the generation of IREADY interrupts
1
PREINH REQDM
0
R/W
Masks setting of the DMA transfer request interrupt flag for the output data stream. When set to 1, the DMA transfer request interrupt source is not retained.
0
PREINH IREADY
0
R/W
Masks setting of the IREADY interrupt flag. When set to 1, the interrupt source is not retained in the IREADY flag.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.51 Buffer Control Register (RINGBUFCTL) RINGBUFCTL introduces a delay in the DMA transfer request signal in order to reduce the time period over which the CD-ROM decoder is unable to respond due to ECC correction. Data from the CD-ROM decoder may be transferred by DMA or by the CPU; the former is triggered by asserting the DMA transfer request signal, while the latter is driven by the IREADY interrupt. When either the DMAC or CPU is trying to get output data for which the input data contained errors and is thus being subjected to ECC correction, a wait will be necessary because the CD-ROM decoder cannot respond during ECC correction.
Bit: 7 -- Initial value: 0 R/W: R/W 6 5 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W
DMREQDELAY [1:0]
0 R/W
0 R/W
Bit 7
Bit Name
Initial Value 0
R/W R/W
Description Reserved This bit is always read as 0.The write value should always be 0.
6, 5
DMREQDELAY [1:0]
00
R/W
00: Assertion of the DMA transfer request signal is not delayed. 01: Assertion of the DMA transfer request signal is delayed by 256 cycles. 10: Assertion of the DMA transfer request signal is delayed by 512 cycles. 11: Assertion of the DMA transfer request signal is delayed by 1024 cycles.
4 to 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN0) STRMDIN0 indicates the 1 byte (from MSB) of the 4 bytes of data that is to be input to the CDROM decoder.
Bit: 7 6 5 4 3 2 1 0
STRMDIN[31:24] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name STRMDIN [31:24]
Initial Value All 0
R/W R/W
Description The highest-order byte (MSB) of the 4-byte input to the CD-ROM decoder The CD-ROM decoder has a 4-byte wide data window or set of registers for data input. The data input to these registers is handled as a data stream. The amount of data for one sector is 2352 bytes.
21.3.53 CD-ROM Decoder Stream Data Input Register (STRMDIN1) STRMDIN1 indicates the next 1 byte, in order from STRMDIN0, of the 4-byte input to the CDROM decoder.
Bit: 7 6 5 4 3 2 1 0
STRMDIN[23:16] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name STRMDIN [23:16]
Initial Value All 0
R/W R/W
Description The next byte, in order from STRMDIN0, of the 4-byte input to the CD-ROM decoder The CD-ROM decoder has a 4-byte wide data window or set of registers for data input. The data input to these registers is handled as a data stream. The amount of data for one sector is 2352 bytes.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.54 CD-ROM Decoder Stream Data Input Register (STRMDIN2) STRMDIN2 indicates the next 1 byte, in order from STRMDIN1, of the 4-byte input to the CDROM decoder.
Bit: 7 6 5 4 3 2 1 0
STRMDIN[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name STRMDIN [15:8]
Initial Value All 0
R/W R/W
Description The next byte, in order from STRMDIN1, of the 4-byte input to the CD-ROM decoder The CD-ROM decoder has a 4-byte wide data window or set of registers for data input. The data input to these registers is handled as a data stream. The amount of data for one sector is 2352 bytes.
21.3.55 CD-ROM Decoder Stream Data Input Register (STRMDIN3) STRMDIN3 indicates the 1 byte (from LSB) of the 4 bytes of data that is to be input to the CDROM decoder.
Bit: 7 6 5 4 3 2 1 0
STRMDIN[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name STRMDIN [7:0]
Initial Value All 0
R/W R/W
Description The lowest-order byte (LSB) of the 4-byte input to the CD-ROM decoder The CD-ROM decoder has a 4-byte wide data window or set of registers for data input. The data input to these registers is handled as a data stream. The amount of data for one sector is 2352 bytes.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.3.56 CD-ROM Decoder Stream Data Output Register (STRMDOUT0) STRMDOUT0 indicates the 1 byte (from MSB) of the 2 bytes of data that is to be output to the CD-ROM decoder.
Bit: 7 6 5 4 3 2 1 0
STRMDOUT[15:8] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name STRMDOUT [15:8]
Initial Value All 0
R/W R/W
Description The higher-order byte (MSB) of the 2-byte output from the CD-ROM decoder The CD-ROM decoder has a 2-byte wide data window or set of registers for the output of decoded data. Every time the relevant register is accessed, further data are output sequentially in the output format which is separately defined. The amount of data for one sector is 2768 bytes. Always read 2768 bytes.
21.3.57 CD-ROM Decoder Stream Data Output Register (STRMDOUT1) STRMDOUT1 indicates the 1 byte (from LSB) of the 2 bytes of data that is to be output to the CD-ROM decoder.
Bit: 7 6 5 4 3 2 1 0
STRMDOUT[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7 to 0
Bit Name STRMDOUT [7:0]
Initial Value All 0
R/W R/W
Description The lower-order byte (LSB) of the 2-byte output from the CD-ROM decoder The CD-ROM decoder has a 2-byte wide data window or set of registers for the output of decoded data. Every time the relevant register is accessed, further data are output sequentially in the output format which is separately defined. The amount of data for one sector is 2768 bytes. Always read 2768 bytes.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.4
21.4.1
Operation
Endian Conversion for Data in the Input Stream
Stream data must be input to the core of the CD-ROM decoder in order according to the CD-ROM data format specifications. In some systems, however, the order of the data from the SSI may have to be changed or the data will have been padded before transfer. To cope with this, the stream data input control section is capable of swapping the order of the data and preventing the input of padding data to the core of the CD-ROM decoder. These functions are controlled through the SSI data control register (SSI). Figure 21.6 shows a case where the upper and lower 16 bits of the data, consisting of padding data plus the first 2 bytes of sync code, that is, H'000000FF, are swapped (H'00FF0000) and input to the CD-ROM decoder as the stream data.
BUFEND0[1:0] = 01
STRMDIN0, STRMDIN1
H'FF
H'00FF
H'00FF
H'00
H'00FF STRMDIN2, STRMDIN3
Core of CD-ROM decoder
H'00
H'00
H'0000
BUFEND1[1:0] = 00 BYTEND = 0
Figure 21.6 Example of Padded Stream Data Control by the SSI Register
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Section 21 CD-ROM Decoder (ROM-DEC)
Figure 21.7 shows a case of input stream data that has no padding (H'12345678). The upper and lower 16 bits of data are swapped (H'56781234) for input to the CD-ROM decoder.
STRMDIN0, STRMDIN1 BUFEND0[1:0] = 10 H'1234 is input first. H'5678 is input next.
H'78
H'5678
H'1234
H'56
H'1234 STRMDIN2, STRMDIN3
H'5678
Core of CD-ROM decoder
H'34
H'012
H'5678 H'1234
BUFEND1[1:0] = 01 BYTEND = 0
Figure 21.7 Example of Non-Padded Stream Data Control by the SSI Register 21.4.2 Sync Code Maintenance Function
Each sector of CD-ROM data consists of 2352 bytes starting with H'00FFFFFFFFFFFFFFFFFFFF00 (sync code). However, a scratch on the disc or some other factor might lead to erroneous recognition of the sync code sequence at the wrong time. Conversely, a sync code might not be detected at a point where it should be detected. As a solution to these problems, the CD-ROM decoder of this LSI has a sync-code maintenance function, which operates to ignore sync codes detected at abnormal times and maintain the appearance of the sync code at the expected times when it is not actually detected on the disc. The operating modes of the sync-code maintenance function are listed below. For details on the settings, refer to section 21.3.2, Sync Code-Based Synchronization Control Register (CROMSY0), and table 21.2. * * * * Automatic sync maintenance mode External sync mode Interpolated sync mode Interpolated sync plus external sync mode
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Section 21 CD-ROM Decoder (ROM-DEC)
(1)
Automatic Sync Maintenance Mode
In automatic sync maintenance mode, the sync code is ignored if detected within the one-sector (2352-byte) period. Furthermore, if a sync code is not detected at the point where a next sector should start, sync code maintenance is applied. If synchronization timing has changed, resynchronization is performed at the point where a sync code is detected within 2352 bytes after the change. Therefore, this mode is effective in rejecting abnormal sync patterns and following changes in synchronization timing. Note, however, that this mode cannot achieve synchronization with the first sector after a change to the synchronization timing. Figure 21.8 shows operation in the case of normal sync-code detection, figure 21.9 shows a case where a sync code is detected before a current one-sector period has elapsed, and figure 21.10 shows the case where the actual sync code is only detected some time after a full one-sector period has elapsed.
Input data Sync code detection Output data
Sector 1 Sector 2 Sector 3 Sector 4 Sector 6
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Figure 21.8 Operation in Automatic Sync Maintenance Mode (Normal Timing)
Abnormal sector Intput data Sync code detection Re-synchronization Ignore Maintain Ignore Maintain Sector 1 Sector 3 Sector 4 Sector 5 Sector 6
Output data
Sector 1
Sector 5
Abnormal sector
Abnormal Abnormal sector sector
Figure 21.9 Operation in Automatic Sync Maintenance Mode (When an Abnormally Short Sector is Encountered)
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Section 21 CD-ROM Decoder (ROM-DEC)
Abnormal sector Intput data Sync code detection Maintain
Sector 1
Sector 1
Sector 3
Sector 4
Sector 5
Ignore
Maintain
Re-synchronization
Output data
Sector 4
Abnormal sector
Abnormal sector
Figure 21.10 Operation in Automatic Sync Maintenance Mode (When an Abnormally Long Sector is Encountered) (2) External Sync Mode
In external sync mode, synchronization is always based on the sync codes in the incoming data. Even if the next sync code is not detected at the 2352nd byte, decoding does not proceed until the next sync code is detected. Accordingly, this mode is effective in that it strictly follows the external synchronization timing. Note, however, that decoding will not be performed normally when the sync-code pattern is input with abnormal timing. Figure 21.11 shows the operation in external sync mode.
Abnormal sector Intput data Sync code detection Sector 1 Sector 3 Sector 4 Sector 5
Output data
Sector 1
Sector 3
Sector 4
Abnormal sector
Figure 21.11 Operation in External Sync Mode
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Section 21 CD-ROM Decoder (ROM-DEC)
(3)
Interpolated Sync Mode
In interpolated sync mode, synchronization is always driven by the internal counter after a sync code pattern has been detected at the start of decoding. Accordingly, this mode is effective when the sync patterns have been damaged. However, decoding becomes incorrect after a change to the synchronization timing, since the change in timing is not followed. Figure 21.12 shows the operation in interpolated sync mode.
Abnormal sector Intput data Sync code detection Maintain
Sector 1
Sector 1
Sector 3
Sector 4
Sector 5
Ignore Maintain Ignore Maintain Ignore Maintain
Output data Abnormal sector Abnormal sector Abnormal sector Abnormal sector
Figure 21.12 Operation in Interpolated Sync Mode (4) Interpolated Sync Plus External Sync Mode
In interpolated sync plus external sync mode, synchronization is based on the detected sync code patterns as long as they are present, and if a sync pattern is not detected at the 2352nd byte, the sync code maintenance is applied. Synchronization in this mode is more quickly responsive to changes in synchronization timing than synchronization in the automatic sync maintenance mode. However, decoding still becomes incorrect when a sync pattern is input with abnormal timing.
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Section 21 CD-ROM Decoder (ROM-DEC)
Figures 21.13 and 21.14 show the operation in interpolated sync plus external sync mode in the cases of abnormally short and long sectors, respectively.
Abnormal sector Intput data Sync code detection Maintain Sector 1 Sector 3 Sector 4 Sector 5 Sector 6
Output data
Sector 1
Sector 3
Sector 4
Sector 5
Abnormal sector
Figure 21.13 Operation in Interpolated Sync Plus External Sync Mode (When an Abnormally Short Sector is Encountered)
Abnormal sector Intput data Sync code detection Maintain
Sector 1 Sector 3 Sector 4
Sector 1
Sector 3
Sector 4
Sector 5
Output data
Abnormal sector
Abnormal sector
Figure 21.14 Operation in Interpolated Sync Plus External Sync Mode (When an Abnormally Long Sector is Encountered)
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Section 21 CD-ROM Decoder (ROM-DEC)
21.4.3
Error Correction
The CD-ROM decoder handles data in the formats containing information relevant to error correction, including the EDC, P parity, and Q parity. The CD-ROM decoder includes the following features for use in error correction. * Syndrome calculation * ECC correction * EDC checking (1) Syndrome Calculation
After the data of a sector in Mode 1 or Form 1 of Mode 2 has been input, the ECC is used in correction if any error is detected (the result of syndrome calculation is non-zero). After correction, the results of syndrome operation for the corrected data are output to bits ST_ECCP (P parity) and ST_ECCQ (Q parity) in the CROMST6 register, respectively. (2) ECC correction and EDC Checking
For CD-ROM format data that contains EDC, P-parity, and Q-parity fields, the CD-ROM decoder performs EDC checking and ECC correction. Supported correction modes are P correction, Q correction, PQ correction (P correction followed by Q correction), and QP correction (Q correction followed by P correction). In PQ and QP correction modes, up to three iterations of correction are possible (the number of iterations is limited by the playback speed). The EDC check is performed twice, before and after correction. The mode of ECC correction and EDC checking is specified by bits MD_DEC[2:0] in the CROMCTL1 register. When the PQ or QP correction mode is selected, the number of iterations is specified by bits MD_PQREP[1:0] in the CROMCTL1 register. When the automatic mode/form detection function is in use, the sector mode determines whether or not ECC correction and EDC checking can be performed. For sectors in Mode 0 and Mode 2 (non-XA), which include neither parity bits nor EDC, ECC correction and EDC checking are not performed. For sectors in Form 2 of Mode 2, ECC correction is not performed. (a) ECC Correction
When ECC correction is in use and an error in a sector is identified as non-correctable, the CDROM decoder generates an IERR interrupt and sets the ST_ECCNG bit of the CROMST6 register to 1. The CD-ROM detector also sets this bit to 1 on detecting a short sector.
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Section 21 CD-ROM Decoder (ROM-DEC)
While the NO_ECC bit of the CROMCTL4 register is set to 1, a 'pass' result in pre-correction EDC checking makes the CD-ROM decoder skip ECC correction, regardless of the results of the syndrome operation. (b) EDC Checking
When EDC checking is in use, checking is in line with the specified or detected sector mode and form, depending on whether or not automatic sector mode and form detection is selected. The results of EDC checking before and after correction are reflected in the ST_EDC1 and ST_EDC2 bits of the CROMST6 register, respectively. If EDC checking after ECC correction indicates that an error remains, an IERR interrupt is generated. 21.4.4 Automatic Decoding Stop Function
Decoding can be stopped automatically in response to an error during the decoding of CD-ROM data. The possible conditions for automatically stopping the decoding process are listed below. The applicable conditions are specified in the CROMCTL3 register. * * * * An error is found to be not correctable by ECC correction. Post-correction EDC checking indicates that an error remains. A change of the sector mode or form. A non-sequential MSF (minutes, seconds, frames (1/75 second)) value.
When automatic stopping is set up and any of the above conditions is encountered in a certain sector, the decoding is stopped after the results of decoding for that sector have been output. After decoding has been stopped in response to a condition specified in the CROMCTL3 register, the condition can be identified by reading the CBUFST1 register. The CD-ROM decoder has buffer space for two sectors. If input of the data stream continues and the output stream of data is not read, the CD-ROM decoder stops at the point where the data of a third sector starts to be input. At this time, the BUF_NG bit in the CBUFST2 register is set to 1, but no interrupt is generated. Once the BUF_NG bit in the CBUFST2 register has been set to 1, recovery can only be accomplished by using the LOGICRST bit in the ROMDECRST register to reset the CD-ROM decoder function. When the LOGICRST bit in the ROMDECRST register is set to 1, a reset signal is output and any registers in which settings have been made are cleared to their initial values.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.4.5
Buffering Format
Figure 21.15 shows the format of the output data stream produced by CD-ROM decoding. A 2-byte-wide window register is provided for the output. When this window register is accessed after decoding of a CD-ROM sector has finished, the bytes of data are output in order from the sync code.
Sync code Header Subheader
12 bytes 4 bytes 8 bytes
Data
2048 bytes
EDC
2768 bytes
4 bytes 276 bytes
ECC
Erasure H'00 Reserved H'0000 H'0000 Status (see below) H'0000 Reserved Storage flag Block error
294 bytes 2 bytes 108 bytes 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes
Figure 21.15 Output Data Stream Format
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Section 21 CD-ROM Decoder (ROM-DEC)
The meanings of bits in the two-byte status field shown in figure 21.15 are given below. The values of the non-assigned bits are undefined.
Status 15 14 13 12 -- 11 -- 10 -- 9 -- 8 -- 7 SD 6 SY 5 4 FM[2:0] 3 2 HD 1 -- 0 --
PERR QERR EDCE
PERR: QERR: EDCE: SD: SY: FM:
HD:
Indicates that a P-parity error remains. Indicates that a Q-parity error remains. Indicates that a remaining error was detected in post-correction EDC checking. Indicates that a short sector was encountered Indicates that a sync code was interpolated. Indicates the data format 001: Mode 0 010: Mode 1 011: Long (format with no EDC and ECC) 100: Mode 2 (non-XA) 101: Mode 2 Form 1 111: Mode 2 Form 2 Header continuity (minutes, seconds, and frames (1/75) are non-sequential)
The value of the storage flag field in figure 21.15 is incremented every time the data for one sector are output. The value starts at H'0000 and wraps back around to H'0000 after incrementation reaches H'FFFF.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.4.6
Target-Sector Buffering Function
In the CD-ROM decoder, the sector for output can be designated in two ways: automatic buffering, where the CD-ROM decoder itself detects the presence of target sectors, and manual buffering, where the target sector for output is designated by software and the software also recognizes the sectors buffered in the CD-ROM decoder. The following describes the procedures for setting the registers in the CD-ROM decoder to set up automatic or manual buffering. (1) Setting Up Automatic Buffering
Figure 21.16 shows an example of setting up the automatic buffering. Set the relevant CD-ROM decoder registers and start input of the data stream; the CD-ROM decoder then detects the target sector and starts the output of the stream data.
Start of automatic buffering setup
Set both the CBUF_AUT and CBUF_EN bits in CBUFCTL0 to 1
[1]
[1] Turn on the automatic buffering function and enable buffering in the buffer RAM. [2] Set the minutes value of the target sector.
Set CBUFCTL1
[2] [3] Set the seconds value of the target sector. [4] Set the frame value of the target sector.
Set CBUFCTL2
[3] [5] Enable subcode processing and CD-ROM decoding.
Set CBUFCTL3
[4]
Set both the SUBC_EN and CROM_EN bits in CROMEN to 1
[5]
End of automatic buffering setup
Figure 21.16 Example of Setting Up Automatic Buffering
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Section 21 CD-ROM Decoder (ROM-DEC)
(2)
Setting Up Manual Buffering
Figure 21.17 shows an example of setting up manual buffering. Each time an ISEC interrupt is generated, the software checks whether or not the sector is the target sector and starts buffering when the target sector is found .
Start of automatic buffering setup
Clear both the CBUF_AUT and CBUF_EN bits in CBUFCTL0 to 0
[1]
[1] Turn off the automatic buffering function and disable buffering in the buffer RAM. [2] Enable subcode processing and CD-ROM decoding.
Set both the CBUF_AUT and CBUF_EN bits in CBUFCTL0 to 1
[2]
[3] Start input of the data stream.
Generation of an ISEC interrupt
[3]
Read HEAD02, etc.
Target sector?
No
Yes Set the CBUF_EN bit in CBUFCTL0 to 1
End of automatic buffering setup
Figure 21.17 Example of Setting Up Manual Buffering
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Section 21 CD-ROM Decoder (ROM-DEC)
21.5
21.5.1
Interrupt Sources
Interrupt and DMA Transfer Request Signals
Table 21.3 lists the interrupt signals and DMA transfer request signal generated by the CD-ROM decoder, along with the meanings and the modules to which the signals are connected. Table 21.3 Interrupt and DMA Transfer Request Signals
Name ISEC ITARG ISY IERR IBUF IREADY DMA transfer request Description Transitions from sector to sector Access to a CD-ROM sector that is not the expected target sector A sync code from the CD-ROM with abnormal timing Connected To INTC INTC INTC
An error that was not correctable by ECC correction or an error INTC indicated by EDC checking after ECC correction State changes in data transfer to the buffer Request for data transfer to the buffer for CD-ROM Request for data transfer to the buffer for CD-ROM INTC INTC DMAC
The above interrupt signals are generated by the following sources (1) ISEC
This interrupt is generated when the sync code indicates a transition from sector to sector. (2) ITARG
This interrupt reports that the stream data transferred from the CD-DSP is not the data of the target sector. The CD-ROM decoder checks the time data in the subcode. In correct operation, data transfer is expected to start slightly before the target sector. An ITARG interrupt is generated in the following cases. * When data of a sector preceding the target sector by quite a few sectors have been transferred * When data of a sector that comes after the target sector have been transferred For the generation of this interrupt, ITARG is detected from the subcode. However, this interrupt has no meaning in this LSI because CD-ROM data are transferred from the SSI module.
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Section 21 CD-ROM Decoder (ROM-DEC)
(3)
ISY
This interrupt can be generated in the following cases. * When a sync code was detected at a position where the value in the word counter (counter for checking sync code intervals) was not correct and the sync code was ignored * When a sync code has not been detected although the word counter has reached the final value and a sync code has been interpolated (for sync maintenance) * When a sync code was detected at a position where the value in the word counter (counter for checking sync code intervals) was not correct and the sync code was used in resynchronization * When a sync code has not been detected although the word counter has reached the final value, so the period taken up by the sector has been prolonged * When the sector has been processed as a short sector with the aid of interpolated sync codes * When the sector has been processed as a long sector with the aid of interpolated sync codes (4) IERR
This interrupt is generated in the following cases. * When ECC correction was incapable of correcting an error * When ECC correction was OK but the subsequent EDC check indicated an error (5) IBUF
This interrupt is generated when the following transitions occur. * Data transfer to the buffer Data transfer complete (searching for data for the next transfer) * Data for transfer to the buffer are being searched for Data transfer started (6) IREADY
This interrupt is generated when decoding of data for one sector is completed. This interrupt should be used to start the CPU buffering stream data for output to SDRAM. (7) DMA Transfer Request
The source of DMA activation is the same as that of IREADY. An interrupt request is generated when output stream data for one sector becomes ready, and after the 2768 bytes of data shown in figure 21.15 have been transferred, the request signal is negated once. This is because a certain amount of time is required before the output data for the next sector is ready, so the transfer request from the DMAC should be turned off between transfers.
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Section 21 CD-ROM Decoder (ROM-DEC)
21.5.2
Timing of Status Registers Updates
The status information registers of the CD-ROM decoder are updated on each ISEC interrupt. The sector for which information is reflected in the status registers is selected by the ER0SEL bit of the CROMCTL4 register.
21.6
21.6.1
Usage Notes
Stopping and Resuming Buffering Alone During Decoding
When the data of the output stream are being not read out but operation of the CD-ROM decoder has continued until the buffers are full, the BUF_NG bit in the CBUFST2 register is set to 1; after that, the CD-ROM decoder becomes incapable of operation. To stop buffering alone, clear the CBUF_EN bit in the CBUFCTL0 register to 0. If the automatic buffering function is in use, clear the CBUF_AUT in the CBUFCTL0 register to 0 at the same time. In this case, the sectors currently in the buffers must be read out. To resume automatic buffering, set the CBUF_AUT and CBUF_EN bits in the CBUFCTL0 register at the same time. 21.6.2 When CROMST0 Status Register Bits are Set
1. When the ST_SECS bit in the CROMST0 register becomes set, stop decoding immediately and retry from one sector before the sector that was being decoded. 2. When the ST_SECL bit in the CROMST0 register becomes set, stop decoding immediately and retry from two sectors before the sector that was being decoded. 21.6.3 Link Blocks
The CD-ROM decoder uses the header information before ECC correction to detect link blocks. Accordingly, an input data stream that contains an error may be erroneously detected as a link block. To prevent this, the following measures should be implemented in software. * During buffering (BUF_ACT = 1 in the CBUFST0 register), check the LINK_OUT1 bit in the CROMST5 register on each ISEC interrupt. If it is set to 1, check to see if an IERR interrupt has also occurred; if an IERR interrupt has not occurred, save the MFS values from the HEAD20 to HEAD23 registers. If an IERR interrupt has occurred, do not save the MSF values.
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Section 21 CD-ROM Decoder (ROM-DEC)
* Perform the following processing for seven sectors (indicated by ISEC being generated seven times) after finding that the LINK_OUT1 bit has been set to 1. In either of cases 1 and 2 below, 1. LINK_ON = 1 (in the CROMST5 register) is confirmed at each ISEC interrupt, and LINK_ON = 1 is detected again within the subsequent two-sector period 2. LINK_ON = 1 was not detected at any ISEC interrupt forcibly stop decoding, set the CROMSY0 register to place the decoder in external sync mode, and retry decoding by specifying the MSF value stored above + 7 as the MSF value for the target sector. The start sector address will be the address where RUN_OUT is stored + 7 when CBUF_LINK = 0, and the address where RUN_OUT is stored when CBUF_LINK = 1. 21.6.4 Reading from the STRMDOUT0 and STRMDOUT1 Registers
When the input stream of data contains an error and ECC correction is executed, the process of reading from the STRMDOUT0 and STRMDOUT1 registers will be kept waiting by the execution of ECC correction if the read request is made immediately after an IREADY interrupt or DMA transfer trigger signal has been generated. This only applies to the first time the registers are read in the reading of one sector. In cases where CD-ROM decoding cannot be performed if kept waiting (for example, when the STRMDOUT0 and STRMDOUT1 registers are read by DMA transfer and input and output for the SSI are also handled by DMA transfer, so that DMA transfer for the SSI must be carried out with a fixed period), use the DMAREQDELAY[1:0] bits in the RINGBUFCTL register to delay the DMA activation signal. This can reduce the length of the wait before reading from the STRMDOUT0 and STRMDOUT1 registers. Table 21.4 shows the waiting times for the first reading of STRMDOUT0 and STRMDOUT1 as approximate numbers of cycles. The number of wait cycles varies according to the positions of any errors for which ECC processing is performed and so on.
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Section 21 CD-ROM Decoder (ROM-DEC)
Table 21.4 Number of Wait Cycles for Reading STRMDOUT0 and STRMDOUT1 Registers
Number of Wait Cycles when Delay is Introduced Number of ECC Corrections 1 Number of Wait Cycles 370 to 1400 DMAREQDELAY[1:0] Setting 0 1 2 3 2 720 to 1900 0 1 2 3 3 1070 to 2400 0 1 2 3 Number of Wait Cycles 370 to 1040 114 to 1144 0 to 888 0 to 376 720 to 1900 464 to 1644 208 to 1388 0 to 876 1070 to 2400 814 to 2144 558 to 1888 46 to 1376
When the number of the ECC correction is 1 and the DMAREQDELAY[1:0] setting is 3, the period of waiting is up to 376 cycles. If the CD-ROM decoding is not completed in this waiting time, take the waiting time into account in software for DMAC activation. In addition, the effect of DMAREQDELAY[1:0] in reducing the wait only applies to the DMA activation signal. Since the IREADY interrupt cannot be delayed, waiting time must be taken into account in the software if the STRMDOUT0 and STRMDOUT1 registers are to be read by the CPU. 21.6.5 Stopping and Resuming CD-DSP Operation
When stopping and resuming the stream data input to the CD-ROM decoder, note that the input data stream does not stop immediately before a sync code and that the CD-ROM decoder may recognize the data as incorrect when the input stream is resumed. This happens because the system holds a combination of the data up to the point where input was stopped and data that is input from the point of resumption. Take care on this point when stopping and resuming input.
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Section 22 A/D Converter (ADC)
Section 22 A/D Converter (ADC)
This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels.
22.1
* * * *
Features
* * *
*
*
Resolution: 10 bits Input channels: 8 Minimum conversion time: 3.9 s per channel Operating modes: 3 Single mode: A/D conversion on one channel Multi mode: A/D conversion on one to four channels or on one to eight channels Scan mode: Continuous A/D conversion on one to four channels or on one to eight channels Data registers: 8 Conversion results are held in a 16-bit data register for each channel Sample-and-hold function A/D conversion start methods: 4 Software Conversion start trigger from multi-function timer pulse unit 2 (MTU2) Conversion start trigger from the 8-bit timer (TMR) External trigger signal Interrupt source An A/D conversion end interrupt (ADI) request can be generated on completion of A/D conversion. Module standby mode can be set
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Section 22 A/D Converter (ADC)
Figure 22.1 shows a block diagram of the A/D converter.
Module data bus
ADDRG
ADDRC
ADDRD
ADDRH
ADDRA
ADDRB
ADDRE
AVref AVss
10-bit D/A
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Multiplexer
+ - Comparator Sample-and-hold circuit Control circuit
ADCSR
ADDRF
AVcc
Successiveapproximation register
Bus interface
Peripheral bus
ADTRG, conversion start trigger from MTU2 or TMR ADI interrupt signal
[Legend] ADCSR: ADDRA: ADDRB: ADDRC: ADDRD:
A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
ADDRE: ADDRF: ADDRG: ADDRH:
A/D data register E A/D data register F A/D data register G A/D data register H
Figure 22.1 Block Diagram of A/D Converter
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Section 22 A/D Converter (ADC)
22.2
Input/Output Pins
Table 22.1 summarizes the A/D converter's input pins. Table 22.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Reference power supply pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Symbol AVcc AVss AVref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input to start A/D conversion Function Analog power supply pin Analog ground pin and A/D conversion reference ground A/D converter reference voltage pin Analog input
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Section 22 A/D Converter (ADC)
22.3
Register Configuration
The A/D converter has the following registers. Table 22.2 Register Configuration
Register Name A/D data register A A/D data register B A/D data register C A/D data register D A/D data register E A/D data register F A/D data register G A/D data register H A/D control/status register Abbreviation ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR R/W R R R R R R R R R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0040 Address H'FFFE5800 H'FFFE5802 H'FFFE5804 H'FFFE5806 H'FFFE5808 H'FFFE580A H'FFFE580C H'FFFE580E H'FFFE5820 Access Size 16 16 16 16 16 16 16 16 16
22.3.1
A/D Data Registers A to H (ADDRA to ADDRH)
The sixteen A/D data registers, ADDRA to ADDRH, are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15 to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0. Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units. ADDR is initialized to H'0000 by a power-on reset as well as in deep standby mode, software standby mode or module standby mode.
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Section 22 A/D Converter (ADC)
Table 22.3 indicates the pairings of analog input channels and ADDR.
Bit: 15 14 13 12 11 10 9 8 7 6 5 -- Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 15 to 6 5 to 0
Bit Name
Initial Value All 0 All 0
R/W R R
Description Bit data (10 bits) Reserved These bits are always read as 0. The write value should always be 0.
Table 22.3 Analog Input Channels and ADDR
Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register where Conversion Result is Stored ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH
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Section 22 A/D Converter (ADC)
22.3.2
A/D Control/Status Register (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter, and enables or disables starting of A/D conversion by external trigger input. ADCSR is initialized to H'0040 by a power-on reset as well as in deep standby mode, software standby mode or module standby mode.
Bit: 15 14 13 12 -- 0 R 0 R/W 11 10 9 8 7 6 5 4 MDS[2:0] 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 CH[2:0] 0 R/W 0 R/W 0
ADF ADIE ADST Initial value: 0 0 R/W: R/(W)* R/W 0 R/W
TRGS[3:0] 0 R/W 0 R/W 0 R/W
CKS[1:0] 0 R/W 1 R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit 15
Bit Name ADF
Initial Value 0
R/W
1
Description
R/(W)* A/D End Flag Status flag indicating the end of A/D conversion. [Clearing conditions] * * Cleared by reading ADF while ADF = 1, then writing 0 to ADF Cleared when DMAC is activated by ADI interrupt and ADDR is read A/D conversion ends in single mode A/D conversion ends for the selected channels in multi mode A/D conversion ends for the selected channels in scan mode
[Setting conditions] * * * 14 ADIE 0 R/W
A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled
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Section 22 A/D Converter (ADC)
Bit 13
Bit Name ADST
Initial Value 0
R/W R/W
Description A/D Start Starts or stops A/D conversion. This bit remains set to 1 during A/D conversion. 0: A/D conversion is stopped 1: Single mode: A/D conversion starts. This bit is automatically cleared to 0 when A/D conversion ends on the selected channel. Multi mode: A/D conversion starts. This bit is automatically cleared to 0 when A/D conversion is completed cycling through the selected channels. Scan mode: A/D conversion starts. A/D conversion is continuously performed until this bit is cleared to 0 by software, by a power-on reset as well as by a transition to deep standby mode, software standby mode or module standby mode.
12
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 22 A/D Converter (ADC)
Bit 11 to 8
Bit Name TRGS[3:0]
Initial Value 0000
R/W R/W
Description Timer Trigger Select These bits enable or disable starting of A/D conversion by a trigger signal. 0000: Start of A/D conversion by external trigger input is disabled 0001: A/D conversion is started by conversion trigger TRGAN from MTU2 0010: A/D conversion is started by conversion trigger TRG0N from MTU2 0011: A/D conversion is started by conversion trigger TRG4AN from MTU2 0100: A/D conversion is started by conversion trigger TRG4BN from MTU2 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1000: Setting prohibited 1001: A/D conversion is started by ADTRG 1010: A/D conversion is started by conversion trigger from the TMR 1011 to 1111: Setting prohibited
7, 6
CKS[1:0]
01
R/W
Clock Select
2 These bits select the A/D conversion time. * Set the A/D conversion time while A/D conversion is halted (ADST = 0).
00: Conversion time = 138 states (maximum) 01: Conversion time = 274 states (maximum) 10: Conversion time = 546 states (maximum) 11: Setting prohibited
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Section 22 A/D Converter (ADC)
Bit 5 to 3
Bit Name MDS[2:0]
Initial Value 000
R/W R/W
Description Multi-scan Mode These bits select the operating mode for A/D conversion. 0xx: Single mode 100: Multi mode: A/D conversion on 1 to 4 channels 101: Multi mode: A/D conversion on 1 to 8 channels 110: Scan mode: A/D conversion on 1 to 4 channels 111: Scan mode: A/D conversion on 1 to 8 channels
2 to 0
CH[2:0]
000
R/W
Channel Select These bits and the MDS bits in ADCSR select the analog input channels. MDS2 = 1, MDS2 = 1, MDS0 = 0 MDS0 = 1 MDS2 = 0 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 000: AN0 001: AN0, AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN4 101: AN4, AN5 110: AN4 to AN6 111: AN4 to AN7 000: AN0 001: AN0, AN1 010: AN0 to AN2 011: AN0 to AN3 100: AN0 to AN4 101: AN0 to AN5 110: AN0 to AN6 111: AN0 to AN7
Note: These bits must be set so that ADCSR_0 and ADCSR_1 do not have the same analog inputs. [Legend] x: Don't care Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. To satisfy the absolute accuracy of the A/D converter characteristics, set a value greater than the minimum conversion time.
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Section 22 A/D Converter (ADC)
22.4
Operation
The A/D converter uses the successive-approximation method, and the resolution is 10 bits. It has three operating modes: single mode, multi mode, and scan mode. Switching the operating mode or analog input channels must be done while the ADST bit in ADCSR is 0 to prevent incorrect operation. The ADST bit can be set at the same time as the operating mode or analog input channels are changed. 22.4.1 Single Mode
Single mode should be selected when only A/D conversion on one channel is required. In single mode, A/D conversion is performed once for the specified one analog input channel, as follows: 1. A/D conversion for the selected channel starts when the ADST bit in ADCSR is set to 1 by software, MTU2, TMR, or external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the A/D data register corresponding to the channel. 3. After A/D conversion has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D conversion is completed, and the A/D converter becomes idle. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel selection is switched.
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Section 22 A/D Converter (ADC)
Typical operations when a single channel (AN1) is selected in single mode are described next. Figure 22.2 shows a timing diagram for this example (the bits which are set in this example belong to ADCSR). 1. Single mode is selected, input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADF = 1, and then writes 0 to the ADF flag. 6. The routine reads and processes the A/D conversion result (ADDRB). 7. Execution of the A/D interrupts handling routine ends. Then, when the ADST bit is set to 1, A/D conversion starts and steps 2. to 7. are executed.
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Set* Set* A/D conversion starts Clear* Clear* Set* Waiting Waiting Waiting Conversion time 1 Conversion time 2 Waiting Waiting Waiting Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2
ADIE
Section 22 A/D Converter (ADC)
ADST
ADF
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Channel 0 (AN0) operating
Channel 1 (AN1) operating
Channel 2 (AN2) operating
Channel 3 (AN3) operating
ADDRA
ADDRB
Figure 22.2 Example of A/D Converter Operation (Single Mode, One Channel (AN1) Selected)
ADDRC
ADDRD
Note: * Vertical arrows ( ) indicate instruction execution by software.
Section 22 A/D Converter (ADC)
22.4.2
Multi Mode
Multi mode should be selected when performing A/D conversion once on one or more channels. In multi mode, A/D conversion is performed once for a maximum of eight specified analog input channels, as follows: 1. A/D conversion starts from the analog input channel with the lowest number (e.g. AN0, AN1, ..., AN3) when the ADST bit in ADCSR is set to 1 by software, MTU2, TMR, or external trigger input. 2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially transferred to the A/D data register corresponding to that channel. 3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D conversion is completed, and the A/D converter becomes idle. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion is halted and the A/D converter becomes idle. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. A/D conversion is to be performed once on all the specified channels. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in multi mode are described next. Figure 22.3 shows a timing diagram for this example. 1. Multi mode is selected (MDS2 = 1, MDS1 = 0), analog input channels AN0 to AN2 are selected (CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D conversion result is transferred into ADDRA. 3. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and the ADST bit cleared to 0. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested.
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A/D conversion Clear* Set* Clear* Waiting Conversion time 1 Waiting Waiting Conversion time 2 Waiting Waiting Conversion time 3 Waiting Waiting A/D conversion result 1 A/D conversion result 2 A/D conversion result 3
ADST
Section 22 A/D Converter (ADC)
ADF
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Channel 0 (AN0) operating
Channel 1 (AN1) operating
Channel 2 (AN2) operating
Channel 3 (AN3) operating
ADDRA
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested.
ADDRB
ADDRC
Figure 22.3 Example of A/D Converter Operation (Multi Mode, Three Channels (AN0 to AN2) Selected)
ADDRD
Note: * Vertical arrows ( ) indicate instruction execution by software.
Section 22 A/D Converter (ADC)
22.4.3
Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels at all times. In scan mode, A/D conversion is performed sequentially for a maximum of eight specified analog input channels, as follows: 1. A/D conversion for the selected channels starts from the analog input channel with the lowest number (e.g. AN0, AN1, ..., AN3) when the ADST bit in ADCSR is set to 1 by software, MTU2, TMR, or external trigger input. 2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially transferred to the A/D data register corresponding to that channel. 3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The A/D converter starts A/D conversion again from the channel with the lowest number. 4. The ADST bit is not cleared automatically, so steps 2. and 3. are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion halts and the A/D converter becomes idle. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described as follows. Figure 22.4 shows a timing diagram for this example. 1. Scan mode is selected (MDS2 = 1, MDS1 = 1), analog input channels AN0 to AN2 are selected (CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D conversion result is transferred into ADDRA. 3. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested.
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Section 22 A/D Converter (ADC)
6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI interrupt is requested at all times. To generate an interrupt on completing conversion of the third channel, clear the ADF bit to 0 after an interrupt is requested.
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Continuous A/D conversion Set*1 Clear*1
ADST Clear*1
ADF Waiting Waiting Conversion time 1 Conversion time 4 *2 Waiting Waiting Conversion time 2 Conversion time 5 Waiting Waiting
Channel 0 (AN0) operating
Channel 1 (AN1) operating
Channel 2 (AN2) operating Waiting
Conversion time 3
Waiting
Channel 3 (AN3) operating Waiting
ADDRA
A/D conversion result 1
A/D conversion result 4
ADDRB
A/D conversion result 2
ADDRC
A/D conversion result 3
Figure 22.4 Example of A/D Converter Operation (Scan Mode, Three Channels (AN0 to AN2) Selected)
Notes: 1. Vertical arrows ( ) indicate instruction execution by software. 2. A/D conversion data is invalid/
Section 22 A/D Converter (ADC)
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ADDRD
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Section 22 A/D Converter (ADC)
22.4.4
A/D Converter Activation by External Trigger, MTU2, or TMR
The A/D converter can be independently activated by an A/D conversion request from the external trigger, MTU2, or TMR. To activate the A/D converter by the external trigger, MTU2, or TMR, set the A/D trigger enable bits (TRGS[3:0]). After this bit setting has been made, the ADST bit is automatically set to 1 and A/D conversion is started when an A/D conversion request from the external trigger, MTU2, or TMR occurs. The channel combination is determined by the CH[2:0] bits in ADCSR. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 22.4.5 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at the A/D conversion start delay time (tD) after the ADST bit in ADCSR is set to 1, then starts conversion. Figure 22.5 shows the A/D conversion timing. Table 22.4 indicates the A/D conversion time. As indicated in figure 22.5, the A/D conversion time (tCONV) includes tD and the input sampling time(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 22.4. In multi mode and scan mode, the values given in table 22.4 apply to the first conversion. In the second and subsequent conversions, time is the values given in table 22.5.
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Section 22 A/D Converter (ADC)
(1) P
Address
(2)
Write signal
Input sampling timing
ADIF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time
Figure 22.5 A/D Conversion Timing Table 22.4 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. 11 -- 135 Typ. -- 33 -- Max. 14 -- 138 Min. 19 -- 267 CKS0 = 1 Typ. -- 65 -- Max. 26 -- 274 Min. 35 -- 531 CKS1 = 1 CKS0 = 0 Typ. -- 129 -- Max. 50 -- 546
Note: Values in the table are the numbers of states.
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Section 22 A/D Converter (ADC)
Table 22.5 A/D Conversion Time (Multi Mode and Scan Mode)
CKS1 0 CKS0 0 1 1 0 Conversion Time (States) 128 (constant) 256 (constant) 512 (constant)
Note: Values in the table are the numbers of states.
22.4.6
External Trigger Input Timing
A/D conversion can also be externally triggered. When the TRGS[3:0] bits in ADCSR are set to B'1001, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, regardless of the operating mode, are the same as when the ADST bit has been set to 1 by software. Figure 22.6 shows the timing.
P ADTRG Internal trigger signal
ADST
A/D conversion
Figure 22.6 External Trigger Input Timing
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Section 22 A/D Converter (ADC)
22.5
Interrupt Sources and DMAC Transfer Request
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. An ADI interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is set to 1 on completion of A/D conversion. Note that the direct memory access controller (DMAC) can be activated by an ADI interrupt depending on the DMAC setting. In this case, an interrupt is not issued to the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the CPU. Having the converted data read by the DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. In single mode, set the DMAC so that DMA transfer initiated by an ADI interrupt is performed only once. In the case of A/D conversion on multiple channels in scan mode or multi mode, setting the DMA transfer count to one causes DMA transfer to finish after transferring only one channel of data. To make the DMAC transfer all conversion data, set the ADDR where A/D conversion data is stored as the transfer source address, and the number of converted channels as the transfer count. When the DMAC is activated by ADI, the ADF bit in ADCSR is automatically cleared to 0 when data is transferred by the DMAC. Table 22.6 Relationship between Interrupt Sources and DMAC Transfer Request
Name ADI Interrupt Source A/D conversion end Interrupt Flag ADF in ADCSR DMAC Activation Possible
22.6
Definitions of A/D Conversion Accuracy
The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * * * * Offset error Full-scale error Quantization error Nonlinearity error
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Section 22 A/D Converter (ADC)
These four error quantities are explained below with reference to figure 22.7. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) B'0000000000 (000 in the figure) to B'000000001 (001 in the figure) (figure 22.7, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from B'1111111110 (110 in the figure) to the maximum B'1111111111 (111 in the figure) (figure 22.7, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 22.7, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 22.7, item (4)). Note that it does not include offset, full-scale, or quantization error.
(2) Full-scale error
Digital output
Digital output
111 110 101 100 011 010 001 000 0 1 2 1024 1024
Ideal A/D conversion characteristic
Ideal A/D conversion characteristic
(4) Nonlinearity error (3) Quantization error Actual A/D convertion characteristic
FS Analog input voltage
1022 1023 FS 1024 1024 Analog input voltage
(1) Offset error
[Legend] FS: Full-scale voltage
Figure 22.7 Definitions of A/D Conversion Accuracy
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Section 22 A/D Converter (ADC)
22.7
Usage Notes
When using the A/D converter, note the following points. 22.7.1 Module Standby Mode Setting
Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, see section 27, Power-Down Modes. 22.7.2 Setting Analog Input Voltage
Permanent damage to the LSI may result if the following voltage ranges are exceeded. 1. Analog input range During A/D conversion, voltages on the analog input pins ANn should not go beyond the following range: AVss ANn AVcc (n = 0 to 7). 2. AVcc and AVss input voltages Input voltages AVcc and AVss should be PVcc - 0.3 V AVcc PVcc and AVss = PVss. Do not leave the AVcc and AVss pins open when the A/D converter or D/A converter is not in use and in software standby mode. When not in use, connect AVcc to the power supply (PVcc) and AVss to the ground (PVss). 3. Setting range of AVref input voltage Set the reference voltage range of the AVref pin as 3.0 V AVref AVcc. 22.7.3 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference voltage (AVref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (PVss) on the board.
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Section 22 A/D Converter (ADC)
22.7.4
Processing of Analog Input Pins
To prevent damage from voltage surges at the analog input pins (AN0 to AN7), connect an input protection circuit like the one shown in figure 22.8. The circuit shown also includes a CR filter to suppress noise. This circuit is shown as an example; the circuit constants should be selected according to actual application conditions. Figure 22.9 shows an equivalent circuit diagram of the analog input ports and table 22.7 lists the analog input pin specifications.
AVcc AVref *2 *1 *1
0.1 F
Rin
100
This LSI AN0 to AN7 AVss
Notes: Values are reference values. 1.
10 F
0.01 F
2. Rin: Input impedance
Figure 22.8 Example of Analog Input Protection Circuit
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Section 22 A/D Converter (ADC)
3 k AN0 to AN7 To A/D converter
20 pF
Note: Values are reference values.
Figure 22.9 Analog Input Pin Equivalent Circuit Table 22.7 Analog Input Pin Ratings
Item Analog input capacitance Allowable signal-source impedance Min. Max. 20 5 Unit pF k
22.7.5
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with a large capacitance provided externally for A/D conversion in single mode, the input load will essentially comprise only the internal input resistance of 3 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 22.10). When converting a high-speed analog signal, a low-impedance buffer should be inserted.
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Section 22 A/D Converter (ADC)
This LSI Sensor output impedance Up to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 3 k
20 pF
Note: Values are reference values.
Figure 22.10 Example of Analog Input Circuit 22.7.6 Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to connect AVss, etc. to an electrically stable GND. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). 22.7.7 Usage Note when Shifting to Single Mode during A/D Conversion
During the A/D conversion in scan mode or multi mode, if the A/D conversion is stopped by clearing the A/D start bit (ADST) in ADCSR to 0 and restarted after a transition to single mode, make sure to set ASDT to 1 after the time required for one-channel A/D conversion has elapsed.
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Section 23 D/A Converter (DAC)
Section 23 D/A Converter (DAC)
23.1
* * * * * *
Features
Resolution: 8 bits Input channels: 2 Minimum conversion time: Max. 10 s (with 20 pF load) Output voltage: 0 V to AVref D/A output hold function in software standby mode Module standby mode can be set
Peripheral bus
DA0 DA1 AVss
D/A
Control circuit [Legend] DADR0: D/A data register 0 DADR1: D/A data register 1 DACR: D/A control register
Figure 23.1 Block Diagram of D/A Converter
DACR
8-bit
DADR0
DADR1
AVCC AVref
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Bus interface
Module data bus
Section 23 D/A Converter (DAC)
23.2
Input/Output Pins
Table 23.1 shows the pin configuration of the D/A converter. Table 23.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog output pin 0 Analog output pin 1 Symbol AVcc AVss AVref DA0 DA1 I/O Input Input Input Output Output Function Analog block power supply Analog block ground D/A conversion reference voltage Channel 0 analog output Channel 1 analog output
23.3
Register Descriptions
The D/A converter has the following registers. Table 23.2 Register Configuration
Register Name D/A data register 0 D/A data register 1 D/A control register Abbreviation DADR0 DADR1 DACR R/W R/W R/W R/W Initial Value H'00 H'00 H'1F Address H'FFFE6800 H'FFFE6801 H'FFFE6802 Access Size 8, 16 8, 16 8, 16
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Section 23 D/A Converter (DAC)
23.3.1
D/A Data Registers 0 and 1 (DADR0 and DADR1)
DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be performed. Whenever analog output is enabled, the values in DADR are converted and output to the analog output pins. DADR is initialized to H'00 by a power-on reset in deep standby mode or module standby mode.
Bit: 7 6 5 4 3 2 1 0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
23.3.2
D/A Control Register (DACR)
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a power-on reset in deep standby mode or module standby mode.
Bit: 7 6 5
DAE
4 -- 1 --
3 -- 1 --
2 -- 1 --
1 -- 1 --
0 -- 1 --
DAOE1 DAOE0
Initial value: 0 R/W: R/W
0 R/W
0 R/W
Bit 7
Bit Name DAOE1
Initial Value 0
R/W R/W
Description D/A Output Enable 1 Controls D/A conversion and analog output for channel 1. 0: Analog output of channel 1 (DA1) is disabled 1: D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled.
6
DAOE0
0
R/W
D/A Output Enable 0 Controls D/A conversion and analog output for channel 0. 0: Analog output of channel 0 (DA0) is disabled 1: D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.
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Section 23 D/A Converter (DAC)
Bit 5
Bit Name DAE
Initial Value 0
R/W R/W
Description D/A Enable Used together with the DAOE0 and DAOE1 bits to control D/A conversion. Output of conversion results is always controlled by the DAOE0 and DAOE1 bits. For details, see table 23.3. 0: D/A conversion for channels 0 and 1 is controlled independently 1: D/A conversion for channels 0 and 1 is controlled together
4 to 0
All 1
Reserved These bits are always read as 1 and cannot be modified.
Table 23.3 Control of D/A Conversion
Bit 5 DAE 0 Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 1 0 1 1 0 0 1 1 0 1 Description D/A conversion is disabled. D/A conversion of channel 0 is enabled and D/A conversion of channel 1 is disabled. D/A conversion of channel 1 is enabled and D/A conversion of channel 0 is disabled. D/A conversion of channels 0 and 1 is enabled. D/A conversion is disabled. D/A conversion of channels 0 and 1 is enabled.
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Section 23 D/A Converter (DAC)
23.4
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion result is output. An operation example of D/A conversion on channel 0 is shown below. Figure 23.2 shows the timing of this operation. 1. Write the conversion data to DADR0. 2. Set the DAOE0 bit in DACR to 1 to start D/A conversion. The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The output value is expressed by the following formula:
Contents of DADR 256 x AVref
3. If DADR0 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. 4. If the DAOE0 bit is cleared to 0, analog output is disabled.
DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle
Address
DADR0
Conversion data 1
Conversion data 2
DAOE0 Conversion result 2 tDCONV
DA0 High-impedance state [Legend] tDCONV: D/A conversion time tDCONV
Conversion result 1
Figure 23.2 Example of D/A Converter Operation
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Section 23 D/A Converter (DAC)
23.5
23.5.1
Usage Notes
Module Standby Mode Setting
Operation of the D/A converter can be disabled or enabled using the standby control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by canceling module standby mode. For details, see section 27, Power-Down Modes. 23.5.2 D/A Output Hold Function in Software Standby Mode
When this LSI enters software standby mode with D/A conversion enabled, the D/A outputs are retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE0, DAOE1, and DAE bits to 0 to disable the D/A outputs. 23.5.3 D/A Conversion and D/A Output in Deep Standby Mode
When this LSI enters deep standby mode with D/A conversion enabled, the D/A conversion is stopped and thus the D/A outputs are also stopped. Before entering deep standby mode, clear the DAOE0, DAOE1, and DAE bits to 0 to disable the D/A outputs. 23.5.4 Setting Analog Input Voltage
The reliability of this LSI may be adversely affected if the following voltage ranges are exceeded. 1. AVcc and AVss input voltages Input voltages AVcc and AVss should be PVcc - 0.3 V AVcc PVcc and AVss = PVss. Do not leave the AVcc and AVss pins open when the A/D converter or D/A converter is not in use and in software standby mode. When not in use, connect AVcc to the power supply (PVcc) and AVss to the ground (PVss). 2. Setting range of AVref input voltage Set the reference voltage range of the AVref pin as 3.0 V AVref AVcc.
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Section 24 I/O Ports
Section 24 I/O Ports
This LSI has six ports: A to F. All port pins are multiplexed with other pin functions. The functions of the multiplexed pins are selected using the pin function controller (PFC). Each port is provided with a data register for storing the pin data and a port read register for reading out the pin values.
24.1
Port A
Port A is an I/O port with 32 pins shown in figure 24.1.
PA31 (I/O) / CRx1 (Input) / DTEND0 (Output) PA30 (I/O) / CTx1 (Output) / DACT0 (Output) PA29 (I/O) / CRx0 (Input) / DACK0 (Output) PA28 (I/O) / CTx0 (Output) / DREQ0 (Input) PA27 (I/O) / A27 (Output) / PINT3 (Input) / DTEND3 (Output) PA26 (I/O) / A26 (Output) / PINT2 (Input) / DACT3 (Output) PA25 (I/O) / A25 (Output) / PINT1 (Input) / DACK3 (Output) PA24 (I/O) / A24 (Output) / PINT0 (Input) / DREQ3 (Input) PA23 (I/O) / A23 (Output) PA22 (I/O) / A22 (Output) PA21 (I/O) / A21 (Output) PA20 (I/O) / A20 (Output) PA19 (I/O) / A19 (Output) PA18 (I/O) / A18 (Output) PA17 (I/O) / A17 (Output) PA16 (I/O) / A16 (Output) PA15 (I/O) / A15 (Output) PA14 (I/O) / A14 (Output) PA13 (I/O) / A13 (Output) PA12 (I/O) / A12 (Output) PA11 (I/O) / A11 (Output) PA10 (I/O) / A10 (Output) PA9 (I/O) / A9 (Output) PA8 (I/O) / A8 (Output) PA7 (I/O) / A7 (Output) PA6 (I/O) / A6 (Output) PA5 (I/O) / A5 (Output) PA4 (I/O) / A4 (Output) PA3 (I/O) / A3 (Output) PA2 (I/O) / A2 (Output) PA1 (I/O) / A1 (Output) PA0 (I/O) / A0 (Output)
Port A
Figure 24.1 Port A
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Section 24 I/O Ports
24.1.1
Register Configuration
Table 24.1 lists the port A registers. Table 24.1 Register Configuration
Register Name Port A data register H Port A data register L Port A port register H Port A port register L Abbreviation PADRH PADRL PAPRH PAPRL R/W R/W R/W R R Address H'FFFE3800 H'FFFE3802 H'FFFE3804 H'FFFE3806 Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16
24.1.2
Port A Data Registers H and L (PADRH and PADRL)
PADRH and PADRL are 16-bit readable/writable registers that store port A data. Bits PA31DR to PA0DR correspond to pins PA31 to PA0, respectively. If a pin is set to the general output function, the pin will output the value written to the corresponding bit in PADRH or PADRL, and the register value is read from PADRH or PADRL regardless of the state of the pin. If a pin is set to the general input function, the pin state, not the register value, will be returned if PADRH or PADRL is read. Also, if a value is written to PADRH or PADRL, although the value will actually be written, it will have no influence on the state of the pin. Table 24.2 summarizes the PADRH and PADRL read/write operations. PADRH and PADRL are initialized to H'0000 by a power-on reset or in deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode.
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Section 24 I/O Ports
* Port A Data Register H (PADRH)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value: 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit:
* Port A Data Register L (PADRL)
Bit: 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 DR DR DR DR DR DR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 PA9 DR 0 R/W 8 PA8 DR 0 R/W 7 PA7 DR 0 R/W 6 PA6 DR 0 R/W 5 PA5 DR 0 R/W 4 PA4 DR 0 R/W 3 PA3 DR 0 R/W 2 PA2 DR 0 R/W 1 PA1 DR 0 R/W 0 PA0 DR 0 R/W
Initial value: 0 R/W: R/W
Table 24.2 Port A Data Registers H and L (PADRH and PADRL) Read/Write Operations
PAIORH, PAIORL 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state Value of PADRH and PADRL Value of PADRH and PADRL Write The value is written to PADRH and PADRL but there is no effect on the pin state. The value is written to PADRH and PADRL but there is no effect on the pin state. The value written is output from the pin.
Other than general output
The value is written to PADRH and PADRL but there is no effect on the pin state.
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Section 24 I/O Ports
24.1.3
Port A Port Registers H and L (PAPRH and PAPRL)
PAPRH and PAPRL are 16-bit read-only registers in which bits PA31PR to PA0PR correspond to pins PA31 to PA0. PAPRH and PAPRL are always read as the states of the pins regardless of the PFC setting. * Port A Port Register H (PAPRH)
0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 R R R R R R R R R R R R R R R R/W: R Bit:
* Port A Port Register L (PAPRL)
Bit: 15 14 13 12 11 10 PA15 PA14 PA13 PA12 PA11 PA10 PR PR PR PR PR PR 9 PA9 PR PA9 R 8 PA8 PR PA8 R 7 PA7 PR PA7 R 6 PA6 PR PA6 R 5 PA5 PR PA5 R 4 PA4 PR PA4 R 3 PA3 PR PA3 R 2 PA2 PR PA2 R 1 PA1 PR PA1 R 0 PA0 PR PA0 R
Initial value: PA15 PA14 PA13 PA12 PA11 PA10 R/W: R R R R R R
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Section 24 I/O Ports
24.2
Port B
Port B is an I/O port with 32 pins shown in figure 24.2.
PB31 (I/O) / D31 (I/O) / PINT7 (Input) PB30 (I/O) / D30 (I/O) / PINT6 (Input) / TMCI0 (Input) / SCK3 (I/O) PB29 (I/O) / D29 (I/O) / PINT5 (Input) / TMRI0 (Input) / RxD3 (Input) PB28 (I/O) / D28 (I/O) / PINT4 (Input) / TMO0 (Output) / TxD3 (Output) PB27 (I/O) / D27 (I/O) / PINT3 (Input) PB26 (I/O) / D26 (I/O) / PINT2 (Input) / TIC5W (I/O) / SCK6 (I/O) PB25 (I/O) / D25 (I/O) / PINT1 (Input) / TIC5V (I/O) / RxD6 (Input) PB24 (I/O) / D24 (I/O) / PINT0 (Input) / TIC5U (I/O) / TxD6 (Output) PB23 (I/O) / D23 (I/O) / IRQ7 (Input) / TIOC4D (I/O) PB22 (I/O) / D22 (I/O) / IRQ6 (Input) / TIOC4C (I/O) / SCK2 (I/O) PB21 (I/O) / D21 (I/O) / IRQ5 (Input) / TIOC4B (I/O) / RxD2 (Input) PB20 (I/O) / D20 (I/O) / IRQ4 (Input) / TIOC4A (I/O) / TxD2 (Output) PB19 (I/O) / D19 (I/O) / IRQ3 (Input) / TIOC3D (I/O) PB18 (I/O) / D18 (I/O) / IRQ2 (Input) / TIOC3C (I/O) PB17 (I/O) / D17 (I/O) / IRQ1 (Input) / TIOC3B (I/O) PB16 (I/O) / D16 (I/O) / IRQ0 (Input) / TIOC3A (I/O) PB15 (I/O) / D15 (I/O) PB14 (I/O) / D14 (I/O) PB13 (I/O) / D13 (I/O) PB12 (I/O) / D12 (I/O) PB11 (I/O) / D11 (I/O) PB10 (I/O) / D10 (I/O) PB9 (I/O) / D9 (I/O) PB8 (I/O) / D8 (I/O) PB7 (I/O) / D7 (I/O) PB6 (I/O) / D6 (I/O) PB5 (I/O) / D5 (I/O) PB4 (I/O) / D4 (I/O) PB3 (I/O) / D3 (I/O) PB2 (I/O) / D2 (I/O) PB1 (I/O) / D1 (I/O) PB0 (I/O) / D0 (I/O)
Port B
Figure 24.2 Port B
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Section 24 I/O Ports
24.2.1
Register Configuration
Table 24.3 lists the port B registers. Table 24.3 Register Configuration
Register Name Port B data register H Port B data register L Port B port register H Port B port register L Abbreviation PBDRH PBDRL PBPRH PBPRL R/W R/W R/W R R Address H'FFFE3808 H'FFFE380A H'FFFE380C H'FFFE380E Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16
24.2.2
Port B Data Registers H and L (PBDRH and PBDRL)
PBDRH and PBDRL are 16-bit readable/writable registers that store port B data. Bits PB31DR to PB0DR correspond to pins PB31 to PB0, respectively. If a pin is set to the general output function, the pin will output the value written to the corresponding bit in PBDRH or PBDRL, and the register value is read from PBDRH or PBDRL regardless of the state of the pin. If a pin is set to the general input function, the pin state, not the register value, will be returned if PBDRH or PBDRL is read. Also, if a value is written to PBDRH or PBDRL, although the value will actually be written, it will have no influence on the state of the pin. Table 24.4 summarizes the PBDRH and PBDRL read/write operations. PBDRH and PBDRL are initialized to H'0000 by a power-on reset or in deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode.
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Section 24 I/O Ports
* Port B data register H (PBDRH)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value: 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit:
* Port B data register L (PBDRL)
Bit: 15 14 13 12 11 10 9 8 PB8 DR 0 R/W 7 PB7 DR 0 R/W 6 PB6 DR 0 R/W 5 PB5 DR 0 R/W 4 PB4 DR 0 R/W 3 PB3 DR 0 R/W 2 PB2 DR 0 R/W 1 PB1 DR 0 R/W 0 PB0 DR 0 R/W
PB15 PB14 PB13 PB12 PB11 PB10 PB9 DR DR DR DR DR DR DR 0 0 0 0 0 0 Initial value: 0 R/W: R/W R/W R/W R/W R/W R/W R/W
Table 24.4 Port B Data Registers H and L (PBDRH and PBDRL) Read/Write Operations
PBIORH, L 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state Value of PBDRH and PBDRL Value of PBDRH and PBDRL Write The value is written to PBDRH and PBDRL but there is no effect on the pin state. The value is written to PBDRH and PBDRL but there is no effect on the pin state. The value written is output from the pin.
Other than general output
The value is written to PBDRH and PBDRL but there is no effect on the pin state.
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Section 24 I/O Ports
24.2.3
Port B Port Registers H and L (PBPRH and PBPRL)
PBPRH and PBPRL are 16-bit read-only registers in which bits PB31PR to PB0PR correspond to pins PB31 to PB0. PBPRH and PBPRL are always read the states of the pins regardless of the PFC setting. * Port B Port Register H (PBPRH)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR Initial value: PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 R/W: R R R R R R R R R R R R R R R R
* Port B Port Register L (PBPRL)
Bit: 15 14 13 12 11 10 9 8 PB8 PR PB8 R 7 PB7 PR PB7 R 6 PB6 PR PB6 R 5 PB5 PR PB5 R 4 PB4 PR PB4 R 3 PB3 PR PB3 R 2 PB2 PR PB2 R 1 PB1 PR PB1 R 0 PB0 PR PB0 R
PB15 PB14 PB13 PB12 PB11 PB10 PB9 PR PR PR PR PR PR PR Initial value: PB15 PB14 PB13 PB12 PB11 PB10 PB9 R/W: R R R R R R R
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Section 24 I/O Ports
24.3
Port C
Port C is an I/O port with 26 pins and is shown in figure 24.3.
PC25 (Input) / IRQ3 (Input) / SDA1 (I/O) PC24 (Input) / IRQ2 (Input) / SCL1 (I/O) PC23 (Input) / IRQ1 (Input) / SDA0 (I/O) PC22 (Input) / IRQ0 (Input) / SCL0 (I/O) / DREQ2 (Input) PC21 (I/O) / BC3(Output) /DQM3 (Output) / TCLKC (Input) / DACK2 (Output) PC20 (I/O) / BC2(Output) /DQM2 (Output) / TCLKB (Input) PC19 (I/O) / BC1(Output) /DQM1 (Output) PC18 (I/O) / BC0(Output) /DQM0 (Output) PC17 (I/O) / SDWE (Output) PC16 (I/O) / SDCAS (Output) PC15 (I/O) / SDRAS (Output) PC14 (I/O) / SDCKE (Output) PC13 (I/O) / WAIT (Input) PC12 (I/O) / WR3 (Output) / WR (Output) / TIOC2B (I/O)/ DTEND2 (Output) PC11 (I/O) / WR2 (Output) / TIOC2A (I/O) / DACT2 (Output) PC10 (I/O) / WR1 (Output) / WR (Output) PC9 (I/O) / WR0 (Output) / WR (Output) PC8 (I/O) / RD (Output) PC7 (I/O) / SDCS0 (Output) PC6 (I/O) / CS6 (Output) / TCLKA (Input) / SCK5 (I/O) PC5 (I/O) / CS5 (Output) / TIOC1B (I/O) / RxD5 (Input) PC4 (I/O) / CS4 (Output) / TIOC1A (I/O) / TxD5 (Output) PC3 (I/O) / CS3 (Output) / UBCTRG (Output) PC2 (I/O) / CS2 (Output) / SDCS1 (Output) / ADTRG (Input) PC1 (I/O) / CS1 (Output) PC0 (I/O) / CS0 (Output)
Port C
Figure 24.3 Port C 24.3.1 Register Configuration
Table 24.5 lists the port C registers. Table 24.5 Register Configuration
Register Name Port C data register H Port C data register L Port C port register H Port C port register L Abbreviation PCDRH PCDRL PCPRH PCPRL R/W R/W R/W R R Address H'FFFE3810 H'FFFE3812 H'FFFE3814 H'FFFE3816 Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16
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Section 24 I/O Ports
24.3.2
Port C Data Registers H and L (PCDRH and PCDRL)
PCDRH and PCDRL are 16-bit readable/writable registers that store port C data. Bits PC21DR to PC0DR correspond to pins PC21 to PC0, respectively. If a pin is set to the general output function, the pin will output the value written to the corresponding bit in PCDRH or PCDRL, and the register value is read from PCDRH and PCDRL regardless of the state of the pin. If a pin is set to the general input function, the pin state, not the register value, will be returned if PCDRH or PCDRL is read. Also, if a value is written to PCDRH or PCDRL, although the value will actually be written, it will have no influence on the state of the pin. Table 24.6 summarizes the PCDRH and PCDRL read/write operations. Bits 15 to 6 in PCDRH are reserved. These bits are read as 0. The write value should always be 0. PCDRH and PCDRL are initialized to H'0000 by a power-on reset or in deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. * Port C data register H (PCDRH)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 4 3 2 1 0
PC21 PC20 PC19 PC18 PC17 PC16 DR DR DR DR DR DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W
* Port C data register L (PCDRL)
15 14 13 12 11 10 9 PC15 PC14 PC13 PC12 PC11 PC10 PC9 DR DR DR DR DR DR DR 0 0 0 0 0 0 Initial value: 0 R/W: R/W R/W R/W R/W R/W R/W R/W Bit: 8 PC8 DR 0 R/W 7 PC7 DR 0 R/W 6 PC6 DR 0 R/W 5 PC5 DR 0 R/W 4 PC4 DR 0 R/W 3 PC3 DR 0 R/W 2 PC2 DR 0 R/W 1 PC1 DR 0 R/W 0 PC0 DR 0 R/W
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Section 24 I/O Ports
Table 24.6 Port C Data Registers H and L (PCDRH and PCDRL) Read/Write Operations
PCIORH, PCIORL 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state Value of PCDRH and PCDRL Value of PCDRH and PCDRHL Write The value is written to PCDRH and PCDRL but there is no effect on the pin state. The value is written to PCDRH and PCDRL but there is no effect on the pin state. The value written is output from the pin.
Other than general output
The value is written to PCDRH and PCDRL but there is no effect on the pin state.
24.3.3
Port C Port Registers H and L (PCPRH and PCPRL)
PCPRH and PCPRL are 16-bit read-only registers in which bits PC25PR to PC0PR correspond to pins PC25 to PC0. PCPRH and PCPRL are always read as the states of the pins regardless of the PFC setting. Bits 15 to 10 in PCPRH are reserved. These bits are read as 0. The write value should always be 0. * Port C Port Register H (PCPRH)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 8 7 6 5 4 3 2 1 0
PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PR PR PR PR PR PR PR PR PR PR PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 R R R R R R R R R R
* Port C Port Register L (PCPRL)
Bit: 15 14 13 12 11 10 9 8 PC8 PR PC8 R 7 PC7 PR PC7 R 6 PC6 PR PC6 R 5 PC5 PR PC5 R 4 PC5 PR PC5 R 3 PC3 PR PC3 R 2 PC2 PR PC2 R 1 PC1 PR PC1 R 0 PC0 PR PC0 R
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PR PR PR PR PR PR PR Initial value: PC15 PC14 PC13 PC12 PC11 PC10 PC9 R/W: R R R R R R R
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Section 24 I/O Ports
24.4
Port D
Port D is an I/O port with 17 pins shown in figure 24.4.
PD16 (Input) / SCL2 (I/O) PD15 (Input) / SDA2 (I/O) PD14 (I/O) / IERxD (Input) / DACK1 (Output) PD13 (I/O) / IETxD (Output) / DREQ1 (Input) PD12 (I/O) / TMCI1 (Input) / SCK1 (I/O) PD11 (I/O) / TMRI1 (Input) / RxD1 (Input) PD10 (I/O) / TMO1 (Output) / TIOC0D (I/O) / TxD1 (Output) PD9 (I/O) / TIOC0C (I/O) / SCK0 (I/O) PD8 (I/O) / TIOC0B (I/O) / RxD0 (Input) / DTEND1 (Output) PD7 (I/O) / TIOC0A (I/O) / TxD0 (Output) / DACT1 (Output) PD6 (I/O) / SCK4 (I/O) / SSIWS1 (I/O) PD5 (I/O) / RxD4 (Input) / SSISCK1 (I/O) PD4 (I/O) / TxD4 (Output) / SSIDATA1 (I/O) PD3 (I/O) / SSIWS0 (I/O) PD2 (I/O) / SSISCK0 (I/O) PD1 (I/O) / SSIDATA0 (I/O) PD0 (I/O) / AUDIO_CLK (Input)
Port D
Figure 24.4 Port D 24.4.1 Register Configuration
Table 24.7 lists the port D registers. Table 24.7 Register Configuration
Register Name Port D data register Port D port register H Port D port register L Abbreviation PDDR PDPRH PDPRL R/W R/W R R Address H'FFFE381A H'FFFE381C H'FFFE381E Access Size 8, 16 8, 16, 32 8, 16
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Section 24 I/O Ports
24.4.2
Port D Data Register (PDDR)
PDDR is a 16-bit readable/writable register that stores port D data. Bits PD14DR to PD0DR correspond to pins PD14 to PD0, respectively. If a pin is set to the general output function, that pin will output the value written to the corresponding bit in PDDR, and the register value is read from PDDR regardless of the state of the pin. If a pin is set to the general input function, the pin state, not the register value, will be returned if PDDR is read. Also, if a value is written to PDDR, although the value will actually be written, it will have no influence on the state of the pin. Table 24.8 summarizes the PDDR read/write operations. Bit 15 in PDDR is reserved. This bit is read as 0. The write value should always be 0. PDDR is initialized to H'0000 by a power-on reset or in deep standby mode. This register is not initialized either by a manual reset or by switching to sleep mode or software standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 13 12 11 10 9 8 PD8 DR 0 R/W 7 PD7 DR 0 R/W 6 PD6 DR 0 R/W 5 PD5 DR 0 R/W 4 PD4 DR 0 R/W 3 PD3 DR 0 R/W 2 PD2 DR 0 R/W 1 PD1 DR 0 R/W 0 PD0 DR 0 R/W
PD14 PD13 PD12 PD11 PD10 PD9 DR DR DR DR DR DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W
Table 24.8 Port D Data Register (PDDR) Read/Write Operations
PDIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state Value of PDDR Value of PDDR Write The value is written to PDDR but there is no effect on the pin state. The value is written to PDDR but there is no effect on the pin state. The value written is output from the pin. The value is written to PDDR but there is no effect on the pin state.
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Section 24 I/O Ports
24.4.3
Port D Port Registers H and L (PDPRH and PDPRL)
PDPRH and PDPRL are 16-bit read-only registers in which bits PD16PR to PD0PR correspond to pins PD16 to PD0. PDPRH and PDPRL are always read as the states of the pins regardless of the PFC setting. Bits 15 to 1 in PDPRH are reserved. These bits are read as 0. The write value should always be 0. * Port D Port Register H (PDPRH)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PD16 PR PD16 R
* Port D Port Register L (PDPRL)
Bit: 15 14 13 12 11 10 9 8 PD8 DR PD8 R 7 PD7 DR PD7 R 6 PD6 DR PD6 R 5 PD5 DR PD5 R 4 PD4 DR PD4 R 3 PD3 DR PD3 R 2 PD2 DR PD2 R 1 PD1 DR PD1 R 0 PD0 DR PD0 R
PD15 PD14 PD13 PD12 PD11 PD10 PD9 DR DR DR DR DR DR DR Initial value: PD15 PD14 PD13 PD12 PD11 PD10 PD9 R/W: R R R R R R R
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Section 24 I/O Ports
24.5
Port E
Port E is an I/O port with 8 pins shown in figure 24.5.
PE7 (Input) / IRQ7 (Input) / AN7 (Input) / DA1 (Output) PE6 (Input) / IRQ6 (Input) / AN6 (Input) / DA0 (Output) PE5 (Input) / IRQ5 (Input) / AN5 (Input) PE4 (Input) / IRQ4 (Input) / AN4 (Input) PE3 (Input) / PINT7 (Input) / AN3 (Input) PE2 (Input) / PINT6 (Input) / AN2 (Input) PE1 (Input) / PINT5 (Input) / AN1 (Input) PE0 (Input) / PINT4 (Input) / AN0 (Input)
Port E
Figure 24.5 Port E 24.5.1 Register Configuration
Table 24.9 lists the port E registers. Table 24.9 Register Configuration
Register Name Port E port register Abbreviation PEPR R/W R Address H'FFFE3826 Access Size 8, 16
24.5.2
Port E Port Register (PEPR)
PEPR is a 16-bit read-only register. Bits PE7PR to PE0PR correspond to pins PE7 to PE0, respectively. The pin values can always be read from PEPR, regardless of the PFC settings.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 PE7 PR PE7 R 6 PE6 PR PE6 R 5 PE5 PR PE5 R 4 PE4 PR PE4 R 3 PE3 PR PE3 R 2 PE2 PR PE2 R 1 PE1 PR PE1 R 0 PE0 PR PE0 R
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Section 24 I/O Ports
24.6
Port F
Port F is an I/O port with 8 pins shown in figure 24.6.
PF7 (I/O) / AUDATA3 (I/O) PF6 (I/O) / AUDATA2 (I/O) PF5 (I/O) / AUDATA1 (I/O) PF4 (I/O) / AUDATA0 (I/O) PF3 (I/O) / AUDSYNC (I/O) PF2 (I/O) / TCLKD (Input) / SCK7 (I/O) / AUDCK (Input) PF1 (I/O) / RxD7 (Input) / AUDMD (Input) PF0 (I/O) / TxD7 (Output) / AUDRST (Input)
Port F
Figure 24.6 Port F 24.6.1 Register Configuration
Table 24.10 lists the port F registers. Table 24.10 Register Configuration
Register Name Port F data register Port F port register Abbreviation PFDR PFPR R/W R/W R Address H'FFFE382A H'FFFE382E Access Size 8, 16 8, 16
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Section 24 I/O Ports
24.6.2
Port F Data Register (PFDR)
PFDR is a 16-bit read-only register that stores the port F data. Bits PF7DR to PF0DR correspond to pins PF7 to PF0, respectively. If a pin is set to the general output function, the pin will output the value written to the corresponding bit in PFDR, and the register value is read from PFDR regardless of the state of the pin. If a pin is set to the general input function, the pin state, not the register value, will be returned if PFDR is read. Also, if a value is written to PFDR, although the value will actually be written, it will have no influence on the state of the pin. Table 24.11 summarizes the PFDR read/write operations. PFDR is initialized to H'0000 by a power-on reset or in deep standby mode. This register is not initialized either by a manual reset or by switching to sleep mode or software standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 PF7 DR 0 R/W 6 PF6 DR 0 R/W 5 PF5 DR 0 R/W 4 PF4 DR 0 R/W 3 PF3 DR 0 R/W 2 PF2 DR 0 R/W 1 PF1 DR 0 R/W 0 PF0 DR 0 R/W
Table 24.11 Port F Data Register (PFDR) Read/Write Operations
PFIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state Value of PFDR Value of PFDR Write The value is written to PFDR but there is no effect on the pin state. The value is written to PFDR but there is no effect on the pin state. The value written is output from the pin. The value is written to PFDR but there is no effect on the pin state.
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Section 24 I/O Ports
24.6.3
Port F Port Register (PFPR)
PFPR is a 16-bit read-only register in which bits PF7PR to PF0PR correspond to pins PF7 to PF0. PFPR are always read as the states of the pins regardless of the PFC setting.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 PF7 PR PF7 R 6 PF6 PR PF6 R 5 PF5 PR PF5 R 4 PF4 PR PF4 R 3 PF3 PR PF3 R 2 PF2 PR PF2 R 1 PF1 PR PF1 R 0 PF0 PR PF0 R
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Section 25 Pin Function Controller (PFC)
Section 25 Pin Function Controller (PFC)
The pin function controller (PFC) consists of registers that select the functions of the multiplexed pins and their I/O directions. Tables 25.1 to 25.6 list the multiplexed pins of this LSI. Table 25.1 Multiplexed Pin Table (Port A)
Function 1 PAnMD[2:0] = 000 Function 2 PAnMD[2:0] = 001 (Related modules) Function 3 PAnMD[2:0] = 010 (Related modules) Function 4 PAnMD[2:0] = 011 (Related modules) Function 5 PAnMD[2:0] = 100 (Related modules)
Port (Related modules) A PA31 I/O (Port) PA30 I/O (Port) PA29 I/O (Port) PA28 I/O (Port) PA27 I/O (Port) PA26 I/O (Port) PA25 I/O (Port) PA24 I/O (Port) PA23 I/O (Port) PA22 I/O (Port) PA21 I/O (Port) PA20 I/O (Port) PA19 I/O (Port) PA18 I/O (Port) PA17 I/O (Port) PA16 I/O (Port) PA15 I/O (Port) PA14 I/O (Port)
CRx1 input (RCAN-ET) CTx1 output (RCAN-ET) CRx0 input (RCAN-ET) CTx0 output (RCAN-ET) A27 output (BSC) A26 output (BSC) A25 output (BSC) A24 output (BSC) A23 output (BSC) A22 output (BSC) A21 output (BSC) A20 output (BSC) A19 output (BSC) A18 output (BSC) A17 output (BSC) A16 output (BSC) A15 output (BSC) A14 output (BSC)
DTEND0 output (DMAC) DACT0 output (DMAC) DACK0 output (DMAC) DREQ0 input (DMAC) DTEND3 output (DMAC) DACT3 output (DMAC) DACK3 output (DMAC) DREQ3 input (DMAC) PINT3B input (INTC) PINT2B input (INTC) PINT1B input (INTC) PINT0B input (INTC)
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Section 25 Pin Function Controller (PFC)
Function 1 PAnMD[2:0] = 000
Function 2 PAnMD[2:0] = 001 (Related modules)
Function 3 PAnMD[2:0] = 010 (Related modules)
Function 4 PAnMD[2:0] = 011 (Related modules)
Function 5 PAnMD[2:0] = 100 (Related modules)
Port (Related modules) A PA13 I/O (Port) PA12 I/O (Port) PA11 I/O (Port) PA10 I/O (Port) PA9 I/O (Port) PA8 I/O (Port) PA7 I/O (Port) PA6 I/O (Port) PA5 I/O (Port) PA4 I/O (Port) PA3 I/O (Port) PA2 I/O (Port) PA1 I/O (Port) PA0 I/O (Port)
A13 output (BSC) A12 output (BSC) A11 output (BSC) A10 output (BSC) A9 output (BSC) A8 output (BSC) A7 output (BSC) A6 output (BSC) A5 output (BSC) A4 output (BSC) A3 output (BSC) A2 output (BSC) A1 output (BSC) A0 output (BSC)
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Section 25 Pin Function Controller (PFC)
Table 25.2 Multiplexed Pin Table (Port B)
Function 1 PBnMD[2:0] = 000 Function 2 PBnMD[2:0] = 001 (Related modules) Function 3 PBnMD[2:0] = 010 (Related modules) Function 4 PBnMD[2:0] = 011 (Related modules) Function 5 PBnMD[2:0] = 100 (Related modules)
Port (Related modules) B PB31 I/O (Port) PB30 I/O (Port) PB29 I/O (Port) PB28 I/O (Port) PB27 I/O (Port) PB26 I/O (Port) PB25 I/O (Port) PB24 I/O (Port) PB23 I/O (Port) PB22 I/O (Port) PB21 I/O (Port) PB20 I/O (Port) PB19 I/O (Port) PB18 I/O (Port) PB17 I/O (Port) PB16 I/O (Port)
D31 I/O (BSC) D30 I/O (BSC) D29 I/O (BSC) D28 I/O (BSC) D27 I/O (BSC) D26 I/O (BSC) D25 I/O (BSC) D24 I/O (BSC) D23 I/O (BSC) D22 I/O (BSC) D21 I/O (BSC) D20 I/O (BSC) D19 I/O (BSC) D18 I/O (BSC) D17 I/O (BSC) D16 I/O (BSC)
PINT7A input (INTC) PINT6A input (INTC) PINT5A input (INTC) PINT4A input (INTC) PINT3A input (INTC) PINT2A input (INTC) PINT1A input (INTC) PINT0A input (INTC) TIC5W input (MTU2) TIC5V input (MTU2) TIC5U input (MTU2) SCK6 I/O (SCIF) RxD6 input (SCIF) TxD6 output (SCIF) SCK3 I/O (SCIF) RxD3 input (SCIF) TMCI0 input (TMR) TMRI0 input (TMR)
TxD3 output (SCIF) TMO0 output (TMR)
IRQ7A input (INTC) TIOC4D I/O (MTU2) IRQ6A input (INTC) TIOC4C I/O (MTU2) IRQ5A input (INTC) TIOC4B I/O (MTU2) IRQ4A input (INTC) TIOC4A I/O (MTU2) IRQ3A input (INTC) TIOC3D I/O (MTU2) IRQ2A input (INTC) TIOC3C I/O (MTU2) IRQ1A input (INTC) TIOC3B I/O (MTU2) IRQ0A input (INTC) TIOC3A I/O (MTU2) SCK2 I/O (SCIF) RxD2 input (SCIF) TxD2 output (SCIF)
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Section 25 Pin Function Controller (PFC)
Function 1 PBnMD[2:0] = 000
Function 2 PBnMD[2:0] = 001 (Related modules)
Function 3 PBnMD[2:0] = 010 (Related modules)
Function 4 PBnMD[2:0] = 011 (Related modules)
Function 5 PBnMD[2:0] = 100 (Related modules)
Port (Related modules) B PB15 I/O (Port) PB14 I/O (Port) PB13 I/O (Port) PB12 I/O (Port) PB11 I/O (Port) PB10 I/O (Port) PB9 I/O (Port) PB8 I/O (Port) PB7 I/O (Port) PB6 I/O (Port) PB5 I/O (Port) PB4 I/O (Port) PB3 I/O (Port) PB2 I/O (Port) PB1 I/O (Port) PB0 I/O (Port)
D15 I/O (BSC) D14 I/O (BSC) D13 I/O (BSC) D12 I/O (BSC) D11 I/O (BSC) D10 I/O (BSC) D9 I/O (BSC) D8 I/O (BSC) D7 I/O (BSC) D6 I/O (BSC) D5 I/O (BSC) D4 I/O (BSC) D3 I/O (BSC) D2 I/O (BSC) D1 I/O (BSC) D0 I/O (BSC)
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Section 25 Pin Function Controller (PFC)
Table 25.3 Multiplexed Pin Table (Port C)
Function 1 PCnMD[2:0] = 000 Function 2 PCnMD[2:0] = 001 (Related modules) Function 3 PCnMD[2:0] = 010 (Related modules) Function 4 PCnMD[2:0] = 011 (Related modules) Function 5 PCnMD[2:0] = 100 (Related modules)
Port (Related modules) C PC25 input (Port) PC24 input (Port) PC23 input (Port) PC22 input (Port) PC21 I/O (Port) PC20 I/O (Port) PC19 I/O (Port) PC18 I/O (Port) PC17 I/O (Port) PC16 I/O (Port) PC15 I/O (Port) PC14 I/O (Port) PC13 I/O (Port) PC12 I/O (Port) PC11 I/O (Port) PC10 I/O (Port)
IRQ3B input (INTC) IRQ2B input (INTC) IRQ1B input (INTC) IRQ0B input (INTC) BC3/DQM3 output (BSC) BC2/DQM2 output (BSC) BC1/DQM1 output (BSC) BC0/DQM0 output (BSC) SDWE output (BSC) SDCAS output (BSC) SDRAS output (BSC) SDCKE output (BSC) WAIT input (BSC) WR3 output (BSC) WR2 output (BSC) WR1 output (BSC) TIOC2B I/O (MTU2) TIOC2A I/O (MTU2) DREQ2 input (DMAC) TCLKC input (MTU2) TCLKB input (MTU2)
SDA1 I/O (IIC3) SCL1 I/O (IIC3) SDA0 I/O (IIC3) SCL0 I/O (IIC3) DACK2 output (DMAC)
DTEND2 output (DMAC) DACT2 output (DMAC)
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Section 25 Pin Function Controller (PFC)
Function 1 PCnMD[2:0] = 000
Function 2 PCnMD[2:0] = 001 (Related modules)
Function 3 PCnMD[2:0] = 010 (Related modules)
Function 4 PCnMD[2:0] = 011 (Related modules)
Function 5 PCnMD[2:0] = 100 (Related modules)
Port (Related modules) C PC9 I/O (Port) PC8 I/O (Port) PC7 I/O (Port) PC6 I/O (Port) PC5 I/O (Port) PC4 I/O (Port) PC3 I/O (Port) PC2 I/O (Port) PC1 I/O (Port) PC0 I/O (Port)
WR0 output (BSC) RD output (BSC) SDCS0 output (BSC) CS6 output (BSC) CS5 output (BSC) CS4 output (BSC) CS3 output (BSC) CS2 output (BSC) CS1 output (BSC) CS0 output (BSC) SCK5 I/O (SCIF) RxD5 input (SCIF) TCLKA input (MTU2) TIOC1B I/O (MTU2)
TxD5 output (SCIF) TIOC1A I/O (MTU2) UBCTRG output (UBC) SDCS1 output (BSC) ADTRG input (A/D)
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Section 25 Pin Function Controller (PFC)
Table 25.4 Multiplexed Pin Table (Port D)
Function 1 PDnMD[2:0] = 000 Function 2 PDnMD[2:0] = 001 (Related modules) Function 3 PDnMD[2:0] = 010 (Related modules) Function 4 PDnMD[2:0] = 011 (Related modules) Function 5 PDnMD[2:0] = 100 (Related modules)
Port (Related modules) D PD16 input (Port) PD15 input (Port) PD14 I/O (Port) PD13 I/O (Port) PD12 I/O (Port) PD11 I/O (Port) PD10 I/O (Port) PD9 I/O (Port) PD8 I/O (Port) PD7 I/O (Port) PD6 I/O (Port) PD5 I/O (Port) PD4 I/O (Port) PD3 I/O (Port) PD2 I/O (Port) PD1 I/O (Port) PD0 I/O (Port)
SCL2 I/O (IIC3) SDA2 I/O (IIC3) IERxD input (IEB) DACK1 output (DMAC)
IETxD output (IEB) DREQ1 input (DMAC) SCK1 I/O (SCIF) RxD1 input (SCIF) TMCI1 input (TMR) TMRI1 input (TMR) TIOC0D I/O (MTU2) TIOC0C I/O (MTU2) DTEND1 output (DMAC) TIOC0B I/O (MTU2) TIOC0A I/O (MTU2)
TxD1 output (SCIF) TMO1 output (TMR) SCK0 I/O (SCIF) RxD0 input (SCIF)
TxD0 output (SCIF) DACT1 output (DMAC) SSIWS1 I/O (SSI) SCK4 I/O (SCIF)
SSISCK1 I/O (SSI) RxD4 input (SCIF) SSIDATA1 I/O (SSI) SSIWS0 I/O (SSI) SSISCK0 I/O (SSI) SSIDATA0 I/O (SSI) AUDIO_CLK input (SSI) TxD4 output (SCIF)
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Section 25 Pin Function Controller (PFC)
Table 25.5 Multiplexed Pin Table (Port E)
Function 1 PEnMD[2:0] = 000 Function 2 PEnMD[2:0] = 001 Function 3 PEnMD[2:0] = 010 (Related modules) Function 4 PEnMD[2:0] = 011 (Related modules) Function 5 PEnMD[2:0] = 100 (Related modules)
Port (Related modules) (Related modules) E PE7 input (Port) PE6 input (Port) PE5 input (Port) PE4 input (Port) PE3 input (Port) PE2 input (Port) PE1 input (Port) PE0 input (Port) IRQ7B input (INTC) IRQ6B input (INTC) IRQ5B input (INTC) IRQ4B input (INTC) PINT7B input (INTC) PINT6B input (INTC) PINT5B input (INTC) PINT4B input (INTC)
Table 25.6 Multiplexed Pin Table (Port F)
Function 1 PFnMD[2:0] = 000 Function 2 PFnMD[2:0] = 001 Function 3 PFnMD[2:0] = 010 (Related modules) Function 4 PFnMD[2:0] = 011 (Related modules) Function 5 PFnMD[2:0] = 100 (Related modules)
Port (Related modules) (Related modules) F PF7 I/O (Port) PF6 I/O (Port) PF5 I/O (Port) PF4 I/O (Port) PF3 I/O (Port) PF2 I/O (Port) PF1 I/O (Port) PF0 I/O (Port) AUDATA3 I/O (AUD-II) AUDATA2 I/O (AUD-II) AUDATA1 I/O (AUD-II) AUDATA0 I/O (AUD-II) AUDSYNC input (AUD-II) AUDCK input (AUD-II) AUDMD input (AUD-II) AUDRST input (AUD-II)
SCK7 I/O (SCIF) RxD7 input (SCIF) TxD7 output (SCIF)
TCLKD input (MTU2)
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Section 25 Pin Function Controller (PFC)
25.1
Register Descriptions
The PFC includes the following registers. Table 25.7 Register Configuration
Register Port A I/O register H Port A I/O register L Port A control register 8 Port A control register 7 Port A control register 6 Port A control register 5 Port A control register 4 Port A control register 3 Port A control register 2 Port A control register 1 Port B I/O register H Port B I/O register L Port B control register 8 Port B control register 7 Port B control register 6 Port B control register 5 Port B control register 4 Port B control register 3 Port B control register 2 Port B control register 1 Port C I/O register H Port C I/O register L Port C control register 7 Port C control register 6 Port C control register 5 Abbr. PAIORH PAIORL PACR8 PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PBIORH PBIORL PBCR8 PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PCIORH PCIORL PCCR7 PCCR6 PCCR5 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'1111 H'1111 H'1111 H'1111 H'1111 H'1111 H'0000 H'0000 H'0000/H'1111 H'0000/H'1111 H'0000/H'1111 H'0000/H'1111 H'0000/H'1111 H'0000/H'1111 H'1111 H'1111 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFE3880 H'FFFE3882 H'FFFE3884 H'FFFE3886 H'FFFE3888 H'FFFE388A H'FFFE388C H'FFFE388E H'FFFE3890 H'FFFE3892 H'FFFE3898 H'FFFE389A H'FFFE389C H'FFFE389E H'FFFE38A0 H'FFFE38A2 H'FFFE38A4 H'FFFE38A6 H'FFFE38A8 H'FFFE38AA H'FFFE38B0 H'FFFE38B2 H'FFFE38B6 H'FFFE38B8 H'FFFE38BA Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16
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Section 25 Pin Function Controller (PFC)
Register Port C control register 4 Port C control register 3 Port C control register 2 Port C control register 1 Port D I/O register Port D control register 5 Port D control register 4 Port D control register 3 Port D control register 2 Port D control register 1 Port E control register 2 Port E control register 1 Port F I/O register Port F control register 2 Port F control register 1
Abbr. PCCR4 PCCR3 PCCR2 PCCR1 PDIOR PDCR5 PDCR4 PDCR3 PDCR2 PDCR1 PECR2 PECR1 PFIOR PFCR2 PFCR1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value H'0000/H'0001
Address H'FFFE38BC
Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16
H'0011/H'0111/ H'FFFE38BE H'1111 H'0000 H'0001 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFE38C0 H'FFFE38C2 H'FFFE38CA H'FFFE38D2 H'FFFE38D4 H'FFFE38D6 H'FFFE38D8 H'FFFE38DA H'FFFE38F0 H'FFFE38F2 H'FFFE38FA H'FFFE3908 H'FFFE390A
Rev. 2.00 Sep. 07, 2007 Page 1070 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.1
Port A I/O Registers H and L (PAIORH and PAIORL)
PAIORH and PAIORL are 16-bit readable/writable registers that select the I/O direction for the port A pins. Bits PA31IOR to PA0IOR correspond to pins PA31 to PA0, respectively. PAIORH and PAIORL are enabled when the function of the port A pins is set to general-purpose I/O (PA31 to PA0) by PACR, and are disabled in other cases. When a bit in PAIORH and PAIORL is set to 1, the corresponding pin is set to output, and when set to 0, the pin is set to input. PAIORH and PAIORL are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. (1) Port A I/O Register H (PAIORH)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(2)
Port A I/O Register L (PAIORL)
Bit: 15 14 13 12 11 10 9 8 PA8 IOR 0 R/W 7 PA7 IOR 0 R/W 6 PA6 IOR 0 R/W 5 PA5 IOR 0 R/W 4 PA4 IOR 0 R/W 3 PA3 IOR 0 R/W 2 PA2 IOR 0 R/W 1 PA1 IOR 0 R/W 0 PA0 IOR 0 R/W
PA15 PA14 PA13 PA12 PA11 PA10 PA9 IOR IOR IOR IOR IOR IOR IOR Initial value: 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W
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Section 25 Pin Function Controller (PFC)
25.1.2
Port A Control Registers 1 to 8 (PACR1 to PACR8)
PACR1 to PACR8 are 16-bit readable/writable registers that select the functions of the multiplexed port A pins. When PINT3B to PINT0B are selected, do not set A input for the same interrupt. PACR8 and PACR7 are initialized to H'0000 by a power-on reset or by switching to deep standby mode. PACR1 to PACR6 are initialized to H'1111 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. (1) Port A Control Register 8 (PACR8)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PA31MD[1:0] 0 R/W 0 R/W
PA30MD[1:0] 0 R/W 0 R/W
PA29MD[1:0] 0 R/W 0 R/W
PA28MD[1:0] 0 R/W 0 R/W
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PA31MD [1:0]
00
R/W
PA31 Mode These bits control the function of the PA31/CRx1/ DTEND0 pin. 00: PA31 I/O (port) 01: CRx1 input (RCAN-ET) 10: DTEND0 output (DMAC) 11: Setting prohibited
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 25 Pin Function Controller (PFC)
Bit 9, 8
Bit Name PA30MD [1:0]
Initial Value 00
R/W R/W
Description PA30 Mode These bits control the function of the PA30/CTx1/ DACT0 pin. 00: PA30 I/O (port) 01: CTx1 output (RCAN-ET) 10: DACT0 output (DMAC) 11: Setting prohibited
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5, 4
PA29MD [1:0]
00
R/W
PA29 Mode These bits control the function of the PA29/CRx0/ DACK0 pin. 00: PA29 I/O (port) 01: CRx0 input (RCAN-ET) 10: DACK0 output (DMAC) 11: Setting prohibited
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PA28MD [1:0]
00
R/W
PA28 Mode These bits control the function of the PA28/CTx0/ DREQ0 pin. 00: PA28 I/O (port) 01: CTx0 output (RCAN-ET) 10: DREQ0 input (DMAC) 11: Setting prohibited
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Section 25 Pin Function Controller (PFC)
(2)
Port A Control Register 7 (PACR7)
Bit: 15 -- 14 13 12 11 -- 0 R 10 9 8 7 -- 0 R 6 5 4 3 -- 0 R 2 -- 0 R 1 0
PA27MD[2:0] 0 R/W 0 R/W 0 R/W
PA26MD[2:0] 0 R/W 0 R/W 0 R/W
PA25MD[2:0] 0 R/W 0 R/W 0 R/W
PA24MD[2:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit 15
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
14 to 12 PA27MD [2:0]
000
R/W
PA27 Mode These bits control the function of the PA27/A27/ DTEND3/PINT3B pin. 000: PA27 I/O (port) 001: A27 output (BSC) 010: DTEND3 output (DMAC) 011: PINT3B input (INTC) 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
11
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 25 Pin Function Controller (PFC)
Bit
Bit Name
Initial Value 000
R/W R/W
Description PA26 Mode These bits control the function of the PA26/A26/ DACT3/PINT2B pin. 000: PA26 I/O (port) 001: A26 output (BSC) 010: DACT3 output (DMAC) 011: PINT2B input (INTC) 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
10 to 8 PA26MD [2:0]
7
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
6 to 4
PA25MD [2:0]
000
R/W
PA25 Mode These bits control the function of the PA25/A25/ DACK3/PINT1B pin. 000: PA25 I/O (port) 001: A25 output (BSC) 010: DACK3 output (DMAC) 011: PINT1B input (INTC) 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PA24MD [1:0]
00
R/W
PA24 Mode These bits control the function of the PA24/A24/ DREQ3/PINT0B pin. 00: PA24 I/O (port) 01: A24 output (BSC) 10: DREQ3 input (DMAC) 11: PINT0B input (INTC)
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Section 25 Pin Function Controller (PFC)
(3)
Port A Control Register 6 (PACR6)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PA23 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PA22 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PA21 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PA20 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PA23MD0 1
R/W
PA23 Mode This bit controls the function of the PA23/A23 pin. 0: PA23 I/O (port) 1: A23 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PA22MD0 1
R/W
PA22 Mode This bit controls the function of the PA22/A22 pin. 0: PA22 I/O (port) 1: A22 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PA21MD0 1
R/W
PA21 Mode This bit controls the function of the PA21/A21 pin. 0: PA21 I/O (port) 1: A21 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PA20MD0 1
R/W
PA20 Mode This bit controls the function of the PA20/A20 pin. 0: PA20 I/O (port) 1: A20 output (BSC)
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Section 25 Pin Function Controller (PFC)
(4)
Port A Control Register 5 (PACR5)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PA19 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PA18 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PA17 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PA16 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PA19MD0 1
R/W
PA19 Mode This bit controls the function of the PA19/A19 pin. 0: PA19 I/O (port) 1: A19 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PA18MD0 1
R/W
PA18 Mode This bit controls the function of the PA18/A18 pin. 0: PA18 I/O (port) 1: A18 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PA17MD0 1
R/W
PA17 Mode This bit controls the function of the PA17/A17 pin. 0: PA17 I/O (port) 1: A17 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PA16MD0 1
R/W
PA16 Mode This bit controls the function of the PA16/A16 pin. 0: PA16 I/O (port) 1: A16 output (BSC)
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Section 25 Pin Function Controller (PFC)
(5)
Port A Control Register 4 (PACR4)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PA15 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PA14 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PA13 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PA12 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PA15MD0
1
R/W
PA15 Mode This bit controls the function of the PA15/A15 pin. 0: PA15 I/O (port) 1: A15 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PA14MD0
1
R/W
PA14 Mode This bit controls the function of the PA14/A14 pin. 0: PA14 I/O (port) 1: A14 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PA13MD0
1
R/W
PA13 Mode This bit controls the function of the PA13/A13 pin. 0: PA13 I/O (port) 1: A13 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PA12MD0
1
R/W
PA12 Mode This bit controls the function of the PA12/A12 pin. 0: PA12 I/O (port) 1: A12 output (BSC)
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Section 25 Pin Function Controller (PFC)
(6)
Port A Control Register 3 (PACR3)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PA11 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PA10 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PA9 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PA8 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PA11MD0
1
R/W
PA11 Mode This bit controls the function of the PA11/A11 pin. 0: PA11 I/O (port) 1: A11 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PA10MD0
1
R/W
PA10 Mode This bit controls the function of the PA10/A10 pin. 0: PA10 I/O (port) 1: A10 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PA9MD0
1
R/W
PA9 Mode This bit controls the function of the PA9/A9 pin. 0: PA9 I/O (port) 1: A9 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PA8MD0
1
R/W
PA8 Mode This bit controls the function of the PA8/A8 pin. 0: PA8 I/O (port) 1: A8 output (BSC)
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Section 25 Pin Function Controller (PFC)
(7)
Port A Control Register 2 (PACR2)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PA7 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PA6 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PA5 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PA4 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PA7MD0
1
R/W
PA7 Mode This bit controls the function of the PA7/A7 pin. 0: PA7 I/O (port) 1: A7 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PA6MD0
1
R/W
PA6 Mode This bit controls the function of the PA6/A6 pin. 0: PA6 I/O (port) 1: A6 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PA5MD0
1
R/W
PA5 Mode This bit controls the function of the PA5/A5 pin. 0: PA5 I/O (port) 1: A5 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PA4MD0
1
R/W
PA4 Mode This bit controls the function of the PA4/A4 pin. 0: PA4 I/O (port) 1: A4 output (BSC)
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Section 25 Pin Function Controller (PFC)
(8)
Port A Control Register 1 (PACR1)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PA3 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PA2 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PA1 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PA0 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PA3MD0
1
R/W
PA3 Mode This bit controls the function of the PA3/A3 pin. 0: PA3 I/O (port) 1: A3 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PA2MD0
1
R/W
PA2 Mode This bit controls the function of the PA2/A2 pin. 0: PA2 I/O (port) 1: A2 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PA1MD0
1
R/W
PA1 Mode This bit controls the function of the PA1/A1 pin. 0: PA1 I/O (port) 1: A1 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PA0MD0
1
R/W
PA0 Mode This bit controls the function of the PA0/A0 pin. 0: PA0 I/O (port) 1: A0 output (BSC)
Rev. 2.00 Sep. 07, 2007 Page 1081 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.3
Port B I/O Registers H and L (PBIORH and PBIORL)
PBIORH and PBIORL are 16-bit readable/writable registers that select the I/O direction for the port B pins. Bits PB31IOR to PB0IOR correspond to pins PB31 to PB0, respectively. PBIORH and PBIORL are enabled when the function of the port B pins is set to general-purpose I/O (PB31 to PB0) and to TIOC I/O (MTU2) by PBCR, and are disabled in other cases. When a bit in PBIORH and PBIORL is set to 1, the corresponding pin is set to output, and when set to 0, the pin is set to input. PBIORH and PBIORL are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. (1) Port B I/O Register H (PBIORH)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(2)
Port B I/O Register L (PBIORL)
Bit: 15 14 13 12 11 10 9 8 PB8 IOR 0 R/W 7 PB7 IOR 0 R/W 6 PB6 IOR 0 R/W 5 PB5 IOR 0 R/W 4 PB4 IOR 0 R/W 3 PB3 IOR 0 R/W 2 PB2 IOR 0 R/W 1 PB1 IOR 0 R/W 0 PB0 IOR 0 R/W
PB15 PB14 PB13 PB12 PB11 PB10 PB9 IOR IOR IOR IOR IOR IOR IOR Initial value: 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Sep. 07, 2007 Page 1082 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.4
Port B Control Registers 1 to 8 (PBCR1 to PBCR8)
PBCR1 to PBCR8 are 16-bit readable/writable registers that select the functions of the multiplexed port B pins. When IRQ7A to IRQ0A or PINT7A to PINT0A are selected, do not set B input for the same interrupt. PBCR1 and PBCR2 are initialized to H'1111 by a power-on reset or by switching to deep standby mode. PBCR3 to PBCR8 are initialized to the values shown in table 25.8 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. Table 25.8 Port B Control Register Initial Values
Initial Value Register PBCR5 to PBCR8 PBCR3, PBCR4 Area 0: 32-Bit Mode H'1111 H'1111 Area 0: 16-Bit Mode H'0000 H'1111 Area 0: 8-Bit Mode H'0000 H'0000
(1)
Port B Control Register 8 (PBCR8)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 9
PB30MD[2:0]
8
7 -- 0 R
6
5
PB29MD[2:0]
4
3 -- 0 R
2
1
PB28MD[2:0]
0
PB31MD[1:0]
Initial value: R/W:
0 R
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
Note: * The initial value depends on the LSI's operating mode.
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PB31MD [1:0]
00/01*
R/W
PB31 Mode These bits control the function of the PB31/D31/ PINT7A pin. 00: PB31 I/O (port) 01: D31 I/O (BSC) 10: PINT7A input (INTC) 11: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 1083 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 11
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
10 to 8
PB30MD [2:0]
000/001* R/W
PB30 Mode These bits control the function of the PB30/D30/ PINT6A/SCK3/TMCI0 pin. 000: PB30 I/O (port) 001: D30 I/O (BSC) 010: PINT6A input (INTC) 011: SCK3 I/O (SCIF) 100: TMCI0 input (TMR) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
7
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
6 to 4
PB29MD [2:0]
000/001* R/W
PB29 Mode These bits control the function of the PB29/D29/ PINT5A/RxD3/TMRI0 pin. 000: PB29 I/O (port) 001: D29 I/O (BSC) 010: PINT5A input (INTC) 011: RxD3 input (SCIF) 100: TMRI0 input (TMR) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
3
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1084 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 2 to 0
Bit Name PB28MD [2:0]
Initial Value
R/W
Description PB28 Mode These bits control the function of the PB28/D28/ PINT4A/TxD3/TMO0 pin. 000: PB28 I/O (port) 001: D28 I/O (BSC) 010: PINT4A input (INTC) 011: TxD3 output (SCIF) 100: TMO0 output (TMR) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
000/001* R/W
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1085 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(2)
Port B Control Register 7 (PBCR7)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 9
PB26MD[2:0]
8
7 -- 0 R
6
5
PB25MD[2:0]
4
3 -- 0 R
2
1
PB24MD[2:0]
0
PB27MD[1:0]
Initial value: R/W: Note: *
0 R
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
The initial value depends on the LSI's operating mode.
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PB27MD [1:0]
00/01*
R/W
PB27 Mode These bits control the function of the PB27/D27/ PINT3A pin. 00: PB27 I/O (port) 01: D27 I/O (BSC) 10: PINT3A input (INTC) 11: Setting prohibited
11
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10 to 8
PB26MD [2:0]
000/001* R/W
PB26 Mode These bits control the function of the PB26/D26/ PINT2A/TIC5W/SCK6 pin. 000: PB26 I/O (port) 001: D26 I/O (BSC) 010: PINT2A input (INTC) 011: TIC5W input (MTU2) 100: SCK6 I/O (SCIF) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 1086 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 7
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6 to 4
PB25MD [2:0]
000/001* R/W
PB25 Mode These bits control the function of the PB25/D25/ PINT1A/TIC5V/RxD6 pin. 000: PB25 I/O (port) 001: D25 I/O (BSC) 010: PINT1A input (INTC) 011: TIC5V input (MTU2) 100: RxD6 input (SCIF) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
3
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2 to 0
PB24MD [2:0]
000/001* R/W
PB24 Mode These bits control the function of the PB24/D24/ PINT0A/TIC5U/TxD6 pin. 000: PB24 I/O (port) 001: D24 I/O (BSC) 010: PINT0A input (INTC) 011: TIC5U input (MTU2) 100: TxD6 output (SCIF) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1087 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(3)
Port B Control Register 6 (PBCR6)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 9
PB22MD[2:0]
8
7 -- 0 R
6
5
PB21MD[2:0]
4
3 -- 0 R
2
1
PB20MD[2:0]
0
PB23MD[1:0]
Initial value: R/W: Note: *
0 R
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
0 R/W
0 R/W
0/1* R/W
The initial value depends on the LSI's operating mode.
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PB23MD [1:0]
00/01*
R/W
PB23 Mode These bits control the function of the PB23/D23/ IRQ7A/TIOC4D pin. 00: PB23 I/O (port) 01: D23 I/O (BSC) 10: IRQ7A input (INTC) 11: TIOC4D I/O (MTU2)
11
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10 to 8
PB22MD [2:0]
000/001* R/W
PB22 Mode These bits control the function of the PB22/D22/ IRQ6A/TIOC4C/SCK2 pin. 000: PB22 I/O (port) 001: D22 I/O (BSC) 010: IRQ6A input (INTC) 011: TIOC4C I/O (MTU2) 100: SCK2 I/O (SCIF) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 1088 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 7
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6 to 4
PB21MD [2:0]
000/001* R/W
PB21 Mode These bits control the function of the PB21/D21/ IRQ5A/TIOC4B/RxD2 pin. 000: PB21 I/O (port) 001: D21 I/O (BSC) 010: IRQ5A input (INTC) 011: TIOC4B I/O (MTU2) 100: RxD2 input (SCIF) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
3
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2 to 0
PB20MD [2:0]
000/001* R/W
PB20 Mode These bits control the function of the PB20/D20/ IRQ4A/TIOC4A/TxD2 pin. 000: PB20 I/O (port) 001: D20 I/O (BSC) 010: IRQ4A input (INTC) 011: TIOC4A I/O (MTU2) 100: TxD2 output (SCIF) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1089 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(4)
Port B Control Register 5 (PBCR5)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PB19MD[1:0]
PB18MD[2:0]
PB17MD[2:0]
PB16MD[2:0]
Initial value: R/W:
0 R
0 R/W
0/1* R/W
0 R/W
0/1* R/W
0 R/W
0/1* R/W
0 R/W
0/1* R/W
Note: * The initial value dependes on the LSI's clock operating mode.
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PB19MD [1:0]
00/01*
R/W
PB19 Mode These bits control the function of the PB19/D19/ IRQ3A/TIOC3D pin. 00: PB19 I/O (port) 01: D19 I/O (BSC) 10: IRQ3A input (INTC) 11: TIOC3D I/O (MTU2)
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PB18MD [1:0]
00/01*
R/W
PB18 Mode These bits control the function of the PB18/D18/ IRQ2A/TIOC3C pin. 00: PB18 I/O (port) 01: D18 I/O (BSC) 10: IRQ2A input (INTC) 11: TIOC3C I/O (MTU2)
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1090 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 5, 4
Bit Name PB17MD [1:0]
Initial Value 00/01*
R/W R/W
Description PB17 Mode These bits control the function of the PB17/D17/ IRQ1A/TIOC3B pin. 00: PB17 I/O (port) 01: D17 I/O (BSC) 10: IRQ1A input (INTC) 11: TIOC3B I/O (MTU2)
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PB16MD [1:0]
00/01*
R/W
PB16 Mode These bits control the function of the PB16/D16/ IRQ0A/TIOC3A pin. 00: PB16 I/O (port) 01: D16 I/O (BSC) 10: IRQ0A input (INTC) 11: TIOC3A I/O (MTU2)
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1091 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(5)
Port B Control Register 4 (PBCR4)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PB15 MD0 0/1 * R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PB14 MD0 0/1 * R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PB13 MD0 0/1 * R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PB12 MD0 0/1 * R/W
Initial value: R/W:
0 R
Note: * The initial value dependes on the LSI's clock operating mode.
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. PB15 Mode This bit controls the function of the PB15/D15 pin. 0: PB15 I/O (port) 1: D15 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB14 Mode This bit controls the function of the PB14/D14 pin. 0: PB14 I/O (port) 1: D14 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB13 Mode This bit controls the function of the PB13/D13 pin. 0: PB13 I/O (port) 1: D13 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB12 Mode This bit controls the function of the PB12/D12 pin. 0: PB12 I/O (port) 1: D12 I/O (BSC)
15 to 13 --
12
PB15MD0
0/1*
R/W
11 to 9
--
All 0
R
8
PB14MD0
0/1*
R/W
7 to 5
--
All 0
R
4
PB13MD0
0/1*
R/W
3 to 1
--
All 0
R
0
PB12MD0
0/1*
R/W
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1092 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(6)
Port B Control Register 3 (PBCR3)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PB11 MD0 0/1* R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PB10 MD0 0/1* R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PB9 MD0 0/1* R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PB8 MD0 0/1* R/W
Initial value: R/W:
0 R
Note: * The initial value dependes on the LSI's clock operating mode.
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. PB11 Mode This bit controls the function of the PB11/D11 pin. 0: PB11 I/O (port) 1: D11 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB10 Mode This bit controls the function of the PB10/D10 pin. 0: PB10 I/O (port) 1: D10 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB9 Mode This bit controls the function of the PB9/D9 pin. 0: PB9 I/O (port) 1: D9 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB8 Mode This bit controls the function of the PB8/D8 pin. 0: PB8 I/O (port) 1: D8 I/O (BSC)
15 to 13 --
12
PB11MD0
0/1*
R/W
11 to 9
--
All 0
R
8
PB10MD0
0/1*
R/W
7 to 5
--
All 0
R
4
PB9MD0
0/1*
R/W
3 to 1
--
All 0
R
0
PB8MD0
0/1*
R/W
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1093 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(7)
Port B Control Register 2 (PBCR2)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PB7 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PB6 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PB5 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PB4 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. PB7 Mode This bit controls the function of the PB7/D7 pin. 0: PB7 I/O (port) 1: D7 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB6 Mode This bit controls the function of the PB6/D6 pin. 0: PB6 I/O (port) 1: D6 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB5 Mode This bit controls the function of the PB5/D5 pin. 0: PB5 I/O (port) 1: D5 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB4 Mode This bit controls the function of the PB4/D4 pin. 0: PB4 I/O (port) 1: D4 I/O (BSC)
15 to 13 --
12
PB7MD0
1
R/W
11 to 9
--
All 0
R
8
PB6MD0
1
R/W
7 to 5
--
All 0
R
4
PB5MD0
1
R/W
3 to 1
--
All 0
R
0
PB4MD0
1
R/W
Rev. 2.00 Sep. 07, 2007 Page 1094 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(8)
Port B Control Register 1 (PBCR1)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PB3 MD0 1 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PB2 MD0 1 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PB1 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PB0 MD0 1 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. PB3 Mode This bit controls the function of the PB3/D3 pin. 0: PB3 I/O (port) 1: D3 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB2 Mode This bit controls the function of the PB2/D2 pin. 0: PB2 I/O (port) 1: D2 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB1 Mode This bit controls the function of the PB1/D1 pin. 0: PB1 I/O (port) 1: D1 I/O (BSC) Reserved These bits are always read as 0. The write value should always be 0. PB0 Mode This bit controls the function of the PB0/D0 pin. 0: PB0 I/O (port) 1: D0 I/O (BSC)
15 to 13 --
12
PB3MD0
1
R/W
11 to 9
--
All 0
R
8
PB2MD0
1
R/W
7 to 5
--
All 0
R
4
PB1MD0
1
R/W
3 to 1
--
All 0
R
0
PB0MD0
1
R/W
Rev. 2.00 Sep. 07, 2007 Page 1095 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.5
Port C I/O Registers H and L (PCIORH and PCIORL)
PCIORH and PCIORL are 16-bit readable/writable registers that select the I/O direction for the port C pins. Bits PC21IOR to PC0IOR correspond to pins PC21 to PC0, respectively. PCIORH and PCIORL are enabled when the function of the port C pins is set to general-purpose I/O (PC21 to PC0) and to TIOC I/O (MTU2) by PCCR, and are disabled in other cases. When a bit in PCIORH and PCIORL is set to 1, the corresponding pin is set to output, and when set to 0, the pin is set to input. Bits 15 to 6 in PCIORH are reserved. These bits are always read as 0. The write value should always be 0. PCIORH and PCIORL are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. (1) Port C I/O Register H (PCIORH)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 4 3 2 1 0
PC21 PC20 PC19 PC18 PC17 PC16 IOR IOR IOR IOR IOR IOR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W
(2)
Port C I/O Register L (PCIORL)
Bit: 15 14 13 12 11 10 9 8 PC8 IOR 0 R/W 7 PC7 IOR 0 R/W 6 PC6 IOR 0 R/W 5 PC5 IOR 0 R/W 4 PC4 IOR 0 R/W 3 PC3 IOR 0 R/W 2 PC2 IOR 0 R/W 1 PC1 IOR 0 R/W 0 PC0 IOR 0 R/W
PC15 PC14 PC13 PC12 PC11 PC10 PC9 IOR IOR IOR IOR IOR IOR IOR Initial value: 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Sep. 07, 2007 Page 1096 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.6
Port C Control Registers 1 to 7 (PCCR1 to PCCR7)
PCCR1 to PCCR7 are 16-bit readable/writable registers that select the functions of the multiplexed port C pins. When IRQ3B to IRQ0B are selected, do not set A input for the same interrupt. PCCR2, PCCR5, PCCR6, and PCCR7 are initialized to H'0000 by a power-on reset or by switching to deep standby mode. PCCR1 is initialized to H'0001 and PCCR3 and PCCR4 are initialized to the values shown in table 25.9 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. Table 25.9 Port C Control Register Initial Values
Initial value Register PCCR4 PCCR3 Area 0: 32-Bit Mode H'0001 H'1111 Area 0: 16-Bit Mode H'0000 H'0111 Area 0: 8-Bit Mode H'0000 H'0011
(1)
Port C Control Register 7 (PCCR7)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PC25MD1[1:0]
PC24MD1[1:0]
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 6
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5, 4
PC25MD [1:0]
00
R/W
PC25 Mode These bits control the function of the PC25/IRQ3B/ SDA1 pin. 00: PC25 input (port) 01: IRQ3B input (INTC) 10: Setting prohibited 11: SDA1 I/O (IIC3)
Rev. 2.00 Sep. 07, 2007 Page 1097 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 3, 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PC24MD [1:0]
00
R/W
PC24 Mode These bits control the function of the PC24/IRQ2B/ SCL1 pin. 00: PC24 input (port) 01: IRQ2B input (INTC) 10: Setting prohibited 11: SCL1 I/O (IIC3)
(2)
Port C Control Register 6 (PCCR6)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PC23MD[1:0]
PC22MD[1:0]
PC21MD[1:0]
PC20MD[1:0]
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PC23MD [1:0]
00
R/W
PC23 Mode These bits control the function of the PC23/IRQ1B/ SDA0 pin. 00: PC23 input (port) 01: IRQ1B input (INTC) 10: Setting prohibited 11: SDA0 I/O (IIC3)
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1098 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 9, 8
Bit Name PC22MD [1:0]
Initial Value 00
R/W R/W
Description PC22 Mode These bits control the function of the PC22/ IRQ0B/DREQ2/SCL0 pin. 00: PC22 input (port) 01: IRQ0B input (INTC) 10: DREQ2 input (DMAC) 11: SCL0 I/O (IIC3)
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5, 4
PC21MD [1:0]
00
R/W
PC21 Mode These bits control the function of the PC21/BC3/ DQM3/TCLKC/DACK2 pin. 00: PC21 input (port) 01: BC3/DQM3 output (BSC) 10: TCLKC input (MTU2) 11: DACK2 output (DMAC)
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PC20MD [1:0]
00
R/W
PC20 Mode These bits control the function of the PC20/BC2/ DQM2/TCLKB pin. 00: PC20 I/O (port) 01: BC2/DQM2 output (BSC) 10: TCLKB input (MTU2) 11: Setting prohibited
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Section 25 Pin Function Controller (PFC)
(3)
Port C Control Register 5 (PCCR5)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PC19 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PC18 MD0 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PC17 MD0 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PC16 MD0 0 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PC19MD0
0
R/W
PC19 Mode This bit controls the function of the PC19/ BC1/ DQM1 pin. 0: PC19 I/O (port) 1: BC1/DQM1 output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PC18MD0
0
R/W
PC18 Mode This bit controls the function of the PC18/ BC0/ DQM0 pin. 0: PC18 I/O (port) 1: BC0/DQM0 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PC17MD0
0
R/W
PC17 Mode This bit controls the function of the PC17/SDWE pin. 0: PC17 I/O (port) 1: SDWE output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 25 Pin Function Controller (PFC)
Bit 0
Bit Name PC16MD0
Initial Value 0
R/W R/W
Description PC16 Mode This bit controls the function of the PC16/SDCAS pin. 0: PC16 I/O (port) 1: SDCAS output (BSC)
(4)
Port C Control Register 4 (PCCR4)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PC15 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PC14 MD0 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PC13 MD0 0 R/W 3 -- 0 R 2 -- 0 R 1 0
PC12MD[1:0]
Initial value: R/W:
0 R
0 R/W
0/1* R/W
Note: * The initial value dependes on the LSI's clock operating mode.
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PC15MD0
0
R/W
PC15 Mode This bit controls the function of the PC15/SDRAS pin. 0: PC15 I/O (port) 1: SDRAS output (BSC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PC14MD0
0
R/W
PC14 Mode This bit controls the function of the PC14/SDCKE pin. 0: PC14 I/O (port) 1: SDCKE output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1101 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 4
Bit Name PC13MD0
Initial Value 0
R/W R/W
Description PC13 Mode This bit controls the function of the PC13/WAIT pin. 0: PC13 I/O (port) 1: WAIT input (BSC)
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PC12MD [1:0]
00/01*
R/W
PC12 Mode These bits control the function of the PC12/WR3/TIOC2B/DTEND2 pin. 00: PC12 I/O (port) 01: WR3 output (BSC) 10: TIOC2B I/O (MTU2) 11: DTEND2 output (DMAC)
Note:
*
The initial value depends on the LSI's operating mode.
(5)
Port C Control Register 3 (PCCR3)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PC10 MD0 0/1* R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PC9 MD0 1 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PC8 MD0 1 R/W
PC11MD[1:0]
Initial value: R/W:
0 R
0 R/W
0/1* R/W
Note: * The initial value dependes on the LSI's clock operating mode.
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 25 Pin Function Controller (PFC)
Bit 13, 12
Bit Name PC11MD [1:0]
Initial Value 00/01*
R/W R/W
Description PC11 Mode These bits control the function of the PC11/WR2/ TIOC2A/DACT2 pin. 00: PC11 I/O (port) 01: WR2 output (BSC) 10: TIOC2A I/O (MTU2) 11: DACT2 output (DMAC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PC10MD0
0/1*
R/W
PC10 Mode This bit controls the function of the PC10/WR1 pin. 0: PC10 I/O (port) 1: WR1 output (BSC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PC9MD0
1
R/W
PC9 Mode This bit controls the function of the PC9/WR0 pin. 0: PC9 I/O (port) 1: WR0 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PC8MD0
1
R/W
PC8 Mode This bit controls the function of the PC8/RD pin. 0: PC8 I/O (port) 1: RD output (BSC)
Note:
*
The initial value depends on the LSI's operating mode.
Rev. 2.00 Sep. 07, 2007 Page 1103 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(6)
Port C Control Register 2 (PCCR2)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PC7 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PC6MD[1:0] 0 R/W 0 R/W
PC5MD[1:0] 0 R/W 0 R/W
PC4MD[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PC7MD0
0
R/W
PC7 Mode This bit controls the function of the PC7/SDCS0 pin. 0: PC7 I/O (port) 1: SDCS0 output (BSC)
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PC6MD[1:0] 00
R/W
PC6 Mode These bits control the function of the PC6/CS6/ SCK5/TCLKA pin. 00: PC6 I/O (port) 01: CS6 output (BSC) 10: SCK5 I/O (SCIF) 11: TCLKA input (MTU2)
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5, 4
PC5MD[1:0] 00
R/W
PC5 Mode These bits control the function of the PC5/CS5/ RxD5/TIOC1B pin. 00: PC5 I/O (port) 01: CS5 output (BSC) 10: RxD5 input (SCIF) 11: TICO1B I/O (MTU2)
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Section 25 Pin Function Controller (PFC)
Bit 3, 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PC4MD[1:0] 00
R/W
PC4 Mode These bits control the function of the PC4/CS4/ TxD5/TIOC1A pin. 00: PC4 I/O (port) 01: CS4 output (BSC) 10: TxD5 output (SCIF) 11: TIOC1A I/O (MTU2)
(7)
Port C Control Register 1 (PCCR1)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PC1 MD0 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PC0 MD0 1 R/W
PC3MD[1:0] 0 R/W 0 R/W
PC2MD[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PC3MD[1:0] 00
R/W
PC3 Mode These bits control the function of the PC3/CS3/ UBCTRG pin. 00: PC3 I/O (port) 01: CS3 output (BSC) 10: UBCTRG output (UBC) 11: Setting prohibited
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1105 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 9, 8
Bit Name
Initial Value
R/W R/W
Description PC2 Mode These bits control the function of the PC2/CS2/ SDCS1/ADTRG pin. 00: PC2 I/O (port) 01: CS2 output (BSC) 10: SDCS1 output (BSC) 11: ADTRG input (A/D)
PC2MD[1:0] 00
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PC1MD0
0
R/W
PC1 Mode This bit controls the function of the PC1/CS1 pin. 0: PC1 I/O (port) 1: CS1 output (BSC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PC0MD0
1
R/W
PC0 Mode This bit controls the function of the PC0/CS0 pin. 0: PC0 I/O (port) 1: CS0 output (BSC)
Rev. 2.00 Sep. 07, 2007 Page 1106 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.7
Port D I/O Register (PDIOR)
PDIOR are 16-bit readable/writable registers that select the I/O direction for the port D pins. Bits PD14IOR to PD0IOR correspond to pins PD14 to PD0, respectively. PDIOR are enabled when the function of the port D pins is set to general-purpose I/O (PD14 to PD0) and to TIOC I/O (MTU2) by PDCR, and are disabled in other cases. When a bit in PDIOR is set to 1, the corresponding pin is set to output, and when set to 0, the pin is set to input. Bits 15 in PDIOR is reserved. These bits are always read as 0. The write value should always be 0. PDIOR are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 13 12 11 10 9 8 PD8 IOR 0 R/W 7 PD7 IOR 0 R/W 6 PD6 IOR 0 R/W 5 PD5 IOR 0 R/W 4 PD4 IOR 0 R/W 3 PD3 IOR 0 R/W 2 PD2 IOR 0 R/W 1 PD1 IOR 0 R/W 0 PD0 IOR 0 R/W
PD14 PD13 PD12 PD11 PD10 PD9 IOR IOR IOR IOR IOR IOR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W
Rev. 2.00 Sep. 07, 2007 Page 1107 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.8
Port D Control Registers 1 to 5 (PDCR1 to PDCR5)
PDCR1 to PDCR5 are 16-bit readable/writable registers that select the functions of the multiplexed port D pins. PDCR1 to PDCR5 are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. (1) Port D Control Register 5 (PDCR5)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 0
PD16MD[1:0] 0 R/W 0 R/W
Bit 15 to 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PD16MD [1:0]
00
R/W
PD16 Mode These bits control the function of the PD16/SCL2 pin. 00: PD16 input (port) 01: SCL2 I/O (IIC3) 10: Setting prohibited 11: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 1108 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(2)
Port D Control Register 4 (PDCR4)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PD15MD[1:0] 0 R/W 0 R/W
PD14MD[1:0] 0 R/W 0 R/W
PD13MD[1:0] 0 R/W 0 R/W
PD12MD[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PD15MD [1:0]
00
R/W
PD15 Mode These bits control the function of the PD15/ SDA2 pin. 00: PD15 input (port) 01: SDA2 I/O (IIC3) 10: Setting prohibited 11: Setting prohibited
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PD14MD [1:0]
00
R/W
PD14 Mode These bits control the function of the PD14/ IERxD/DACK1 pin. 00: PD14 I/O (port) 01: IERxD input (IEB) 10: DACK1 output (DMAC) 11: Setting prohibited
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1109 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 5, 4
Bit Name PD13MD [1:0]
Initial Value 000
R/W R/W
Description PD13 Mode These bits control the function of the PD13/ IETxD/DREQ1 pin. 00: PD13 I/O (port) 01: IETxD output (IEB) 10: DREQ1 input (DMAC) 11: Setting prohibited
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PD12MD [1:0]
00
R/W
PD12 Mode These bits control the function of the PD12/ SCK1/TMCI1 pin. 00: PD12 I/O (port) 01: SCK1 I/O (SCIF) 10: TMCI1 input (TMR) 11: Setting prohibited
Rev. 2.00 Sep. 07, 2007 Page 1110 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(3)
Port D Control Register 3 (PDCR3)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PD11MD[1:0] 0 R/W 0 R/W
PD10MD[1:0] 0 R/W 0 R/W
PD9MD[1:0] 0 R/W 0 R/W
PD8MD[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13, 12
PD11MD [1:0]
00
R/W
PD11 Mode These bits control the function of the PD11/ RxD1/TMRI1 pin. 00: PD11 I/O (port) 01: RxD1 input (SCIF) 10: TMRI1 output (TMR) 11: Setting prohibited
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PD10MD [1:0]
00
R/W
PD10 Mode These bits control the function of the PD10/ TxD1/TMO1/TIOC0D pin. 00: PD10 I/O (port) 01: TxD1 output (SCIF) 10: TMO1 output (TMR) 11: TIOC0D I/O (MTU2)
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1111 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 5, 4
Bit Name
Initial Value
R/W R/W
Description PD9 Mode These bits control the function of the PD9/ SCK0/TIOC0C pin. 00: PD9 I/O (port) 01: SCK0 I/O (SCIF) 10: Setting prohibited 11: TIOC0C I/O (MTU2)
PD9MD[1:0] 00
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PD8MD[1:0] 00
R/W
PD8 Mode These bits control the function of the PD8/RxD0/DTEND1/TIOC0B pin. 00: PD8 I/O (port) 01: RxD0 input (SCIF) 10: DTEND1 output (DMAC) 11: TIOC0B I/O (MTU2)
(4)
Port D Control Register 2 (PDCR2)
Bit: 15 -- 14 -- 0 R 13 12 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PD7MD[1:0] 0 R/W 0 R/W
PD6MD[1:0] 0 R/W 0 R/W
PD5MD[1:0] 0 R/W 0 R/W
PD4MD[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit 15, 14
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1112 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 13, 12
Bit Name
Initial Value
R/W R/W
Description PD7 Mode These bits control the function of the PD7/TxD0/DACT1/TIOC0A pin. 00: PD7 I/O (port) 01: TxD0 output (SCIF) 10: DACT1 output (DMAC) 11: TIOC0A I/O (MTU2)
PD7MD[1:0] 00
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PD6MD[1:0] 00
R/W
PD6 Mode These bits control the function of the PD6/ SSIWS1/SCK4 pin. 00: PD6 I/O (port) 01: SSIWS1 I/O (SSI) 10: SCK4 I/O (SCIF) 11: Setting prohibited
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
5, 4
PD5MD[1:0] 00
R/W
PD5 Mode These bits control the function of the PD5/ SSICK1/RxD4 pin. 00: PD5 I/O (port) 01: SSISCK1 I/O (SSI) 10: RxD4 input (SCIF) 11: Setting prohibited
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1113 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 1, 0
Bit Name
Initial Value
R/W R/W
Description PD4 Mode These bits control the function of the PD4/ SSIDATA1/TxD4 pin. 00: PD4 I/O (port) 01: SSIDATA1 I/O (SSI) 10: TxD4 output (SCIF) 11: Setting prohibited
PD4MD[1:0] 00
(5)
Port D Control Register 1 (PDCR1)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PD3 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PD2 MD0 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PD1 MD0 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PD0 MD0 0 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PD3MD0
0
R/W
PD3 Mode This bit controls the function of the PD3/SSIWS0 pin. 0: PD3 I/O (port) 1: SSIWS0 I/O (SSI)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PD2MD0
0
R/W
PD2 Mode This bit controls the function of the PD2/SICK0 pin. 0: PD2 I/O (port) 1: SSISCK0 I/O (SSI)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1114 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 4
Bit Name PD1MD0
Initial Value 0
R/W R/W
Description PD1 Mode This bit controls the function of the PD1/SSIDATA0 pin. 0: PD1 I/O (port) 1: SSIDATA0 I/O (SSI)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PD0MD0
0
R/W
PD0 Mode This bit controls the function of the PD0/ AUDIO_CLK pin. 0: PD0 I/O (port) 1: AUDIO_CLK input (SSI)
25.1.9
Port E Control Registers 1 and 2 (PECR1 and PECR2)
PECR1 and PECR2 are 16-bit readable/writable registers that select the functions of the multiplexed port E pins. The pins states are set by the corresponding module for A/D converter input and for D/A converter output. When IRQ7B to IRQ4B or PINT7B to PINT4B are selected, do not set A input for the same interrupt. PECR1 and PECR2 are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode.
Rev. 2.00 Sep. 07, 2007 Page 1115 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(1)
Port E Control Register 2 (PECR2)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PE7 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PE6 MD0 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PE5 MD0 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PE4 MD0 0 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PE7MD0
0
R/W
PE7 Mode This bit controls the function of the PE7/IRQ7B pin. 0: PE7 input (port) 1: IRQ7B input (INTC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PE6MD0
0
R/W
PE6 Mode This bit controls the function of the PE6/IRQ6B pin. 0: PE6 input (port) 1: IRQ6B input (INTC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PE5MD0
0
R/W
PE5 Mode This bit controls the function of the PE5/IRQ5B pin. 0: PE5 input (port) 1: IRQ5B input (INTC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PE4MD0
0
R/W
PE4 Mode This bit controls the function of the PE4/IRQ4B pin. 0: PE4 input (port) 1: IRQ4B input (INTC)
Rev. 2.00 Sep. 07, 2007 Page 1116 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
(2)
Port E Control Register 1 (PECR1)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PE3 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 PE2 MD0 0 R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 PE1 MD0 0 R/W 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 PE0 MD0 0 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PE3MD0
0
R/W
PE3 Mode This bit controls the function of the PE3/PINT7B pin. 0: PE3 input (port) 1: PINT7B input (INTC)
11 to 9
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
PE2MD0
0
R/W
PE2 Mode This bit controls the function of the PE2/PINT6B pin. 0: PE2 input (port) 1: PINT6B input (INTC)
7 to 5
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
PE1MD0
0
R/W
PE1 Mode This bit controls the function of the PE1/PINT5B pin. 0: PE1 input (port) 1: PINT5B input (INTC)
3 to 1
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PE0MD0
0
R/W
PE0 Mode This bit controls the function of the PE0/PINT4B pin. 0: PE0 input (port) 1: PINT4B input (INTC)
Rev. 2.00 Sep. 07, 2007 Page 1117 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.10 Port F I/O Register (PFIOR) PFIOR is a 16-bit readable/writable register that selects the I/O direction for the port F pins. Bits PF7IOR to PF0IOR correspond to pins PF7 to PF0, respectively. PFIOR is enabled when the function of the port F pins is set to general-purpose I/O (PF7 to PF0) by PFCR, and are disabled in other cases. When a bit in PFIOR is set to 1, the corresponding pin is set to output, and when set to 0, the pin is set to input. Bits 15 to 8 in PFIOR are reserved. These bits are always read as 0. The write value should always be 0. PFIOR is initialized to H'0000 by a power-on reset or by switching to deep standby mode. This register is not initialized either by a manual reset or by switching to sleep mode or software standby mode.
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 -- 0 R 11 -- 0 R 10 -- 0 R 9 -- 0 R 8 -- 0 R 7 PF7 IOR 0 R/W 6 PF6 IOR 0 R/W 5 PF5 IOR 0 R/W 4 PF4 IOR 0 R/W 3 PF3 IOR 0 R/W 2 PF2 IOR 0 R/W 1 PF1 IOR 0 R/W 0 PF0 IOR 0 R/W
Rev. 2.00 Sep. 07, 2007 Page 1118 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
25.1.11 Port F Control Registers 1 and 2 (PFCR1 and PFCR2) PFCR1 and PFCR2 are 16-bit readable/writable registers that select the functions of the multiplexed port F pins. PFCR1 and PFCR2 are initialized to H'0000 by a power-on reset or by switching to deep standby mode. These registers are not initialized either by a manual reset or by switching to sleep mode or software standby mode. (1) Port F Control Register 2 (PFCR2)
Bit: 15 -- Initial value: R/W: 0 R 14 -- 0 R 13 -- 0 R 12 PF7 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PF6MD[1:0] 0 R/W 0 R/W
PF5MD[1:0] 0 R/W 0 R/W
PF4MD[1:0] 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PF7MD0
0
R/W
PF7 Mode This bit controls the function of the PF7/AUDATA3 pin. 0: PF7 I/O (port) 1: AUDATA3 I/O (AUD-II)
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PF6MD[1:0] 00
R/W
PF6 Mode These bits control the function of the PF6/ AUDATA2 pin. 00: PF6 I/O (port) 01: AUDATA2 I/O (AUD-II) 10: Setting prohibited 11: Setting prohibited
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Section 25 Pin Function Controller (PFC)
Bit 7, 6
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5, 4
PF5MD[1:0] 00
R/W
PF5 Mode These bits control the function of the PF5/ AUDATA1 pin. 00: PF5 I/O (port) 01: AUDATA1 I/O (AUD-II) 10: Setting prohibited 11: Setting prohibited
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PF4MD[1:0] 00
R/W
PF4 Mode These bits control the function of the PF4/ AUDATA0 pin. 00: PF4 I/O (port) 01: AUDATA0 I/O (AUD-II) 10: Setting prohibited 11: Setting prohibited
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Section 25 Pin Function Controller (PFC)
(2)
Port F Control Register 1 (PFCR1)
Bit: 15 -- 14 -- 0 R 13 -- 0 R 12 PF3 MD0 0 R/W 11 -- 0 R 10 -- 0 R 9 8 7 -- 0 R 6 -- 0 R 5 4 3 -- 0 R 2 -- 0 R 1 0
PF2MD[1:0] 0 R/W 0 R/W
PF1MD[1:0] 0 R/W 0 R/W
PF0MD[1:0] 0 R/W 0 R/W
Initial value: R/W:
0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13 --
12
PF3MD0
0
R/W
PF3 Mode This bit controls the function of the PF3/ AUDSYNC pin. 0: PF3 I/O (port) 1: AUDSYNC input (AUD-II)
11, 10
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9, 8
PF2MD[1:0] 00
R/W
PF2 Mode These bits control the function of the PF2/ AUDCK/SCK7/TCLKD pin. 00: PF2 I/O (port) 01: AUDCK input (AUD-II) 10: SCK7 I/O (SCIF) 11: TCLKD input (MTU2)
7, 6
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 07, 2007 Page 1121 of 1312 REJ09B0320-0200
Section 25 Pin Function Controller (PFC)
Bit 5, 4
Bit Name
Initial Value
R/W R/W
Description PF1 Mode These bits control the function of the PF1/ AUDMD/RxD7 pin. 00: PF1 I/O (port) 01: AUDMD input (AUD-II) 10: RxD7 input (SCIF) 11: Setting prohibited
PF1MD[1:0] 00
3, 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1, 0
PF0MD[1:0] 00
R/W
PF0 Mode These bits control the function of the PF0/ AUDRST/TxD7 pin. 00: PF0 I/O (port) 01: AUDRST input (AUD-II) 10: TxD7 output (SCIF) 11: Setting prohibited
25.2
Usage Note
The settings of the port control registers are used as the output pin select signals, and are not basically used as the input pin select signals. This causes the signals input from the pins to propagate to all the modules having the relevant multiplexed pins. So, unnecessary input signals must be disabled by the settings of the respective modules. Settings of port control registers are decoded to enable/disable pins IRQ7A to IRQ0A and IRQ7B to IRQ0B or pins PINT7A to PINT0A and PINT7B to PINT0B. Be sure to select either one of them.
Rev. 2.00 Sep. 07, 2007 Page 1122 of 1312 REJ09B0320-0200
Section 26 On-Chip RAM
Section 26 On-Chip RAM
This LSI has an on-chip RAM module that achieves high-speed access and can store instructions or data. On-chip RAM operation and write access to the RAM can be enabled or disabled through the RAM enable bits and RAM write enable bits.
26.1
Features
* Pages Two pages (pages 0 and 1) are provided. * Memory map The on-chip RAM is located in the address spaces shown in table 26.1. Table 26.1 On-Chip RAM Address Spaces
Page Page 0 Page 1 Address H'FFF80000 to H'FFF83FFF H'FFF84000 to H'FFF87FFF
* Ports Each page has two independent read and write ports and is connected to the internal bus (I bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F bus is connected only to the read ports.) The F bus and M bus are used for access by the CPU, and the I bus is used for access by the DMAC via the internal DMA write bus/internal DMA read bus and bus bridge. * Priority When requests for access to the same page from different buses coincide, the access is processed in priority order. The priority is I bus > M bus > F bus.
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Section 26 On-Chip RAM
26.2
26.2.1
Usage Notes
Page Conflict
When the same page is accessed from different buses simultaneously, a conflict on the page occurs. Although each access is completed correctly, this kind of conflict degrades the memory access speed. Therefore, it is advisable to provide software measures to prevent such conflicts as far as possible. For example, no conflict will arise if different memory modules or different pages are accessed by each bus. 26.2.2 RAME and RAMWE Bits
Before disabling memory operation or write access through the RAME or RAMWE bit, be sure to read from any address and then write to the same address in each page; otherwise, the last written data in each page may not be actually written to the RAM.
// For RAM page 0 MOV.L MOV.L MOV.L #H'FFF80000,R0 @R0,R1 R1,@R0
// For RAM page 1 MOV.L MOV.L MOV.L #H'FFF84000,R0 @R0,R1 R1,@R0
Figure 26.1 Examples of Read/Write before Disabling RAM
Rev. 2.00 Sep. 07, 2007 Page 1124 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
Section 27 Power-Down Modes
This LSI supports sleep mode, software standby mode, deep standby mode, and module standby mode. In power-down modes, functions of CPU, clocks, on-chip memory, or part of on-chip peripheral modules are halted or the power-supply is turned off, through which low power consumption is achieved. These modes are canceled by a reset or interrupt.
27.1
27.1.1
Features
Power-Down Modes
This LSI has the following power-down modes and function: 1. 2. 3. 4. Sleep mode Software standby mode Deep standby mode Module standby function
Table 27.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode.
Rev. 2.00 Sep. 07, 2007 Page 1125 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
Table 27.1 States of Power-Down Modes
State*1 PowerDown Mode Sleep mode Transition Conditions Execute SLEEP instruction with STBY bit in STBCR cleared to 0 CPU CPG CPU Register Runs Halts Held On-Chip RAM Runs On-Chip Peripheral Modules Runs Power RTC Runs*
2
External Memory
Canceling Procedure Interrupt Manual reset Power-on reset Bus error NMI interrupt IRQ interrupt Manual reset Power-on reset NMI interrupt*4 IRQ interrupt*4 (only for PE7 to PE4 and PC25 to PC22) * * Manual reset*
4
supply Runs
Auto* refreshing * * *
Software standby mode
Execute SLEEP instruction with STBY bit in STBCR set to 1 and DEEP bit to 0
Halts Halts Held
Halts (contents are held)
Halts
Runs*2
Runs
Self-
*
refreshing * * *
Deep standby mode
Execute SLEEP Halts Halts Halts instruction with STBY and DEEP bits in STBCR set to 1
Halts (contents are held*3)
Halts
Runs*
2
Halts
Self* refreshing *
Power-on reset*4 Clear MSTP bit to 0 Power-on reset (only for RTC, H-UDI, UBC, DMAC, and AUD-II)
Module standby function
Set the MSTP bits in Runs Runs Held STBCR2 to STBCR5 to 1
Runs
Specified module halts
Halts
Runs
* refreshing * Auto-
Notes: 1. The pin state is retained or set to high impedance. For details, see appendix A, Pin States. 2. RTC operates when the START bit in the RCR2 register is set to 1. For details, see section 15, Realtime Clock (RTC). 3. Setting bits RAMKP3 to RAMKP0 in the RAMKP register to 1 enables the retention of data in the corresponding area in the on-chip RAM during the transition to deep standby mode. However, when deep standby mode is canceled by a power-on reset, the contents in the corresponding on-chip RAM area are not retained. 4. Deep standby mode can be canceled by an interrupt (NMI or IRQ) or a reset (manual reset or power-on reset). However, IRQ is reset only by PE7 to PE0 and PC25 to PC22. When deep standby mode is canceled by NMI interrupt or IRQ interrupt, reset exception handling is executed instead of interrupt exception handling. These are power-on reset exception handlings including a manual reset.
Rev. 2.00 Sep. 07, 2007 Page 1126 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2
Register Descriptions
The following registers are used in power-down modes. Table 27.2 Register Configuration
Register Name Standby control register Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 System control register 1 System control register 2 RAM retaining area specifying register Deep standby oscillation stabilizing clock select register Deep standby cancel source flag register Abbreviation STBCR STBCR2 STBCR3 STBCR4 STBCR5 SYSCR1 SYSCR2 RAMKP DSCNT R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'1E H'3F H'FF H'FF H'FF H'FF H'00 H'00 Address H'FFFE0014 H'FFFE0018 H'FFFE0408 H'FFFE040C H'FFFE0410 H'FFFE0402 H'FFFE0404 H'FFFF1907 H'FFFF1906 Access Size 8 8 8 8 8 8 8 8 8
DSFR
R/W
H'0000
H'FFFF1904
16
Rev. 2.00 Sep. 07, 2007 Page 1127 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2.1
Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized to H'00 by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7 6 5 0 R 4 0 R 3 0 R 2 0 R 1
MSTP1
0 0 R
STBY DEEP Initial value: R/W: 0 R/W 0 R/W
0 R/W
Bit 7 6
Bit Name STBY DEEP
Initial Value 0 0
R/W R/W R/W
Description Software Standby, Deep Standby Specifies transition to software standby mode or deep standby mode. 0x: Executing SLEEP instruction puts chip into sleep mode. 10: Executing SLEEP instruction puts chip into software standby mode. 11: Executing SLEEP instruction puts chip into deep standby mode.
5 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
MSTP1
0
R/W
Module Stop 1 Setting the MSTP1 bit to 1 stops supplying clock to RTC 0: RTC runs 1: Stops supplying clock to RTC
0
0
R
Reserved This bit is always read as 0. The write value should always be 0.
[Legend] x: Don't care
Rev. 2.00 Sep. 07, 2007 Page 1128 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2.2
Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR2 is initialized to H'1E by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: When writing to this register, see section 27.4, Usage Note.
7 6 5 4 3 2 1 0 MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP 10 9 8 7 6 5 4 3 Initial value: 0 0 0 1 1 1 1 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Bit 7
Bit Name MSTP10
Initial Value 0
R/W R/W
Description Module Stop 10 When the MSTP10 bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI runs. 1: Clock supply to H-UDI halted.
6
MSTP9
0
R/W
Module Stop 9 When the MSTP9 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs. 1: Clock supply to UBC halted.
5
MSTP8
0
R/W
Module Stop 8 When the MSTP8 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs. 1: Clock supply to DMAC halted.
4
MSTP7
1
R/W
Module Stop 7 When the MSTP7 bit is set to 1, the supply of the clock to the ROM-DEC is halted. 0: ROM-DEC runs. 1: Clock supply to ROM-DEC halted.
Rev. 2.00 Sep. 07, 2007 Page 1129 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
Bit 3
Bit Name MSTP6
Initial Value 1
R/W R/W
Description Module Stop 6 When the MSTP6 bit is set to 1, the supply of the clock to the RCAN-ET0 is halted. 0: RCAN-ET0 runs. 1: Clock supply to RCAN-ET0 halted.
2
MSTP5
1
R/W
Module Stop 5 When the MSTP5 bit is set to 1, the supply of the clock to the RCAN-ET1 is halted. 0: RCAN-ET1 runs. 1: Clock supply to RCAN-ET1 halted.
1
MSTP4
1
R/W
Module Stop 4 When the MSTP4 bit is set to 1, the supply of the clock to the IEB except IECKSR is halted. 0: IEB runs. 1: Clock supply to IEB except IECKSR halted.
0
MSTP3
0
R/W
Module Stop 3 When the MSTP3 bit is set to 1, the supply of the clock to the AUD-II is halted. 0: AUD-II runs. 1: Clock supply to AUD-II halted.
Rev. 2.00 Sep. 07, 2007 Page 1130 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2.3
Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR3 is initialized to H'3F by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7 Initial value: R/W: 0 R 6 0 R 5 MSTP 35 1 R/W 4 1 R 3 2 1 MSTP MSTP MSTP 33 32 31 1 1 1 R/W R/W R/W 0 1 R
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
5
MSTP35
1
R/W
Module Stop 35 When the MSTP35 bit is set to 1, the supply of the clock to the MTU2 is halted. 0: MTU2 runs. 1: Clock supply to MTU2 halted.
4
1
R
Reserved This bit is always read as 1. The write value should always be 1.
3
MSTP33
1
R/W
Module Stop 33 When the MSTP33 bit is set to 1, the supply of the clock to the TMR is halted. 0: TMR runs. 1: Clock supply to TMR halted.
2
MSTP32
1
R/W
Module Stop 32 When the MSTP32 bit is set to 1, the supply of the clock to the ADC is halted. 0: ADC runs. 1: Clock supply to ADC halted.
Rev. 2.00 Sep. 07, 2007 Page 1131 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
Bit 1
Bit Name MSTP31
Initial Value 1
R/W R/W
Description Module Stop 31 When the MSTP31 bit is set to 1, the supply of the clock to the DAC is halted. 0: DAC runs. 1: Clock supply to DAC halted.
0
1
R
Reserved This bit is always read as 1. The write value should always be 1.
27.2.4
Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR4 is initialized to H'FF by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: When writing to this register, see section 27.4, Usage Note.
7 6 5 4 3 2 1 0 MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP 47 46 45 44 43 42 41 40 1 1 1 1 Initial value: 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Bit 7
Bit Name MSTP47
Initial Value 1
R/W R/W
Description Module Stop 47 When the MSTP47 bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: SCIF0 runs. 1: Clock supply to SCIF0 halted.
6
MSTP46
1
R/W
Module Stop 46 When the MSTP46 bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: SCIF1 runs. 1: Clock supply to SCIF1 halted.
Rev. 2.00 Sep. 07, 2007 Page 1132 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
Bit 5
Bit Name MSTP45
Initial Value 1
R/W R/W
Description Module Stop 45 When the MSTP45 bit is set to 1, the supply of the clock to the SCIF2 is halted. 0: SCIF2 runs. 1: Clock supply to SCIF2 halted.
4
MSTP44
1
R/W
Module Stop 44 When the MSTP44 bit is set to 1, the supply of the clock to the SCIF3 is halted. 0: SCIF3 runs. 1: Clock supply to SCIF3 halted.
3
MSTP43
1
R/W
Module Stop 43 When the MSTP43 bit is set to 1, the supply of the clock to the SCIF4 is halted. 0: SCIF4 runs. 1: Clock supply to SCIF4 halted.
2
MSTP42
1
R/W
Module Stop 42 When the MSTP42 bit is set to 1, the supply of the clock to the SCIF5 is halted. 0: SCIF5 runs. 1: Clock supply to SCIF5 halted.
1
MSTP41
1
R/W
Module Stop 41 When the MSTP41 bit is set to 1, the supply of the clock to the SCIF6 is halted. 0: SCIF6 runs. 1: Clock supply to SCIF6 halted.
0
MSTP40
1
R/W
Module Stop 40 When the MSTP40 bit is set to 1, the supply of the clock to the SCIF7 is halted. 0: SCIF7 runs. 1: Clock supply to SCIF7 halted.
Rev. 2.00 Sep. 07, 2007 Page 1133 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2.5
Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR5 is initialized to H'FF by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: When writing to this register, see section 27.4, Usage Note.
7 6 5 MSTP MSTP MSTP 57 56 55 Initial value: 1 1 1 R/W: R/W R/W R/W Bit: 4 1 R 3 2 MSTP MSTP 53 52 1 1 R/W R/W 1 1 R 0 CKDV 3 1 R/W
Bit 7
Bit Name MSTP57
Initial Value 1
R/W R/W
Description Module Stop 57 When the MSTP57 bit is set to 1, the supply of the clock to the IIC30 is halted. 0: IIC30 runs. 1: Clock supply to IIC30 halted.
6
MSTP56
1
R/W
Module Stop 56 When the MSTP56 bit is set to 1, the supply of the clock to the IIC31 is halted. 0: IIC31 runs. 1: Clock supply to IIC31 halted.
5
MSTP55
1
R/W
Module Stop 55 When the MSTP55 bit is set to 1, the supply of the clock to the IIC32 is halted. 0: IIC32 runs. 1: Clock supply to IIC32 halted.
4
1
R
Reserved This bit is always read as 1. The write value should always be 0.
3
MSTP53
1
R/W
Module Stop 53 When the MSTP53 bit is set to 1, the supply of the clock to the SSI0 is halted. 0: SSI0 runs. 1: Clock supply to SSI0 halted.
Rev. 2.00 Sep. 07, 2007 Page 1134 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
Bit 2
Bit Name MSTP52
Initial Value 1
R/W R/W
Description Module Stop 52 When the MSTP52 bit is set to 1, the supply of the clock to the SSI1 is halted. 0: SSI1 runs. 1: Clock supply to SSI1 halted.
1
1
R
Reserved This bit is always read as 1. The write value should always be 0.
0
CKDV3
1
R/W
SSI Clock Select Selects division ratio for oversample clock input to SSI 0: x1/4 times 1: x 1 time
Rev. 2.00 Sep. 07, 2007 Page 1135 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2.6
System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM. SYSCR1 is initialized to H'FF by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an undefined value is returned when reading data or fetching an instruction from the on-chip RAM, and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1. Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAME bit. If such an instruction is not executed, the data last written to each page may not be written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be located immediately after the instruction to write to SYSCR1. If an on-chip RAM access instruction is set, normal access is not guaranteed. Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7 Initial value: R/W: 1 R 6 1 R 5 1 R 4 1 R 3 1 R 2 1 R 1 0
RAME1 RAME0
1 R/W
1 R/W
Bit 7 to 2
Bit Name
Initial Value All 1
R/W R
Description Reserved These bits are always read as 1. The write value should always be 1.
1
RAME1
1
R/W
RAM Enable 1 (corresponding RAM addresses: H'FFF84000 to H'FFF87FFF) 0: On-chip RAM disabled 1: On-chip RAM enabled
0
RAME0
1
R/W
RAM Enable 0 (corresponding RAM addresses: H'FFF80000 to H'FFF83FFF) 0: On-chip RAM disabled 1: On-chip RAM enabled
Rev. 2.00 Sep. 07, 2007 Page 1136 of 1312 REJ09B0320-0200
Section 27 Power-Down Modes
27.2.7
System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM. SYSCR2 is initialized to H'FF by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. When an RAMWE bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAMWE bit is cleared to 0, the corresponding on-chip RAM area cannot be written to. In this case, writing to the on-chip RAM is ignored. The initial value of an RAMWE bit is 1. Note that when clearing the RAMWE bit to 0 to disable the on-chip RAM, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAMWE bit. If such an instruction is not executed, the data last written to each page may not be written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be placed immediately after the instruction to write to SYSCR2. If an on-chip RAM access instruction is set, normal access is not guaranteed. Note: When writing to this register, see section 27.4, Usage Note.
Bit: 7 Initial value: R/W: 1 R 6 1 R 5 1 R 4 1 R 3 1 R 2 1 R 1 0 RAM RAM WE1 WE0 1 1 R/W R/W
Bit 7 to 2
Bit Name
Initial Value All 1
R/W R
Description Reserved These bits are always read as 1. The write value should always be 1.
1
RAMWE1
1
R/W
RAM Write Enable 1 (corresponding RAM addresses: H'FFF84000 to H'FFF87FFF) 0: On-chip RAM write disabled 1: On-chip RAM write enabled
0
RAMWE0
1
R/W
RAM Write Enable 0 (corresponding RAM addresses: H'FFF80000 to H'FFF83FFF) 0: On-chip RAM write disabled 1: On-chip RAM write enabled
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Section 27 Power-Down Modes
27.2.8
RAM Retaining Area Specifying Register (RAMKP)
RAMKP is an 8-bit readable/writable register that specifies whether or not to retain data in the corresponding on-chip RAM area in deep standby mode. RAMKP is initialized to H'00 by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. When an RAMKP bit is set to 1, data in the corresponding on-chip RAM area is retained in deep standby mode. When an RAMWE bit is cleared to 0, data in the corresponding on-chip RAM is not retained in deep standby mode. Deep standby mode is canceled by an interrupt (NMI or IRQ) or a reset (manual reset or power-on reset). However, when deep standby mode is canceled by a power-on reset, the contents in the corresponding on-chip RAM area are not retained even with the RAMKP bit set to 1.
Bit: 7 Initial value: R/W: 0 R 6 0 R 5 0 R 4 0 R 3 2 1 0 RAM RAM RAM RAM KP3 KP2 KP1 KP0 0 0 0 0 R/W R/W R/W R/W
Bit 7 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. RAM Retaining Area 3 (corresponding RAM addresses: H'FFF86000 to H'FFF87FFF) 0: Data in RAM is not retained in deep standby mode 1: Data in RAM is retained in deep standby mode RAM Retaining Area 2 (corresponding RAM addresses: H'FFF84000 to H'FFF85FFF) 0: Data in RAM is not retained in deep standby mode 1: Data in RAM is retained in deep standby mode RAM Retaining Area 1 (corresponding RAM addresses: H'FFF82000 to H'FFF83FFF) 0: Data in RAM is not retained in deep standby mode 1: Data in RAM is retained in deep standby mode RAM Retaining Area 0 (corresponding RAM addresses: H'FFF80000 to H'FFF81FFF) 0: Data in RAM is not retained in deep standby mode 1: Data in RAM is retained in deep standby mode
3
RAMKP3
0
R/W
2
RAMKP2
0
R/W
1
RAMKP1
0
R/W
0
RAMKP0
0
R/W
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Section 27 Power-Down Modes
27.2.9
Deep Standby Oscillation Settling Clock Select Register (DSCNT)
DSCNT is an 8-bit readable/writable register that selects the clock used to count the oscillation settling time when the system returns from deep standby mode. DSCNT is initialized to H'00 by a power-on reset or in deep standby mode but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Since the frequency control register for the CPG (FRQCR) is initialized in deep standby mode, the frequency of the peripheral clock (P) specified by the CKS[2:0] bits in DSCNT is determined by the FRQCR's initial value.
Bit: 7 Initial value: R/W: 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 R/W 2 1 CKS[2:0] 0 R/W 0 R/W 0
Bit 7 to 3
Bit Name
Initial Value All 0
R/W R
2 to 0
CKS[2:0]
000
R/W
Description Reserved These bits are always read as 0. The write value should always be 0. Clock Select Selects the clock used to count the oscillation settling time from among eight types clocks derived by dividing the peripheral clock (P). The oscillation settling time is calculated as follows: Oscillation settling time = 1/P x Division ratio specified by CKS[2:0] x 255 [s] The following are the oscillation settling times when the peripheral clock (P) is running at 5, 10, and 15 MHz.
Setting Clock value select 000: 001: 010: 011: 100: 101: 110: 111: 1 x P*1 1/64 x P*1 1/128 x P*1 1/256 x P*2 1/512 x P*2 1/1024 x P 1/4096 x P 1/16384 x P Oscillation settling time (ms) 5 MHz 0.05 3.26 6.53 13.06 26.11 52.22 208.90 835.58 10 MHz 0.03 1.63 3.26 6.53 13.06 26.11 104.45 417.79 15 MHz 0.02 1.09 2.18 4.35 8.70 17.41 69.63 278.53
Notes: 1. Do not use this setting. 2. Set the clock so that it is equal to or longer than the oscillation settling time 2 on return from standby (tOSC3).
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Section 27 Power-Down Modes
27.2.10 Deep Standby Cancel Source Flag Register (DSFR) DSFR is a 16-bit readable/writable register composed of two types of bits. One is the flag that confirms which interrupt canceled deep standby mode. The other is the bit that releases the retaining state of pins after canceling the deep standby mode. DSFR is initialized to H'0000 by a power-on reset by the RES pin but retains its previous value through a power-on reset caused by a WDT overflow, a manual reset, or a period in software standby mode. When deep standby mode is canceled by interrupts (NMI or IRQ) and a manual reset, this register retains the previous data although power-on reset exception handling is executed. Only word access is valid. Since interrupt inputs for the NMI and IRQ pins specified by the interrupt controller (INTC) and the pin function controller (PFC) are always detected, these interrupts set flags even during normal operation. Therefore, all flags must be cleared immediately before the transition to deep standby mode. If an interrupt occurred immediately before executing the SLEEP instruction after the flag clear, the system enters deep standby mode with the flag set again. To prevent this, clear the flag in DSFR even in interrupt exception handling routine.
Bit: 15
IOKEEP
14 0 R
13 0 R
12 0 R
11 0 R
10 0 R
9
MRESF
8
7
6
5
4
3
2
1
0
NMIF IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial value: 0 R/W: R/(W)*
0 0 0 0 0 0 0 0 0 0 R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Note: * Only 0 can be written after reading 1 to clear the flag. Even when IRQ is input after a manual reset has been accepted as a source canceling deep standby, the IRQ flag is not set.
Bit 15
Bit Name IOKEEP
Initial Value 0
R/W
Description
R/(W)* Pin State Retention Releases the retaining state of pins after canceling the deep standby mode 0: Pin state not retained [Clearing condition] * Writing 0 after reading 1 1: Retains pin state [Setting condition] * When transits to deep standby mode
14 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
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Section 27 Power-Down Modes
Bit 9
Bit Name MRESF
Initial Value 0
R/W
Description 0: No interrupt on MRES pin 1: Interrupt on MRES pin
R/(W)* MRES Flag
8
NMIF
0
R/(W)* NMI Flag 0: No interrupt on NMI pin 1: Interrupt on NMI pin
7
IRQ7F
0
R/(W)* IRQ7 Flag 0: No interrupt on IRQ7 pin 1: Interrupt on IRQ7 pin
6
IRQ6F
0
R/(W)* IRQ6 Flag 0: No interrupt on IRQ6 pin 1: Interrupt on IRQ6 pin
5
IRQ5F
0
R/(W)* IRQ5 Flag 0: No interrupt on IRQ5 pin 1: Interrupt on IRQ5 pin
4
IRQ4F
0
R/(W)* IRQ4 Flag 0: No interrupt on IRQ4 pin 1: Interrupt on IRQ4 pin
3
IRQ3F
0
R/(W)* IRQ3 Flag 0: No interrupt on IRQ3 pin 1: Interrupt on IRQ3 pin
2
IRQ2F
0
R/(W)* IRQ2 Flag 0: No interrupt on IRQ2 pin 1: Interrupt on IRQ2 pin
1
IRQ1F
0
R/(W)* IRQ1 Flag 0: No interrupt on IRQ1 pin 1: Interrupt on IRQ1 pin
0
IRQ0F
0
R/(W)* IRQ0 Flag 0: No interrupt on IRQ0 pin 1: Interrupt on IRQ0 pin
Note:
*
Only 0 can be written after reading 1 to clear the flag. Even when IRQ is input after a manual reset has been accepted as a source canceling deep standby, the IRQ flag is not set.
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Section 27 Power-Down Modes
27.3
27.3.1 (1)
Operation
Sleep Mode
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin. (2) Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, H-UDI, IRQ, PINT, and on-chip peripheral module), a bus error, or a reset (manual reset or power-on reset). * Canceling with an interrupt When an NMI, H-UDI, IRQ, PINT, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the priority level of the generated interrupt is equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU, or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt request is not accepted and sleep mode is not canceled. * Canceling with a bus error When a bus error occurs, sleep mode is canceled and bus error exception handling is executed. * Canceling with a reset Sleep mode is canceled by a power-on reset or a manual reset.
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Section 27 Power-Down Modes
27.3.2 (1)
Software Standby Mode
Transition to Software Standby Mode
The LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit and DEEP bit in STBCR are 1 and 0 respectively. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also halts in clock mode 0 or 2. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. As for the states of on-chip peripheral module registers in software standby mode, see section 30.3, Register States in Each Operating Mode. The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely reflected in the SLEEP instruction. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. 2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY and DEEP bits in STBCR to 1 and 0 respectively, read STBCR. Then, execute a SLEEP instruction. (2) Canceling Software Standby Mode
Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or poweron reset). In clock modes 0 and 2, a clock signal starts to be output from the CKIO pin. * Canceling with an interrupt When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC)) is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation settling counter (WDT) used to count the oscillation settling time.
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Section 27 Power-Down Modes
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer control/status register (WTCSR) of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in case of IRQ) is started. However, when the IRQ interrupt priority level is lower than the interrupt mask level set in the status register (SR) of the CPU, the interrupt request is not accepted and software standby mode is not canceled. When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation settling time. The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until software standby mode is canceled. When software standby mode is canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from software standby mode (when the clock is initiated after the oscillation settling). When software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation settling) (This is the same with the IRQ pin.) * Canceling with a reset When the RES pin is driven low, software standby mode is canceled and the LSI enters the power-on reset state. After that, if the RES pin is driven high, the power-on reset exception handling is started. When the MRES pin is driven low, software standby mode is canceled and the LSI enters the manual reset state. After that, if the MRES pin is driven high, the manual reset exception handling is started. Keep the RES or MRES pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin in clock mode 0 or 2. (3) Note on Making a Transition To Software Standby Mode
If the SLEEP instruction is executed to make a transition to software standby mode during transfer by the DMAC, the DMAC stops its operation without waiting for the completion of the transfer. Thus, the DMA transfer is not guaranteed. Therefore, when making a transition to software standby mode, wait for the completion of the DMA transfer or stop the DMA transfer to execute the SLEEP instruction.
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Section 27 Power-Down Modes
27.3.3
Software Standby Mode Application Example
This example describes a transition to software standby mode on the falling edge of the NMI signal, and cancellation on the rising edge of the NMI signal. The timing is shown in figure 27.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine, the STBY and DEEP bits in STBCR are set to 1 and 0 respectively, and a SLEEP instruction is executed, software standby mode is entered. Thereafter, software standby mode is canceled when the NMI pin is changed from low to high level.
Oscillator
CK
NMI pin
NMIE bit
STBY bit
LSI state
Program execution
NMI exception handling
Exception service routine
Software standby mode
Oscillation settling time
NMI exception handling
Figure 27.1 NMI Timing in Software Standby Mode (Application Example)
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Section 27 Power-Down Modes
27.3.4 (1)
Deep Standby Mode
Transition to Deep Standby Mode
The LSI switches from a program execution state to deep standby mode by executing the SLEEP instruction when the STBY bit and DEEP bit in STBCR are set to 1. In deep standby mode, not only the CPU, clocks, and on-chip peripheral modules but also power supply is turned off excluding the on-chip RAM retaining area specified by the RAMKP3 to RAMKP0 bits in the RAMKP register and RTC. This can significantly reduce power consumption. Therefore, data in the registers of the CPU, cache, and on-chip peripheral modules are not retained. Pin state values immediately before the transition to deep standby mode can be retained. The CPU takes one cycle to finish writing to DSFR, and then executes processing for the next instruction. However, it actually takes one or more cycles to write. Therefore, execute a SLEEP instruction after reading DSFR to have the values written to DSFR by the CPU to be definitely reflected in the SLEEP instruction. The procedure for switching to deep standby mode is as follows. Figure 27.2 also shows its flowchart. 1. Set the RAMKP3 to RAMKP0 bits in the RAMKP register for the corresponding on-chip RAM retaining area. 2. Execute read and write of an arbitrary but the same address for each page in the retaining RAM area. When this is not executed, data last written may not be stored in the on-chip RAM. If there is a write to the on-chip RAM after this time, execute this processing after the last write to the on-chip RAM. 3. Set the CKS[2:0] bits in the DSCNT register so that the initial value of FRQCR in the CPG becomes larger than the oscillation settling time. 4. Set the STBY and DEEP bits in the STBCR register to 1. 5. Read out the DSFR register after clearing the flag in the DSFR register. Then execute the SLEEP instruction.
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Section 27 Power-Down Modes
Program executing state
Set INTC register as needed
Set RAMKP bit in RAMKP as needed
Execute read and write of an arbitrary but the same address for each page in the retaining RAM area.
Set the bits CKS2 to CKS0 in DSCNT so that the initial value of FRQCR in the CPG become larger than the oscillation settling time.
Set the STBY and DEEP bits in STBCR to 1.
Read STBCR
Clear the flag in DSFR
Interrupt processing routine
Clear the flag in DSFR Execute SLEEP instruction Execute RTE instruction
Transition to deep standby mode
Figure 27.2 Flowchart of Transition to Deep Standby Mode
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Section 27 Power-Down Modes
(2)
Canceling Deep Standby Mode
Deep standby mode is canceled by interrupts (NMI or IRQ) or a reset (manual reset or power-on reset). However, IRQ is canceled only by PE7 to PE4 and PC25 to PC22. To cancel deep standby mode by interrupt NMI or IRQ, a power-on reset exception handling instead of an interrupt exception handling is executed. In the same way, a power-on reset exception handling is executed by a power-on reset. Figure 27.3 shows the flowchart of canceling deep standby mode.
Deep standby mode
Interrupt detection (NMI, IRQ)
Reset detection (MRES, RES)
Oscillation settling time count by DSCNT
Keep reset pins (MRES, RES) low during oscillation settling time
Power-on reset exception handling routine
DSFR flag check
No Power-on reset? Reconfiguration of peripheral functions*
Yes To power-on reset exception handling
Clear IOKEEP bit in DSFR
Back to previous state before deep standby mode Note: * Peripheral functions include every function such as CPG, INTC, BSC, I/O ports, PFC, and peripheral modules
Figure 27.3 Flowchart of Canceling Deep Standby Mode
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Section 27 Power-Down Modes
* Canceling with an interrupt When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling edge or rising edge of an IRQ pin (IRQ7 to IRQ0: PE7 to PE4 and PC25 to PC22) (selected by the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC)) is detected, clock oscillation is started after the wait time for the oscillation settling time. This clock pulse is supplied only to the oscillation settling counter (DSCNT) used to count the oscillation settling time. After the elapse of the time set in the clock select bits (CKS[2:0]) in DSCNT before the transition to deep standby mode, an overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow. Deep standby mode is thus cleared and reset exception handling is started. When canceling deep standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0] bits so that the overflow period will be equal to or longer than the oscillation settling time. The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until deep standby mode is canceled. When deep standby mode is canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters deep standby mode (when the clock pulse stops) and should be low when the CPU returns from deep standby mode (when the clock is initiated after the oscillation settling). When deep standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters deep standby mode (when the clock pulse stops) and should be high when the CPU returns from deep standby mode (when the clock is initiated after the oscillation settling). (This is the same with the IRQ pin.) * Canceling with a reset When the RES or MRES pin is driven low, this LSI enters the power-on reset state and deep standby mode is canceled. Keep the RES or MRES pin low until the clock oscillation settles. When deep standby mode is canceled by the RES pin, the contents in the on-chip RAM area are not retained.
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Section 27 Power-Down Modes
(3)
Operation after Canceling Deep Standby Mode
When deep standby mode is canceled by interrupts (NMI or IRQ) or a manual reset, the deep standby cancel source flag register (DSFR) can be used to confirm which interrupt has canceled the mode. Pins retain the state immediately before the transition to deep standby mode. However, in canceling deep standby mode, only the pins in buses listed in the table 27.3 can fetch programs while canceling pin states. Pins other than those retain the pin states after canceling deep standby mode, in which DSFR can confirm which interrupt has triggered returning to deep standby mode. Reconfiguration of peripheral functions is required to return to the previous state of deep standby mode. Peripheral functions include every function such as CPG, INTC, BSC, I/O ports, PFC, and peripheral modules. After the reconfiguration, pin-retaining state can be canceled by reading 1 in the IOKEEP bit of DSFR then writing 0 to it. Table 27.3 Pin States in Different Modes
Operation Mode (1) (External 8_bit Bus Initiated) PA[23:0] PB[7:0] PC[9:8], PC[0] CKIO Operation Mode (2) (External 16_bit Bus Initiated) PA[23:0] PB[15:0] PC[10:8], PC[0] CKIO Operation Mode (3) (External 32_bit Bus Initiated) PA[23:0] PB[31:0] PC[12:8], PC[0] CKIO
(4)
Note on Making a Transition To Deep Standby Mode
If the SLEEP instruction is executed to make a transition to deep standby mode during transfer by the DMAC, the DMAC stops its operation without waiting for the completion of the transfer. Thus, the DMA transfer is not guaranteed. Therefore, when making a transition to deep standby mode, wait for the completion of the DMA transfer or stop the DMA transfer to execute the SLEEP instruction.
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Section 27 Power-Down Modes
27.3.5 (1)
Module Standby Function
Transition to Module Standby Function
Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. Disable a module before placing it in the module standby mode. In addition, do not access the module's registers while it is in the module standby state. The register states are the same as those in software standby mode. However, the state of DAC registers are exceptional. In the DAC, all registers retain their previous values in software standby mode, but are initialized in module standby mode. (2) Canceling Module Standby Function
The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on reset (only possible for RTC, H-UDI, UBC, DMAC, and AUD-II). When taking a module out of the module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to confirm that it has been cleared to 0.
27.4
27.4.1
Usage Note
Note on Setting Registers
When writing to the registers related to power-down modes, note the following. When writing to the register related to power-down modes, the CPU, after executing a write instruction, executes the next instruction without waiting for the write operation to complete. Therefore, to reflect the change specified by writing to the register while the next instruction is executed, insert a dummy read of the same register between the register write instruction and the next instruction. 27.4.2 Note on Canceling Standby Mode when an External Clock is being Input
When release from standby mode is initiated by an interrupt (NMI or IRQ) while an external clock from the EXTAL pin or CKIO pin is in use, make sure that the external clock is being input before input of the interrupt. If this is not the case, correct counting of the oscillation settling time will not be possible.
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Section 27 Power-Down Modes
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Section 28 User Debugging Interface (H-UDI)
Section 28 User Debugging Interface (H-UDI)
This LSI incorporates a user debugging interface (H-UDI) for emulator support.
28.1
Features
The user debugging interface (H-UDI) has reset and interrupt request functions. The H-UDI in this LSI is used for emulator connection. Refer to the emulator manual for the method of connecting the emulator. Figure 28.1 shows a block diagram of the H-UDI.
UDTDI
SDBPR
Shift register
SDIR
UDTDO
MUX
UDTCK UDTMS UDTRST
TAP control circuit
Decoder
Local bus
[Legend] SDBPR: SDIR:
Bypass register Instruction register
Figure 28.1 Block Diagram of H-UDI
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Section 28 User Debugging Interface (H-UDI)
28.2
Input/Output Pins
Table 28.1 Pin Configuration
Pin Name H-UDI serial data input/output clock pin Symbol UDTCK* I/O Input Function Data is serially supplied to the H-UDI from the data input pin (UDTDI), and output from the data output pin (UDTDO), in synchronization with this clock. Fix high when not used. The state of the TAP control circuit is determined by changing this signal in synchronization with UDTCK. For the protocol, see figure 28.2. Fix high when not used. Input is accepted asynchronously with respect to UDTCK, and when low, the H-UDI is reset. UDTRST must be low for oscillation settling time when power is turned on. See section 28.4.2, Reset Types, for more information. Data transfer to the H-UDI is executed by changing this signal in synchronization with UDTCK. Fix high when not used. Data read from the H-UDI is executed by reading this pin in synchronization with UDTCK. The initial value of the data output timing is the UDTCK falling edge. This can be changed to the UDTCK rising edge by inputting the UDTDO change timing switch command to SDIR. See section 28.4.3, UDTDO Output Timing, for more information. Fix high.
Mode select input pin
UDTMS*
Input
H-UDI reset input pin
UDTRST*
Input
H-UDI serial data input pin H-UDI serial data output pin
UDTDI*
Input
UDTDO
Output
ASE mode select pin Note: *
ASEMD
Input
The pin with the pull-up function.
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Section 28 User Debugging Interface (H-UDI)
28.3
Register Descriptions
The H-UDI has the following registers. Table 28.2 Register Configuration
Register Name Bypass register Instruction register Abbreviation SDBPR SDIR R/W R Initial Value H'EFFD Address H'FFFD9000 Access Size 16
28.3.1
Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS mode, SDBPR is connected between H-UDI pins UDTDI and UDTDO. The initial value is undefined.
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Section 28 User Debugging Interface (H-UDI)
28.3.2
Instruction Register (SDIR)
SDIR is a 16-bit read-only register. It is initialized by UDTRST assertion, in the TAP test-logicreset state or in deep standby mode, and can be written to by the H-UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in this register. The initial value is H'EFFD.
Bit: 15 14 13 12 11 10 9 8 7 1* R 1* R 1* R 1 R 6 1 R 5 1 R 4 1 R 3 1 R 2 1 R 1 0 R 0 1 R
TI[7:0] Initial value: R/W: Note: * 1* R 1* R 1* R 0* R 1* R
The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
Bit 15 to 8
Bit Name TI[7:0]
Initial Value 11101111*
R/W R
Description Test Instruction The H-UDI instruction is transferred to SDIR by a serial input from UDTDI. For commands, see table 28.3.
7 to 2 1 0 Note: *

All 1 0 1
R R R
Reserved These bits are always read as 1. Reserved This bit is always read as 0. Reserved This bit is always read as 1.
The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
Table 28.3 H-UDI Commands
Bits 15 to 8 TI7 0 0 1 1 1 TI6 1 1 0 0 1 TI5 1 1 0 1 1 TI4 0 1 1 1 1 TI3 -- -- 1 -- -- TI2 -- -- 1 -- -- TI1 -- -- 0 -- -- TI0 -- -- 0 -- -- Description H-UDI reset negate H-UDI reset assert UDTDO change timing switch H-UDI interrupt BYPASS mode Reserved
Other than above
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Section 28 User Debugging Interface (H-UDI)
28.4
28.4.1
Operation
TAP Controller
Figure 28.2 shows the internal states of the TAP controller.
1
Test -logic-reset 0 1 1 Select-DR 0 Select-IR 0 1 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 Exit1-IR 0 Pause-IR 1 0 0 Capture-IR 0 Shift-IR 1 1 0 1
0
Run-test/idle
1
Figure 28.2 TAP Controller State Transitions Note: The transition condition is the UDTMS value at the rising edge of UDTCK. The UDTDI value is sampled at the rising edge of UDTCK; shifting occurs at the falling edge of UDTCK. For details on change timing of the UDTDO value, see section 28.4.3, UDTDO Output Timing. The UDTDO is at high impedance, except with shift-DR and shift-IR states. There is a transition to test-logic-reset asynchronously with UDTCK by UDTRST assertion or deep standby mode.
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Section 28 User Debugging Interface (H-UDI)
28.4.2
Reset Types
Table 28.4 Reset Types
ASEMD* H RES L UDTRST L H H Note: * Fix ASEMD to high. L H Chip State Power-on reset and H-UDI reset Power-on reset H-UDI reset only Normal operation
28.4.3
UDTDO Output Timing
The initial value of the UDTDO change timing is to perform data output from the UDTDO pin on the UDTCK falling edge. However, setting a UDTDO change timing switch command in SDIR via the H-UDI pin and passing the Update-IR state synchronizes the UDTDO change timing to the UDTCK rising edge. Hereafter, to synchronize the UDTDO change timing with the UDTCK falling edge, the UDTRST pin must be asserted simultaneously with a power-on reset or deep standby mode must be entered. In the case of a power-on reset by the RES pin, the LSI falls in reset state for a certain period after the RES pin negation. Therefore, when the UDTRST pin is asserted immediately after the RES pin negation, a UDTDO change timing switch command is cleared and the UDTDO change timing becomes synchronous with the output of UDTCK falling edge. To prevent this, at least 20 tcyc must be set between the change timings of the RES pin and UDTRST pin.
UDTCK
UDTDO (after execution of UDTDO change timing switch command) UDTDO (initial value)
tTDOD
tTDOD
Figure 28.3 H-UDI Data Transfer Timing
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Section 28 User Debugging Interface (H-UDI)
28.4.4
H-UDI Reset
An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by setting an H-UDI reset negate command. The required time between the H-UDI reset assert command and H-UDI reset negate command is the same as time for keeping the RES pin low to apply a power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Fetch the initial values of PC and SR from the exception handling vector table
Figure 28.4 H-UDI Reset 28.4.5 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in fetching the exception service routine start address from the exception handling vector table, jumping to that address, and starting program execution from that address. This interrupt request has a fixed priority level of 15. H-UDI interrupts are accepted in sleep mode, but not in software standby or deep standby mode.
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Section 28 User Debugging Interface (H-UDI)
28.5
Usage Notes
1. An H-UDI command, once set, will not be modified as long as another command is not set again from the H-UDI. If the same command is to be set continuously, the command must be set after a command (BYPASS mode, etc.) that does not affect chip operations is once set. 2. In software standby mode or H-UDI module standby state, all of the functions in the H-UDI cannot be used. To retain the TAP status before and after software standby mode or H-UDI module standby state, keep UDTCK high before entering software standby mode or H-UDI module standby state. 3. In deep standby mode, all of the functions in the H-UDI cannot be used. H-UDI is initialized in deep standby mode. 4. Make sure to allow 20 tcyc or more between the signal change timing of the RES and UDTRST pins. 5. When starting the TAP controller after the negation of the UDTRST pin, make sure to allow 200 ms or more after the negation.
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Section 29 Advanced User Debugger II (AUD-II)
Section 29 Advanced User Debugger II (AUD-II)
The AUD-II offers functions that support user program debugging with the LSI mounted and operated in actual performance. Use of the AUD-II simplifies the construction of a simple emulator, with functions such as monitoring/tuning of on-chip RAM data.
29.1
Features
The AUD-II can be used in RAM monitor mode by setting AUDMD. RAM monitor mode: * Functions to read/write modules connected to internal/external buses (except cache and H-UDI) * Outputs data corresponding to an address that is externally written to AUDATA * Transmits data to the address in AUDATA to which address and data are written
29.2
Input/Output Pins
Table 29.1 Pin Configuration
Pin Name AUD reset AUD sync signal AUD clock AUD mode AUD data Symbol AUDRST AUDSYNC AUDCK AUDMD AUDATA[3:0] Function AUD reset input Data start position identification signal input External clock input Mode select input (H) Monitor address input and data input/output
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Section 29 Advanced User Debugger II (AUD-II)
(1) Description of Pins Table 29.2 Description of Pins
Pin AUDMD Function The mode is selected by changing the input level at this pin. Low: Setting prohibited High: RAM monitor mode The input at this pin should be changed when AUDRST is low. AUDRST When this pin is driven low, the AUD enters the reset state and the AUD's internal buffers and logic are reset. When AUDRST goes high again after the AUDMD level settles, the AUD starts operating in the selected mode. This pin is for external clock input. Input the clock to be used for debugging. Note that the available frequency is up to B/2. AUDSYNC AUD Bus Command Valid Signal 1: Read data is output 0: Inputs write address, data, DIR command Note: Do not assert this pin until commands are input to AUDATA from outside and necessary data is prepared. For details, see the protocol as described later. AUDATA[3:0] The following data is output in time-sharing mode. * * * AUD bus command Address Data
AUDCK
When a command is input from outside, data is output after Ready is transmitted. The output starts after AUDSYNC is negated. For details, see the protocol as described later.
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Section 29 Advanced User Debugger II (AUD-II)
29.3
RAM Monitor Mode
In this mode, all the modules connected to this LSI's internal or external bus can be read and written to (except cache and H-UDI), allowing RAM monitoring and tuning to be carried out. 29.3.1 Communication Protocol
The AUD-II latches the AUDATA input when AUDSYNC is asserted. The following AUDATA input format should be used.
0000
DIR
A3 to A0
A31 to A28
D3 to D0
Dn to Dn-3
Command
Address
Data (in case of write only) B write: n = 7 W write: n = 15 L write: n = 31 Bit 3 Bit 2 Bit 1 Bit 0
Fixed at 1 0: Read 1: Write
00: Byte 01: Word 10: Longword
Spare bits (4 bits): B'0000
Figure 29.1 AUDATA Input Format
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Section 29 Advanced User Debugger II (AUD-II)
29.3.2
Operation
Operation starts in RAM monitor mode when AUDRST is asserted, AUDMD is driven high, and then AUDRST is negated. Figure 29.2 shows an example of a read operation, and figure 29.3 shows an example of a write operation. When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address, or data (writing only) is input in the format shown in figure 29.1, execution of read/write access to the specified address is started. During internal execution, the AUD returns Not Ready (B'0000). When execution is completed, the Ready flag (B'0001) is returned (figures 29. 2 and 29. 3). Table 29.3 shows the Ready flag format. In a read, data of the specified size is output when AUDSYNC is negated following detection of this flag (figure 29. 2). If a command other than the above is input in DIR, the AUD-II treats this as a command error, disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the command specified in DIR causes a bus error, the AUD-II disables processing and sets bit 2 in the Ready flag to 1 (figure 29. 4). Bus error conditions are shown below. 1. Word access to address 4n+1 or 4n+3 2. Longword access to address 4n+1, 4n+2, or 4n+3 Table 29.3 Ready Flag Format
Bit 3 Fixed at 0 Bit 2 0: Normal status 1: Bus error Bit 1 0: Normal status 1: Command error Bit 0 0: Not ready 1: Ready
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Section 29 Advanced User Debugger II (AUD-II)
AUDCK
AUDSYNC
Input/output changeover
AUDATA[3:0]
0000 1000 A3 to A0 DIR Input
A31 to A28
0000 Not Ready
0001 Ready
0001 0001 D3 to D0 Ready Ready Output
D7 to D4
Figure 29.2 Example of Read Operation (Byte Read)
AUDCK
AUDSYNC
Input/output changeover
AUDATA[3:0]
0000 1110 A3 to A0 DIR Input
A31 to A28
D3 to D0
D31 to D28
0000 Not Ready
0001 0001 0001 Ready Ready Ready Output
Figure 29.3 Example of Write Operation (Longword Write)
AUDCK
AUDSYNC
Input/output changeover
AUDATA[3:0]
0000 1010 A3 to A0 DIR
A31 to A28
0000 Not Ready
0101 Ready (Bus error)
0101 0101 Ready Ready (Bus error) (Bus error)
Input
Output
Figure 29.4 Example of Error Occurrence (Longword Read)
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Section 29 Advanced User Debugger II (AUD-II)
29.3.3 (1)
Usage Notes (RAM Monitor Mode)
Guidelines for initialization of the RAM monitor mode
The buffers in this debugger and the processing status are initialized under the following conditions. * * * * (2) Power-on reset When the AUDRST pin is driven low Module standby Deep standby mode Guidelines for AUDCK
* AUDCK is for inputting the external clock. Input the clock to satisfy B/2 AUDCK. (3) Other Limitations
* Do not negate AUDSYNC until the command is input to AUDATA and the Ready is returned. * The RAM monitor functions in sleep mode but is not available in software standby or deep standby mode.
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Section 30 List of Registers
Section 30 List of Registers
The address map gives information on the on-chip I/O registers and is configured as described below. 1. * * * Register Addresses (address order) Registers are described by functional module, in order of the corresponding section numbers. Access to reserved addresses that are not described in this register address list is prohibited. When addresses consist of 16 or 32 bits, the addresses of the MSBs are given when big-endian mode is selected.
2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (address order). * Reserved bits are indicated by - in the bit name. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 or 32 bits, the bits are given from the MSB side. The listing order of bytes is based on big-endian mode. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (address order). * For the initial state of each bit, refer to the description of the register in the corresponding section. * The register states described are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
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Section 30 List of Registers
30.1
Register Addresses (Address Order)
Entries under Access Size indicate numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access.
Register Name ROM-DEC enable control register Abbreviation CROMEN Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'E8000000 H'E8000001 H'E8000002 H'E8000003 H'E8000005 H'E8000006 H'E8000007 H'E8000008 H'E8000009 H'E800000B H'E800000C H'E800000D H'E800000E H'E8000014 H'E8000015 H'E8000016 H'E8000018 H'E8000019 H'E800001A H'E800001B Module ROM-DEC Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Sync code-based synchronization control register CROMSY0 Decoding mode control register EDC/ECC check control register Automatic decoding stop control register Decoding option setting control register HEAD20 to HEAD22 representation control register Sync code status register Post-ECC header error status register Post-ECC subheader error status register Header/subheader validity check status register Mode determination and link sector detection status register ECC/EDC error status register Buffer status register Decoding stoppage source status register Buffer overflow status register Pre-ECC correction header: minutes data register Pre-ECC correction header: seconds data register Pre-ECC correction header: frames data register Pre-ECC correction header: mode data register CROMCTL0 CROMCTL1 CROMCTL3 CROMCTL4 CROMCTL5 CROMST0 CROMST1 CROMST3 CROMST4 CROMST5 CROMST6 CBUFST0 CBUFST1 CBUFST2 HEAD00 HEAD01 HEAD02 HEAD03
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Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Register Name Pre-ECC correction subheader: file number data register Pre-ECC correction subheader: channel number data register Pre-ECC correction subheader: sub-mode data register Pre-ECC correction subheader: data type data register Pre-ECC correction subheader: file number data register Pre-ECC correction subheader: channel number data register Pre-ECC correction subheader: sub-mode data register Pre-ECC correction subheader: data type data register Post-ECC correction header: minutes data register Post-ECC correction header: seconds data register Post-ECC correction header: frames data register Post-ECC correction header: mode data register Post-ECC correction subheader: file number data register Post-ECC correction subheader: channel number data register Post-ECC correction subheader: sub-mode data register Post-ECC correction subheader: data type data register Post-ECC correction subheader: file number data register Post-ECC correction subheader: channel number data register Post-ECC correction subheader: sub-mode data register Post-ECC correction subheader: data type data register
Abbreviation SHEAD00 SHEAD01 SHEAD02 SHEAD03 SHEAD04 SHEAD05 SHEAD06 SHEAD07 HEAD20 HEAD21 HEAD22 HEAD23 SHEAD20 SHEAD21 SHEAD22 SHEAD23 SHEAD24 SHEAD25 SHEAD26 SHEAD27
Address H'E800001C H'E800001D H'E800001E H'E800001F H'E8000020 H'E8000021 H'E8000022 H'E8000023 H'E8000024 H'E8000025 H'E8000026 H'E8000027 H'E8000028 H'E8000029 H'E800002A H'E800002B H'E800002C H'E800002D H'E800002E H'E800002F
Module ROM-DEC
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Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access Size 8 8 8 8 8 8 8 8 8 8 8 Read: 16 Write: 32 Read: 16 Write: 32 16
Register Name Automatic buffering setting control register Automatic buffering start sector setting: minutes control register Automatic buffering start sector setting: seconds control register Automatic buffering start sector setting: frames control register ISY interrupt source mask control register CD-ROM decoder reset control register CD-ROM decoder reset status register SSI data control register Interrupt flag register Interrupt source mask control register Buffer control register CD-ROM decoder stream data input register CD-ROM decoder stream data input register CD-ROM decoder stream data input register CD-ROM decoder stream data input register CD-ROM decoder stream data output register CD-ROM decoder stream data output register Bus monitor enable register Bus monitor status register 1 Bus monitor status register 2 Bus error control register CS0 control register CS0 recovery cycle setting register CS1 control register CS1 recovery cycle setting register CS2 control register CS2 recovery cycle setting register CS3 control register CS3 recovery cycle setting register CS4 control register CS4 recovery cycle setting register
Abbreviation CBUFCTL0 CBUFCTL1 CBUFCTL2 CBUFCTL3 CROMST0M ROMDECRST RSTSTAT SSI INTHOLD INHINT RINGBUFCTL STRMDIN0 STRMDIN1 STRMDIN2 STRMDIN3 STRMDOUT0 STRMDOUT1 SYCBEEN SYCBESTS1 SYCBESTS2 SYCBESW CS0CNT CS0REC CS1CNT CS1REC CS2CNT CS2REC CS3CNT CS3REC CS4CNT CS4REC
Address H'E8000040 H'E8000041 H'E8000042 H'E8000043 H'E8000045 H'E8000100 H'E8000101 H'E8000102 H'E8000108 H'E8000109 H'E800010C H'E8000200 H'E8000201 H'E8000202 H'E8000203 H'E8000204 H'E8000205 H'FF400000 H'FF400004 H'FF400008 H'FF40000C H'FF420000 H'FF420008 H'FF420010 H'FF420018 H'FF420020 H'FF420028 H'FF420030 H'FF420038 H'FF420040 H'FF420048
Module ROM-DEC
Bus Monitor
8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
BSC
8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
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Section 30 List of Registers
Number of Bits 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
Register Name CS5 control register CS5 recovery cycle setting register CS6 control register CS6 recovery cycle setting register SDRAMC0 control register SDRAMC1 control register CS0 mode register CS0 wait control register 1 CS0 wait control register 2 CS1 mode register CS1 wait control register 1 CS1 wait control register 2 CS2 mode register CS2 wait control register 1 CS2 wait control register 2 CS3 mode register CS3 wait control register 1 CS3 wait control register 2 CS4 mode register CS4 wait control register 1 CS4 wait control register 2 CS5 mode register CS5 wait control register 1 CS5 wait control register 2 CS6 mode register CS6 wait control register 1 CS6 wait control register 2 SDRAM refresh control register 0 SDRAM refresh control register 1 SDRAM initialized register 0 SDRAM initialized register 1 SDRAM power down control register
Abbreviation CS5CNT CS5REC CS6CNT CS6REC SDC0CNT SDC1CNT CSMOD0 CS1WCNT0 CS2WCNT0 CSMOD1 CS1WCNT1 CS2WCNT1 CSMOD2 CS1WCNT2 CS2WCNT2 CSMOD3 CS1WCNT3 CS2WCNT3 CSMOD4 CS1WCNT4 CS2WCNT4 CSMOD5 CS1WCNT5 CS2WCNT5 CSMOD6 CS1WCNT6 CS2WCNT6 SDRFCNT0 SDRFCNT1 SDIR0 SDIR1 SDPWDCNT
Address H'FF420050 H'FF420058 H'FF420060 H'FF420068 H'FF420100 H'FF420110 H'FF421000 H'FF421004 H'FF421008 H'FF421010 H'FF421014 H'FF421018 H'FF421020 H'FF421024 H'FF421028 H'FF421030 H'FF421034 H'FF421038 H'FF421040 H'FF421044 H'FF421048 H'FF421050 H'FF421054 H'FF421058 H'FF421060 H'FF421064 H'FF421068 H'FF422000 H'FF422004 H'FF422008 H'FF42200C H'FF422010
Module BSC
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Section 30 List of Registers
Number of Bits 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access Size 8, 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 16, 32 8, 16, 32 8, 16, 32 DMAC 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Register Name SDRAM deep power down control register SDRAM0 address register SDRAM0 timing register SDRAM0 mode register SDRAM1 address register SDRAM1 timing register SDRAM1 mode register SDRAM status register SDRAM clock stop control signal setting register DMA current source address register 0 DMA current destination address register 0 DMA current byte count register 0 DMA mode register 0 DMA current source address register 1 DMA current destination address register 1 DMA current byte count register 1 DMA mode register 1 DMA current source address register 2 DMA current destination address register 2 DMA current byte count register 2 DMA mode register 2 DMA current source address register 3 DMA current destination address register 3 DMA current byte count register 3 DMA mode register 3 DMA current source address register 4 DMA current destination address register 4 DMA current byte count register 4 DMA mode register 4 DMA current source address register 5 DMA current destination address register 5
Abbreviation SDDPWDCNT SD0ADR SD0TR SD0MOD SD1ADR SD1TR SD1MOD SDSTR SDCKSCNT DMCSADR0 DMCDADR0 DMCBCT0 DMMOD0 DMCSADR1 DMCDADR1 DMCBCT1 DMMOD1 DMCSADR2 DMCDADR2 DMCBCT2 DMMOD2 DMCSADR3 DMCDADR3 DMCBCT3 DMMOD3 DMCSADR4 DMCDADR4 DMCBCT4 DMMOD4 DMCSADR5 DMCDADR5
Address H'FF422014 H'FF422020 H'FF422024 H'FF422028 H'FF422040 H'FF422044 H'FF422048 H'FF4220E4 H'FF4220E8 H'FF460000 H'FF460004 H'FF460008 H'FF46000C H'FF460010 H'FF460014 H'FF460018 H'FF46001C H'FF460020 H'FF460024 H'FF460028 H'FF46002C H'FF460030 H'FF460034 H'FF460038 H'FF46003C H'FF460040 H'FF460044 H'FF460048 H'FF46004C H'FF460050 H'FF460054
Module BSC
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Section 30 List of Registers
Number of Bits 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Register Name DMA current byte count register 5 DMA mode register 5 DMA current source address register 6 DMA current destination address register 6 DMA current byte count register 6 DMA mode register 6 DMA current source address register 7 DMA current destination address register 7 DMA current byte count register 7 DMA mode register 7 DMA reload source address register 0 DMA reload destination address register 0 DMA reload byte count register 0 DMA reload source address register 1 DMA reload destination address register 1 DMA reload byte count register 1 DMA reload source address register 2 DMA reload destination address register 2 DMA reload byte count register 2 DMA reload source address register 3 DMA reload destination address register 3 DMA reload byte count register 3 DMA reload source address register 4 DMA reload destination address register 4 DMA reload byte count register 4 DMA reload source address register 5 DMA reload destination address register 5 DMA reload byte count register 5 DMA reload source address register 6 DMA reload destination address register 6 DMA reload byte count register 6 DMA reload source address register 7 DMA reload destination address register 7 DMA reload byte count register 7
Abbreviation DMCBCT5 DMMOD5 DMCSADR6 DMCDADR6 DMCBCT6 DMMOD6 DMCSADR7 DMCDADR7 DMCBCT7 DMMOD7 DMRSADR0 DMRDADR0 DMRBCT0 DMRSADR1 DMRDADR1 DMRBCT1 DMRSADR2 DMRDADR2 DMRBCT2 DMRSADR3 DMRDADR3 DMRBCT3 DMRSADR4 DMRDADR4 DMRBCT4 DMRSADR5 DMRDADR5 DMRBCT5 DMRSADR6 DMRDADR6 DMRBCT6 DMRSADR7 DMRDADR7 DMRBCT7
Address H'FF460058 H'FF46005C H'FF460060 H'FF460064 H'FF460068 H'FF46006C H'FF460070 H'FF460074 H'FF460078 H'FF46007C H'FF460200 H'FF460204 H'FF460208 H'FF460210 H'FF460214 H'FF460218 H'FF460220 H'FF460224 H'FF460228 H'FF460230 H'FF460234 H'FF460238 H'FF460240 H'FF460244 H'FF460248 H'FF460250 H'FF460254 H'FF460258 H'FF460260 H'FF460264 H'FF460268 H'FF460270 H'FF460274 H'FF460278
Module DMAC
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Section 30 List of Registers
Number of Bits 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 32 Access Size 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 UBC 32 32 32 32 32 32 32 32 16 16 32
Register Name DMA control register A0 DMA control register B0 DMA control register A1 DMA control register B1 DMA control register A2 DMA control register B2 DMA control register A3 DMA control register B3 DMA control register A4 DMA control register B4 DMA control register A5 DMA control register B5 DMA control register A6 DMA control register B6 DMA control register A7 DMA control register B7 DMA activation control register DMA interrupt control register DMA common interrupt control register DMA interrupt status register DMA transfer end detection register DMA arbitration status register Break address register_0 Break address mask register_0 Break data register_0 Break data mask register_0 Break address register_1 Break address mask register_1 Break data register_1 Break data mask register_1 Break bus cycle register_0 Break bus cycle register_1 Break control register
Abbreviation DMCNTA0 DMCNTB0 DMCNTA1 DMCNTB1 DMCNTA2 DMCNTB2 DMCNTA3 DMCNTB3 DMCNTA4 DMCNTB4 DMCNTA5 DMCNTB5 DMCNTA6 DMCNTB6 DMCNTA7 DMCNTB7 DMSCNT DMICNT DMICNTA DMISTS DMEDET DMASTS BAR_0 BAMR_0 BDR_0 BDMR_0 BAR_1 BAMR_1 BDR_1 BDMR_1 BBR_0 BBR_1 BRCR
Address H'FF460400 H'FF460404 H'FF460408 H'FF46040C H'FF460410 H'FF460414 H'FF460418 H'FF46041C H'FF460420 H'FF460424 H'FF460428 H'FF46042C H'FF460430 H'FF460434 H'FF460438 H'FF46043C H'FF460500 H'FF460508 H'FF46050C H'FF460510 H'FF460514 H'FF460518 H'FFFC0400 H'FFFC0404 H'FFFC0408 H'FFFC040C H'FFFC0410 H'FFFC0414 H'FFFC0418 H'FFFC041C H'FFFC04A0 H'FFFC04B0 H'FFFC04C0
Module DMAC
Rev. 2.00 Sep. 07, 2007 Page 1174 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 32 32 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 Access Size 32 32 BSC H-UDI INTC 8, 16, 32 16 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 WDT 16 16 16 CPG SYSTEM 16 8 8 8 8 8 8
Register Name Cache control register 1 Cache control register 2 AC characteristics switching register Instruction register Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register PINT interrupt enable register PINT interrupt request register Bank control register Bank number register Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 05 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 Interrupt priority register 15 Interrupt priority register 16 Watchdog timer control/status register Watchdog timer counter Watchdog reset control/status register Frequency control register Standby control register Standby control register 2 System control register 1 System control register 2 Standby control register 3 Standby control register 4
Abbreviation CCR1 CCR2 ACSWR SDIR ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR01 IPR02 IPR05 IPR06 IPR07 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 IPR15 IPR16 WTCSR WTCNT WRCSR FRQCR STBCR STBCR2 SYSCR1 SYSCR2 STBCR3 STBCR4
Address H'FFFC1000 H'FFFC1004 H'FFFD8808 H'FFFD9000 H'FFFD9400 H'FFFD9402 H'FFFD9404 H'FFFD9406 H'FFFD9408 H'FFFD940A H'FFFD940C H'FFFD940E H'FFFD9418 H'FFFD941A H'FFFD9420 H'FFFD9800 H'FFFD9802 H'FFFD9804 H'FFFD9806 H'FFFD9808 H'FFFD980A H'FFFD980C H'FFFD980E H'FFFD9810 H'FFFD9812 H'FFFD9814 H'FFFE0000 H'FFFE0002 H'FFFE0004 H'FFFE0010 H'FFFE0014 H'FFFE0018 H'FFFE0402 H'FFFE0404 H'FFFE0408 H'FFFE040C
Module Cache
Rev. 2.00 Sep. 07, 2007 Page 1175 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 16 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Size 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 16 8 I/O Ports 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16, 32 8, 16 8, 16 8, 16 8, 16, 32 8, 16 8, 16 8, 16 8, 16
Register Name Standby control register 5 64-Hz counter Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date alarm register Month alarm register RTC control register 1 RTC control register 2 Year alarm register RTC control register 3 Port A data register H Port A data register L Port A port register H Port A port register L Port B data register H Port B data register L Port B port register H Port B port register L Port C data register H Port C data register L Port C port register H Port C port register L Port D data register Port D port register H Port D port register L Port E port register Port F data register Port F port register
Abbreviation STBCR5 R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 RYRAR RCR3 PADRH PADRL PAPRH PAPRL PBDRH PBDRL PBPRH PBPRL PCDRH PCDRL PCPRH PCPRL PDDR PDPRH PDPRL PEPR PFDR PFPR
Address H'FFFE0410 H'FFFE0800 H'FFFE0802 H'FFFE0804 H'FFFE0806 H'FFFE0808 H'FFFE080A H'FFFE080C H'FFFE080E H'FFFE0810 H'FFFE0812 H'FFFE0814 H'FFFE0816 H'FFFE0818 H'FFFE081A H'FFFE081C H'FFFE081E H'FFFE0820 H'FFFE0824 H'FFFE3800 H'FFFE3802 H'FFFE3804 H'FFFE3806 H'FFFE3808 H'FFFE380A H'FFFE380C H'FFFE380E H'FFFE3810 H'FFFE3812 H'FFFE3814 H'FFFE3816 H'FFFE381A H'FFFE381C H'FFFE381E H'FFFE3826 H'FFFE382A H'FFFE382E
Module SYSTEM RTC
Rev. 2.00 Sep. 07, 2007 Page 1176 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32
Register Name Port A I/O register H Port A I/O register L Port A control register 8 Port A control register 7 Port A control register 6 Port A control register 5 Port A control register 4 Port A control register 3 Port A control register 2 Port A control register 1 Port B I/O register H Port B I/O register L Port B control register 8 Port B control register 7 Port B control register 6 Port B control register 5 Port B control register 4 Port B control register 3 Port B control register 2 Port B control register 1 Port C I/O register H Port C I/O register L Port C control register 7 Port C control register 6 Port C control register 5 Port C control register 4 Port C control register 3 Port C control register 2 Port C control register 1 Port D I/O register Port D control register 5 Port D control register 4 Port D control register 3 Port D control register 2 Port D control register 1 Port E control register 2
Abbreviation PAIORH PAIORL PACR8 PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PBIORH PBIORL PBCR8 PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PCIORH PCIORL PCCR7 PCCR6 PCCR5 PCCR4 PCCR3 PCCR2 PCCR1 PDIOR PDCR5 PDCR4 PDCR3 PDCR2 PDCR1 PECR2
Address H'FFFE3880 H'FFFE3882 H'FFFE3884 H'FFFE3886 H'FFFE3888 H'FFFE388A H'FFFE388C H'FFFE388E H'FFFE3890 H'FFFE3892 H'FFFE3898 H'FFFE389A H'FFFE389C H'FFFE389E H'FFFE38A0 H'FFFE38A2 H'FFFE38A4 H'FFFE38A6 H'FFFE38A8 H'FFFE38AA H'FFFE38B0 H'FFFE38B2 H'FFFE38B6 H'FFFE38B8 H'FFFE38BA H'FFFE38BC H'FFFE38BE H'FFFE38C0 H'FFFE38C2 H'FFFE38CA H'FFFE38D2 H'FFFE38D4 H'FFFE38D6 H'FFFE38D8 H'FFFE38DA H'FFFE38F0
Module PFC
Rev. 2.00 Sep. 07, 2007 Page 1177 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 Access Size 8, 16 8, 16 8, 16, 32 8, 16 MTU2 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8
Register Name Port E control register 1 Port F I/O register Port F control register 2 Port F control register 1 Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_3 Timer interrupt enable register_4 Timer output master enable register Timer gate control register Timer output control register 1 Timer output control register 2 Timer counter_3 Timer counter_4 Timer cycle data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer subcounter Timer cycle buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 Timer interrupt skipping set register
Abbreviation PECR1 PFIOR PFCR2 PFCR1 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TITCR
Address H'FFFE38F2 H'FFFE38FA H'FFFE3908 H'FFFE390A H'FFFE4200 H'FFFE4201 H'FFFE4202 H'FFFE4203 H'FFFE4204 H'FFFE4205 H'FFFE4206 H'FFFE4207 H'FFFE4208 H'FFFE4209 H'FFFE420A H'FFFE420D H'FFFE420E H'FFFE420F H'FFFE4210 H'FFFE4212 H'FFFE4214 H'FFFE4216 H'FFFE4218 H'FFFE421A H'FFFE421C H'FFFE421E H'FFFE4220 H'FFFE4222 H'FFFE4224 H'FFFE4226 H'FFFE4228 H'FFFE422A H'FFFE422C H'FFFE422D H'FFFE4230
Module PFC
Rev. 2.00 Sep. 07, 2007 Page 1178 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 Access Size 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8
Register Name Timer interrupt skipping counter Timer buffer transfer set register Timer dead time enable register Timer output level buffer register Timer buffer operation transfer mode register_3 Timer buffer operation transfer mode register_4 Timer A/D converter start request control register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4
Abbreviation TITCNT TBTER TDER TOLBR TBTM_3 TBTM_4 TADCR TADCORA_4 TADCORB_4
Address H'FFFE4231 H'FFFE4232 H'FFFE4234 H'FFFE4236 H'FFFE4238 H'FFFE4239 H'FFFE4240 H'FFFE4244 H'FFFE4246 H'FFFE4248 H'FFFE424A H'FFFE4260 H'FFFE4280 H'FFFE4281 H'FFFE4282 H'FFFE4284 H'FFFE4300 H'FFFE4301 H'FFFE4302 H'FFFE4303 H'FFFE4304 H'FFFE4305 H'FFFE4306 H'FFFE4308 H'FFFE430A H'FFFE430C H'FFFE430E H'FFFE4320 H'FFFE4322 H'FFFE4324 H'FFFE4325
Module MTU2
Timer A/D converter start request cycle set buffer TADCOBRA_4 register A_4 Timer A/D converter start request cycle set buffer TADCOBRB_4 register B_4 Timer waveform control register Timer start register Timer synchronous register Timer counter synchronous start register Timer read/write enable register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer general register E_0 Timer general register F_0 Timer interrupt enable register 2_0 Timer status register 2_0 TWCR TSTR TSYR TCSYSTR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0
Rev. 2.00 Sep. 07, 2007 Page 1179 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 8 16 8 8 8 8 8 8 8 8 8 Access Size 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 8 16 8 8 8 8 8 8 TMR 8 8 8
Register Name Timer buffer operation transfer mode register_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer input capture control register Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer counter U_5 Timer general register U_5 Timer control register U_5 Timer I/O control register U_5 Timer counter V_5 Timer general register V_5 Timer control register V_5 Timer I/O control register V_5 Timer counter W_5 Timer general register W_5 Timer control register W_5 Timer I/O control register W_5 Timer status register_5 Timer interrupt enable register_5 Timer start register_5 Timer compare match clear register Timer control register_0 Timer control register_1 Timer control/status register_0
Abbreviation TBTM_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 TIORV_5 TCNTW_5 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 TCNTCMPCLR T8TCR_0 T8TCR_1 T8TCSR_0
Address H'FFFE4326 H'FFFE4380 H'FFFE4381 H'FFFE4382 H'FFFE4384 H'FFFE4385 H'FFFE4386 H'FFFE4388 H'FFFE438A H'FFFE4390 H'FFFE4000 H'FFFE4001 H'FFFE4002 H'FFFE4004 H'FFFE4005 H'FFFE4006 H'FFFE4008 H'FFFE400A H'FFFE4080 H'FFFE4082 H'FFFE4084 H'FFFE4086 H'FFFE4090 H'FFFE4092 H'FFFE4094 H'FFFE4096 H'FFFE40A0 H'FFFE40A2 H'FFFE40A4 H'FFFE40A6 H'FFFE40B0 H'FFFE40B2 H'FFFE40B4 H'FFFE40B6 H'FFFE5400 H'FFFE5401 H'FFFE5402
Module MTU2
Rev. 2.00 Sep. 07, 2007 Page 1180 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 8 8 8 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 Access Size 8 8 8 8 8 8 8 8 8 ADC 16 16 16 16 16 16 16 16 16 DAC 8, 16 8, 16 8, 16 SCIF 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8
Register Name Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 Timer counter control register_0 Timer counter control register_1 A/D data register A_0 A/D data register B_0 A/D data register C_0 A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 A/D control/status register D/A data register 0 D/A data register 1 D/A control register Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit FIFO data register_0 Serial status register Receive FIFO data register_0 FIFO control register_0 FIFO data count register_0 Serial port register_0 Line status register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit FIFO data register_1 Serial status register_1 Receive FIFO data register_1
Abbreviation T8TCSR_1 T8TCORA_0 T8TCORA_1 T8TCORB_0 T8TCORB_1 T8TCNT_0 T8TCNT_1 T8TCCR_0 T8TCCR_1 ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR DADR0 DADR1 DACR SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1
Address H'FFFE5403 H'FFFE5404 H'FFFE5405 H'FFFE5406 H'FFFE5407 H'FFFE5408 H'FFFE5409 H'FFFE540A H'FFFE540B H'FFFE5800 H'FFFE5802 H'FFFE5804 H'FFFE5806 H'FFFE5808 H'FFFE580A H'FFFE580C H'FFFE580E H'FFFE5820 H'FFFE6800 H'FFFE6801 H'FFFE6802 H'FFFE8000 H'FFFE8004 H'FFFE8008 H'FFFE800C H'FFFE8010 H'FFFE8014 H'FFFE8018 H'FFFE801C H'FFFE8020 H'FFFE8024 H'FFFE8800 H'FFFE8804 H'FFFE8808 H'FFFE880C H'FFFE8810 H'FFFE8814
Module TMR
Rev. 2.00 Sep. 07, 2007 Page 1181 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 Access Size 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16
Register Name FIFO control register_1 FIFO data count register_1 Serial port register_1 Line status register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit FIFO data register_2 Serial status register_2 Receive FIFO data register_2 FIFO control register_2 FIFO data count register_2 Serial port register_2 Line status register_2 Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit FIFO data register_3 Serial status register_3 Receive FIFO data register_3 FIFO control register_3 FIFO data count register_3 Serial port register_3 Line status register_3 Serial mode register_4 Bit rate register_4 Serial control register_4 Transmit FIFO data register_4 Serial status register_4 Receive FIFO data register_4 FIFO control register_4 FIFO data count register_4 Serial port register_4 Line status register_4 Serial mode register_5 Bit rate register_5 Serial control register_5
Abbreviation SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 SCFSR_3 SCFRDR_3 SCFCR_3 SCFDR_3 SCSPTR_3 SCLSR_3 SCSMR_4 SCBRR_4 SCSCR_4 SCFTDR_4 SCFSR_4 SCFRDR_4 SCFCR_4 SCFDR_4 SCSPTR_4 SCLSR_4 SCSMR_5 SCBRR_5 SCSCR_5
Address H'FFFE8818 H'FFFE881C H'FFFE8820 H'FFFE8824 H'FFFE9000 H'FFFE9004 H'FFFE9008 H'FFFE900C H'FFFE9010 H'FFFE9014 H'FFFE9018 H'FFFE901C H'FFFE9020 H'FFFE9024 H'FFFE9800 H'FFFE9804 H'FFFE9808 H'FFFE980C H'FFFE9810 H'FFFE9814 H'FFFE9818 H'FFFE981C H'FFFE9820 H'FFFE9824 H'FFFEA000 H'FFFEA004 H'FFFEA008 H'FFFEA00C H'FFFEA010 H'FFFEA014 H'FFFEA018 H'FFFEA01C H'FFFEA020 H'FFFEA024 H'FFFEA800 H'FFFEA804 H'FFFEA808
Module SCIF
Rev. 2.00 Sep. 07, 2007 Page 1182 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 32 32 32 32 32 32 32 32 8 8 Access Size 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 8 16 8 16 8 16 16 16 16 SSI 32 32 32 32 32 32 32 32 IIC3 8 8
Register Name Transmit FIFO data register_5 Serial status register_5 Receive FIFO data register_5 FIFO control register_5 FIFO data count register_5 Serial port register_5 Line status register_5 Serial mode register_6 Bit rate register_6 Serial control register_6 Transmit FIFO data register_6 Serial status register_6 Receive FIFO data register_6 FIFO control register_6 FIFO data count register_6 Serial port register_6 Line status register_6 Serial mode register_7 Bit rate register_7 Serial control register_7 Transmit FIFO data register_7 Serial status register_7 Receive FIFO data register_7 FIFO control register_7 FIFO data count register_7 Serial port register_7 Line status register_7 Control register_0 Status register_0 Transmit data register_0 Receive data register_0 Control register_1 Status register_1 Transmit data register_1 Receive data register_1 I2C bus control register 1_0 I2C bus control register 2_0
Abbreviation SCFTDR_5 SCFSR_5 SCFRDR_5 SCFCR_5 SCFDR_5 SCSPTR_5 SCLSR_5 SCSMR_6 SCBRR_6 SCSCR_6 SCFTDR_6 SCFSR_6 SCFRDR_6 SCFCR_6 SCFDR_6 SCSPTR_6 SCLSR_6 SCSMR_7 SCBRR_7 SCSCR_7 SCFTDR_7 SCFSR_7 SCFRDR_7 SCFCR_7 SCFDR_7 SCSPTR_7 SCLSR_7 SSICR_0 SSISR_0 SSITDR_0 SSIRDR_0 SSICR_1 SSISR_1 SSITDR_1 SSIRDR_1 ICCR1_0 ICCR2_0
Address H'FFFEA80C H'FFFEA810 H'FFFEA814 H'FFFEA818 H'FFFEA81C H'FFFEA820 H'FFFEA824 H'FFFEB000 H'FFFEB004 H'FFFEB008 H'FFFEB00C H'FFFEB010 H'FFFEB014 H'FFFEB018 H'FFFEB01C H'FFFEB020 H'FFFEB024 H'FFFEB800 H'FFFEB804 H'FFFEB808 H'FFFEB80C H'FFFEB810 H'FFFEB814 H'FFFEB818 H'FFFEB81C H'FFFEB820 H'FFFEB824 H'FFFED000 H'FFFED004 H'FFFED008 H'FFFED00C H'FFFED080 H'FFFED084 H'FFFED088 H'FFFED08C H'FFFEE000 H'FFFEE001
Module SCIF
Rev. 2.00 Sep. 07, 2007 Page 1183 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 RCAN-ET 16 16 16 16 16 16 16
Register Name I2C bus mode register_0 I2C bus interrupt enable register_0 I2C bus status register_0 Slave address register_0 I2C bus transmit data register_0 I2C bus receive data register_0 NF2CYC register_0 I2C bus control register 1_1 I C bus control register 2_1 I2C bus mode register_1 I2C bus interrupt enable register_1 I2C bus status register_1 Slave address register_1 I2C bus transmit dataregister_1 I2C bus receive data register_1 NF2CYC register_1 I2C bus control register 1_2 I2C bus control register 2_2 I2C bus mode register_2 I C bus interrupt enable register_2 I2C bus status register_2 Slave address register_2 I2C bus transmit data register_2 I2C bus receive data register_2 NF2CYC register_2 Master control register_0 General status register_0 Bit configuration register 1_0 Bit configuration register 0_0 Interrupt request register_0 Interrupt mask register_0 Transmit error counter_0/ Receive error counter_0
2 2
Abbreviation ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 NF2CYC_0 ICCR1_1 ICCR2_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 NF2CYC_1 ICCR1_2 ICCR2_2 ICMR_2 ICIER_2 ICSR_2 SAR_2 ICDRT_2 ICDRR_2 NF2CYC_2 MCR_0 GSR_0 BCR1_0 BCR0_0 IRR_0 IMR_0 TEC_0/ REC_0
Address H'FFFEE002 H'FFFEE003 H'FFFEE004 H'FFFEE005 H'FFFEE006 H'FFFEE007 H'FFFEE008 H'FFFEE080 H'FFFEE081 H'FFFEE082 H'FFFEE083 H'FFFEE084 H'FFFEE085 H'FFFEE086 H'FFFEE087 H'FFFEE088 H'FFFEE100 H'FFFEE101 H'FFFEE102 H'FFFEE103 H'FFFEE104 H'FFFEE105 H'FFFEE106 H'FFFEE107 H'FFFEE108 H'FFFF0000 H'FFFF0002 H'FFFF0004 H'FFFF0006 H'FFFF0008 H'FFFF000A H'FFFF000C
Module IIC3
Rev. 2.00 Sep. 07, 2007 Page 1184 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 Access Size 32
Register Name Transmit pending register 1_0 Transmit pending register 0_0 Transmit cancel register 0_0 Transmit acknowledge register 0_0 Abort acknowledge register 0_0 Data frame receive pending register 0_0 Remote frame receive pending register 0_0 Mailbox interrupt mask register0_0 Unread message status register 0_0 Mailbox 0 Control 0
Abbreviation TXPR1_0 TXPR0_0 TXCR0_0 TXACK0_0 ABACK0_0 RXPR0_0 RFPR0_0 MBIMR0_0 UMSR0_0 CONTROL0H CONTROL0L LAFM LAFMH LAFML Data MSG_DATA[0] MSG_DATA[1] MSG_DATA[2] MSG_DATA[3] MSG_DATA[4] MSG_DATA[5] MSG_DATA[6] MSG_DATA[7] Control 1 CONTROL1H CONTROL1L
Address H'FFFF0020 H'FFFF0022 H'FFFF002A H'FFFF0032 H'FFFF003A H'FFFF0042 H'FFFF004A H'FFFF0052 H'FFFF005A H'FFFF0100 H'FFFF0102 H'FFFF0104 H'FFFF0106 H'FFFF0108 H'FFFF0109 H'FFFF010A H'FFFF010B H'FFFF010C H'FFFF010D H'FFFF010E H'FFFF010F H'FFFF0110 H'FFFF0111 H'FFFF0100 + n x 32 H'FFFF0102 + n x 32 H'FFFF0104 + n x 32 H'FFFF0106 + n x 32 H'FFFF0108 + n x 32 H'FFFF0109 + n x 32 H'FFFF010A + n x 32
Module RCAN-ET
16 16 16 16 16 16 16 16, 32 16 16, 32 16 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8 16, 32 16 16, 32 16 8, 16, 32 8 8, 16
Mailbox n (n = 1 to 15)
Control 0
CONTROL0H CONTROL0L
LAFM
LAFMH LAFML
Data
MSG_DATA[0] MSG_DATA[1] MSG_DATA[2]
Rev. 2.00 Sep. 07, 2007 Page 1185 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Size 8 8, 16, 32 8 8, 16 8 8, 16 8 16 16 16 16 16 16 16 32
Register Name Mailbox n (n = 1 to 15) Data
Abbreviation MSG_DATA[3] MSG_DATA[4] MSG_DATA[5] MSG_DATA[6] MSG_DATA[7] Control 1 CONTROL1H CONTROL1L
Address H'FFFF010B + n x 32 H'FFFF010C + n x 32 H'FFFF010D + n x 32 H'FFFF010E + n x 32 H'FFFF010F + n x 32 H'FFFF0110 + n x 32 H'FFFF0111 + n x 32 H'FFFF0800 H'FFFF0802 H'FFFF0804 H'FFFF0806 H'FFFF0808 H'FFFF080A H'FFFF080C H'FFFF0820 H'FFFF0822 H'FFFF082A H'FFFF0832 H'FFFF083A H'FFFF0842 H'FFFF084A H'FFFF0852 H'FFFF085A H'FFFF0900 H'FFFF0902 H'FFFF0904 H'FFFF0906
Module RCAN-ET
Master control register_1 General status register_1 Bit configuration register1_1 Bit configuration register0_1 Interrupt request register_1 Interrupt mask register_1 Transmit error counter_1/ Receive error counter_1 Transmit pending register 1_1 Transmit pending register 0_1 Transmit cancel register 0_1 Transmit acknowledge register 0_1 Abort acknowledge register 0_1 Data frame receive pending register 0_1 Remote frame receive pending register 0_1 Mailbox interrupt mask register0_1 Unread message status register 0_1 Mailbox 0 Control 0
MCR_1 GSR_1 BCR1_1 BCR0_1 IRR_1 IMR_1 TEC_1/ REC_1 TXPR1_1 TXPR0_1 TXCR0_1 TXACK0_1 ABACK0_1 RXPR0_1 RFPR0_1 MBIMR0_1 UMSR0_1 CONTROL0H CONTROL0L
16 16 16 16 16 16 16 16, 32 16 16, 32 16
LAFM
LAFMH LAFML
Rev. 2.00 Sep. 07, 2007 Page 1186 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 Access Size 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8 16, 32 16 16, 32 16 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8
Register Name Mailbox 0 Data
Abbreviation MSG_DATA[0] MSG_DATA[1] MSG_DATA[2] MSG_DATA[3] MSG_DATA[4] MSG_DATA[5] MSG_DATA[6] MSG_DATA[7] Control 1 CONTROL1H CONTROL1L
Address H'FFFF0908 H'FFFF0909 H'FFFF090A H'FFFF090B H'FFFF090C H'FFFF090D H'FFFF090E H'FFFF090F H'FFFF0910 H'FFFF0911 H'FFFF0900 + n x 32 H'FFFF0902 + n x 32 H'FFFF0904 + n x 32 H'FFFF0906 + n x 32 H'FFFF0908*nx 32 H'FFFF0909*nx 32 H'FFFF090A + n x 32 H'FFFF090B + n x 32 H'FFFF090C + n x 32 H'FFFF090D + n x 32 H'FFFF090E + n x 32 H'FFFF090F + n x 32 H'FFFF0910 + n x 32 H'FFFF0911 + n x 32
Module RCAN-ET
Mailbox n (n = 1 to 15)
Control 0
CONTROL0H CONTROL0L
LAFM
LAFMH LAFML
Data
MSG_DATA[0] MSG_DATA[1] MSG_DATA[2] MSG_DATA[3] MSG_DATA[4] MSG_DATA[5] MSG_DATA[6] MSG_DATA[7]
Control 1
CONTROL1H CONTROL1L
Rev. 2.00 Sep. 07, 2007 Page 1187 of 1312 REJ09B0320-0200
Section 30 List of Registers
Number of Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 INTC 8, 16, 32 8 8, 16 8 SYSTEM 16 8 8
Register Name IEBus control register IEBus command register IEBus master control register IEBus master unit address register 1 IEBus master unit address register 2 IEBus slave address setting register 1 IEBus slave address setting register 2 IEBus transmit message length register IEBus reception master address register 1 IEBus reception master address register 2 IEBus receive control field register IEBus receive message length register IEBus lock address register 1 IEBus lock address register 2 IEBus general flag register IEBus transmit status register IEBus transmit interrupt enable register IEBus receive status register IEBus receive interrupt enable register IEBus clock select register IEBus transmit data buffer register 001 to 128 IEBus receive data buffer register 001 to 128 DMA transfer enable register 0 DMA transfer enable register 1 DMA transfer enable register 2 DMA transfer enable register 3 Deep standby cancel source flag register
Abbreviation IECTR IECMR IEMCR IEAR1 IEAR2 IESA1 IESA2 IETBFL IEMA1 IEMA2 IERCTL IERBFL IELA1 IELA2 IEFLG IETSR IEIET IERSR IEIER IECKSR IETB001 to IETB128 IERB001 to IERB128 DREQER0 DREQER1 DREQER2 DREQER3 DSFR
Address H'FFFF1000 H'FFFF1001 H'FFFF1002 H'FFFF1003 H'FFFF1004 H'FFFF1005 H'FFFF1006 H'FFFF1007 H'FFFF1009 H'FFFF100A H'FFFF100B H'FFFF100C H'FFFF100E H'FFFF100F H'FFFF1010 H'FFFF1011 H'FFFF1012 H'FFFF1014 H'FFFF1015 H'FFFF1018 H'FFFF1100 to H'FFFF117F H'FFFF1200 to H'FFFF127F H'FFFF1600 H'FFFF1601 H'FFFF1602 H'FFFF1603 H'FFFF1904 H'FFFF1906 H'FFFF1907
Module IEB
Deep standby oscillation stabilization clock select DSCNT register RAM retained area specification register RAMKP
Rev. 2.00 Sep. 07, 2007 Page 1188 of 1312 REJ09B0320-0200
Section 30 List of Registers
30.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
Register Abbreviation CROMEN CROMSY0 CROMCTL0 CROMCTL1 CROMCTL3 CROMCTL4 CROMCTL5 CROMST0 CROMST1 CROMST3 CROMST4 CROMST5 CROMST6 CBUFST0 CBUFST1 CBUFST2 HEAD00 HEAD01 HEAD02 HEAD03 SHEAD00 SHEAD01 SHEAD02 SHEAD03 SHEAD04 SHEAD05 SHEAD06 SHEAD07 HEAD20 HEAD21 HEAD22 HEAD23 Bits 31/ 23/15/7 SUBC_EN SY_AUT MD_DESC M2F2EDC STP_ECC LINKOFF ER2_SHEAD0 NG_MD ST_AMD2 ST_ERR BUF_REF BUF_ECC BUF_NG HEAD007 HEAD017 HEAD027 HEAD037 SHEAD007 SHEAD017 SHEAD027 SHEAD037 SHEAD047 SHEAD057 SHEAD067 SHEAD077 HEAD207 HEAD217 HEAD227 HEAD237 Bits30/ 22/14/6 CROM_EN SY_IEN MD_DEC2 STP_EDC LINK2 ER2_SHEAD1 NG_MDCMP1 ST_AMD1 BUF_ACT BUF_EDC HEAD006 HEAD016 HEAD026 HEAD036 SHEAD006 SHEAD016 SHEAD026 SHEAD036 SHEAD046 SHEAD056 SHEAD066 SHEAD076 HEAD206 HEAD216 HEAD226 HEAD236 Bits 29/ 21/13/5 CROM_STP SY_DEN MD_AUTO MD_DEC1 ST_SYIL ER2_SHEAD2 NG_MDCMP2 ST_AMD0 ST_ECCABT HEAD005 HEAD015 HEAD025 HEAD035 SHEAD005 SHEAD015 SHEAD025 SHEAD035 SHEAD045 SHEAD055 SHEAD065 SHEAD075 HEAD205 HEAD215 HEAD225 HEAD235 Bits28/ 20/12/4 MD_AUTOS1 MD_DEC0 STP_MD EROSEL ST_SYNO ER2_SHEAD3 NG_MDCMP3 ST_MDX ST_ECCNG BUF_MD HEAD004 HEAD014 HEAD024 HEAD034 SHEAD004 SHEAD014 SHEAD024 SHEAD034 SHEAD044 SHEAD054 SHEAD064 SHEAD074 HEAD204 HEAD214 HEAD224 HEAD234 Bits 27/ 19/11/3 MD_AUTOS2 MD_PQREP3 STP_MIN NO_ECC ST_BLKS ER2_HEAD0 ER2_SHEAD4 NG_MDCMP4 LINK_ON ST_ECCP BUF_MIN HEAD003 HEAD013 HEAD023 HEAD033 SHEAD003 SHEAD013 SHEAD023 SHEAD033 SHEAD043 SHEAD053 SHEAD063 SHEAD073 HEAD203 HEAD213 HEAD223 HEAD233 Bits26/ 18/10/2 MD_SEC2 MD_PQREP2 ST_BLKL ER2_HEAD1 ER2_SHEAD5 NG_MDDEF LINK_DET ST_ECCQ HEAD002 HEAD012 HEAD022 HEAD032 SHEAD002 SHEAD012 SHEAD022 SHEAD032 SHEAD042 SHEAD052 SHEAD062 SHEAD072 HEAD202 HEAD212 HEAD222 HEAD232 Bits 25/ 17/9/1 MD_SEC1 MD_PQREP1 ST_SECS ER2_HEAD2 ER2_SHEAD6 NG_MDTIM1 LINK_SDET ST_EDC1 HEAD001 HEAD011 HEAD021 HEAD031 SHEAD001 SHEAD011 SHEAD021 SHEAD031 SHEAD041 SHEAD051 SHEAD061 SHEAD071 HEAD201 HEAD211 HEAD221 HEAD231 Bits24/ 16/8/0 MD_SEC0 MD_PQREP0 MSF_LBA_SEL ST_SECL ER2_HEAD3 ER2_SHEAD7 NG_MDTIM2 LINK_OUT1 ST_EDC2 HEAD000 HEAD010 HEAD020 HEAD030 SHEAD000 SHEAD010 SHEAD020 SHEAD030 SHEAD040 SHEAD050 SHEAD060 SHEAD070 HEAD200 HEAD210 HEAD220 HEAD230 Module ROM-DEC
Rev. 2.00 Sep. 07, 2007 Page 1189 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SHEAD20 SHEAD21 SHEAD22 SHEAD23 SHEAD24 SHEAD25 SHEAD26 SHEAD27 CBUFCTL0 CBUFCTL1 CBUFCTL2 CBUFCTL3 CROMST0M ROMDECRST RSTSTAT SSI INTHOLD INHINT RINGBUFCTL STRMDIN0 STRMDIN1 STRMDIN2 STRMDIN3 STRMDOUT0 STRMDOUT1 SYCBEEN
Bits 31/ 23/15/7 SHEAD207 SHEAD217 SHEAD227 SHEAD237 SHEAD247 SHEAD257 SHEAD267 SHEAD277 CBUF_AUT BS_MIN7 BS_SEC7 BS_FRM7 LOGICRST RAMCLRST BYTEND ISEC INHISEC STRMDIN31 STRMDIN23 STRMDIN15 STRMDIN7 STRMDOUT15 STRMDOUT7 STSCLR
Bits30/ 22/14/6 SHEAD206 SHEAD216 SHEAD226 SHEAD236 SHEAD246 SHEAD256 SHEAD266 SHEAD276 CBUF_EN BS_MIN6 BS_SEC6 BS_FRM6 RAMRST BITEND ITARG INHITARG
Bits 29/ 21/13/5 SHEAD205 SHEAD215 SHEAD225 SHEAD235 SHEAD245 SHEAD255 SHEAD265 SHEAD275 CBUF_LINK BS_MIN5 BS_SEC5 BS_FRM5 ST_SYILM INHBUSCAN BUFEND01 ISY INHISY
Bits28/ 20/12/4 SHEAD204 SHEAD214 SHEAD224 SHEAD234 SHEAD244 SHEAD254 SHEAD264 SHEAD274 CBUF_MD1 BS_MIN4 BS_SEC4 BS_FRM4 ST_SYNOM BUFEND00 IERR INHIERR
Bits 27/ 19/11/3 SHEAD203 SHEAD213 SHEAD223 SHEAD233 SHEAD243 SHEAD253 SHEAD263 SHEAD273 CBUF_MD0 BS_MIN3 BS_SEC3 BS_FRM3 ST_BLKSM BUFEND11 IBUF INHIBUF STRMDIN27 STRMDIN19 STRMDIN11 STRMDIN3 STRMDOUT11 STRMDOUT3
Bits26/ 18/10/2 SHEAD202 SHEAD212 SHEAD222 SHEAD232 SHEAD242 SHEAD252 SHEAD262 SHEAD272 CBUF_TS BS_MIN2 BS_SEC2 BS_FRM2 ST_BLKLM BUFEND10 IREADY INHIREADY STRMDIN26 STRMDIN18 STRMDIN10 STRMDIN2 STRMDOUT10 STRMDOUT2 TOEN
Bits 25/ 17/9/1 SHEAD201 SHEAD211 SHEAD221 SHEAD231 SHEAD241 SHEAD251 SHEAD261 SHEAD271 CBUF_Q BS_MIN1 BS_SEC1 BS_FRM1 ST_SECSM PREINHREQDM STRMDIN25 STRMDIN17 STRMDIN9 STRMDIN1 STRMDOUT9 STRMDOUT1 IGAEN PMST1 CMST1 EMST1 OMST1 SHMST1
Bits24/ 16/8/0 SHEAD200 SHEAD210 SHEAD220 SHEAD230 SHEAD240 SHEAD250 SHEAD260 SHEAD270 BS_MIN0 BS_SEC0 BS_FRM0 ST_SECLM PREINHIREADY STRMDIN24 STRMDIN16 STRMDIN8 STRMDIN0 STRMDOUT8 STRMDOUT0 PMST0 CMST0 EMST0 OMST0 SHMST0 Bus Monitor Module ROM-DEC
DRMREQDELAY1 DRMREQDELAY0 STRMDIN30 STRMDIN22 STRMDIN14 STRMDIN6 STRMDOUT14 STRMDOUT6 PTO CTO ETO STRMDIN29 STRMDIN21 STRMDIN13 STRMDIN5 STRMDOUT13 STRMDOUT5 PER CER EER OER SHER STRMDIN28 STRMDIN20 STRMDIN12 STRMDIN4 STRMDOUT12 STRMDOUT4
SYCBESTS1

SYCBESTS2

Rev. 2.00 Sep. 07, 2007 Page 1190 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SYCBESW
Bits 31/ 23/15/7 00CPEN
Bits30/ 22/14/6
Bits 29/ 21/13/5 10CPEN BSIZE1 BSIZE1 BSIZE1 BSIZE1
Bits28/ 20/12/4 11CPEN BSIZE0 BSIZE0 BSIZE0 BSIZE0
Bits 27/ 19/11/3 WRCV3 RRCV3 WRCV3 RRCV3 WRCV3 RRCV3 WRCV3 RRCV3
Bits26/ 18/10/2 WRCV2 RRCV2 WRCV2 RRCV2 WRCV2 RRCV2 WRCV2 RRCV2
Bits 25/ 17/9/1 WRCV1 RRCV1 WRCV1 RRCV1 WRCV1 RRCV1 WRCV1 RRCV1
Bits24/ 16/8/0 EXENB WRCV0 RRCV0 EXENB WRCV0 RRCV0 EXENB WRCV0 RRCV0 EXENB WRCV0 RRCV0 BSC Module Bus Monitor
CS0CNT

CS0REC

CS1CNT

CS1REC

CS2CNT

CS2REC

CS3CNT

CS3REC

Rev. 2.00 Sep. 07, 2007 Page 1191 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation CS4CNT
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5 BSIZE1 BSIZE1 BSIZE1 BSIZE1 BSIZE1 PBCNT1
Bits28/ 20/12/4 BSIZE0 BSIZE0 BSIZE0 BSIZE0 BSIZE0 PBCNT0
Bits 27/ 19/11/3 WRCV3 RRCV3 WRCV3 RRCV3 WRCV3 RRCV3 EWENB
Bits26/ 18/10/2 WRCV2 RRCV2 WRCV2 RRCV2 WRCV2 RRCV2
Bits 25/ 17/9/1 WRCV1 RRCV1 WRCV1 RRCV1 WRCV1 RRCV1 PWENB
Bits24/ 16/8/0 EXENB WRCV0 RRCV0 EXENB WRCV0 RRCV0 EXENB WRCV0 RRCV0 EXENB EXENB PRENB WRMOD Module BSC
CS4REC

CS5CNT

CS5REC

CS6CNT

CS6REC

SDC0CNT

SDC1CNT

CSMOD0
PRMOD
Rev. 2.00 Sep. 07, 2007 Page 1192 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation CS1WCNT0
Bits 31/ 23/15/7
Bits30/ 22/14/6 CSON2 WRON2 CSWOFF2 CSON2 WRON2 CSWOFF2 CSON2 WRON2 CSWOFF2
Bits 29/ 21/13/5 CSON1 WRON1 CSWOFF1 PBCNT1 CSON1 WRON1 CSWOFF1 PBCNT1 CSON1 WRON1 CSWOFF1 PBCNT1
Bits28/ 20/12/4 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 PBCNT0 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 PBCNT0 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 PBCNT0
Bits 27/ 19/11/3 CSRWAIT3 CSWWAIT3 EWENB CSRWAIT3 CSWWAIT3 EWENB CSRWAIT3 CSWWAIT3 EWENB
Bits26/ 18/10/2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2
Bits 25/ 17/9/1 CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 PWENB CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 PWENB CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 PWENB
Bits24/ 16/8/0 CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 PRENB WRMOD CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 PRENB WRMOD CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 PRENB WRMOD Module BSC
CS2WCNT0

CSMOD1
PRMOD
CS1WCNT1

CS2WCNT1

CSMOD2
PRMOD
CS1WCNT2

CS2WCNT2

CSMOD3
PRMOD
Rev. 2.00 Sep. 07, 2007 Page 1193 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation CS1WCNT3
Bits 31/ 23/15/7
Bits30/ 22/14/6 CSON2 WRON2 CSWOFF2 CSON2 WRON2 CSWOFF2 CSON2 WRON2 CSWOFF2
Bits 29/ 21/13/5 CSON1 WRON1 CSWOFF1 PBCNT1 CSON1 WRON1 CSWOFF1 PBCNT1 CSON1 WRON1 CSWOFF1 PBCNT1
Bits28/ 20/12/4 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 PBCNT0 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 PBCNT0 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 PBCNT0
Bits 27/ 19/11/3 CSRWAIT3 CSWWAIT3 EWENB CSRWAIT3 CSWWAIT3 EWENB CSRWAIT3 CSWWAIT3 EWENB
Bits26/ 18/10/2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2
Bits 25/ 17/9/1 CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 PWENB CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 PWENB CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 PWENB
Bits24/ 16/8/0 CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 PRENB WRMOD CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 PRENB WRMOD CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 PRENB WRMOD Module BSC
CS2WCNT3

CSMOD4
PRMOD
CS1WCNT4

CS2WCNT4

CSMOD5
PRMOD
CS1WCNT5

CS2WCNT5

CSMOD6
PRMOD
Rev. 2.00 Sep. 07, 2007 Page 1194 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation CS1WCNT6
Bits 31/ 23/15/7
Bits30/ 22/14/6 CSON2 WRON2 CSWOFF2 DREFW2 DRFC6 DARFC2
Bits 29/ 21/13/5 CSON1 WRON1 CSWOFF1 DREFW1 DRFC5 DARFC1
Bits28/ 20/12/4 CSRWAIT4 CSWWAIT4 CSON0 WRON0 CSWOFF0 DREFW0 DRFC4 DARFC0
Bits 27/ 19/11/3 CSRWAIT3 CSWWAIT3 DRFC11 DRFC3 DARFI3
Bits26/ 18/10/2 CSRWAIT2 CSWWAIT2 CSPRWAIT2 CSPWWAIT2 WDON2 RDON2 WDOFF2 CSROFF2 DRFC10 DRFC2 DPC2 DARFI2 DSZ2
Bits 25/ 17/9/1 CSRWAIT1 CSWWAIT1 CSPRWAIT1 CSPWWAIT1 WDON1 RDON1 WDOFF1 CSROFF1 DRFC9 DRFC1 DPC1 DARFI1 DDBW1 DSZ1
Bits24/ 16/8/0 CSRWAIT0 CSWWAIT0 CSPRWAIT0 CSPWWAIT0 WDON0 RDON0 WDOFF0 CSROFF0 DSFEN DRFEN DRFC8 DRFC0 DPC0 DARFI0 DINIST DINIRQ DPWD DDPD DDBW0 DSZ0 Module BSC
CS2WCNT6

SDRFCNT0

SDRFCNT1
DREFW3 DRFC7
SDIR0
DARFC3
SDIR1

SDPWDCNT

SDDPWDCNT

SD0ADR

Rev. 2.00 Sep. 07, 2007 Page 1195 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SD0TR
Bits 31/ 23/15/7
Bits30/ 22/14/6 DMR14 DMR6 DMR14 DMR6 DCKSC6 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6
Bits 29/ 21/13/5 DRCD1 DMR13 DMR5 DRCD1 DMR13 DMR5 DCKSC5 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5
Bits28/ 20/12/4 DRCD0 DMR12 DMR4 DRCD0 DMR12 DMR4 DSRFST DCKSC4 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4
Bits 27/ 19/11/3 DPCG2 DMR11 DMR3 DPCG2 DMR11 DMR3 DINIST DCKSC3 CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3
Bits26/ 18/10/2 DRAS2 DPCG1 DCL2 DMR10 DMR2 DSZ2 DRAS2 DPCG1 DCL2 DMR10 DMR2 DPWDST DCKSC2 CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2
Bits 25/ 17/9/1 DRAS1 DPCG0 DCL1 DMR9 DMR1 DDBW1 DSZ1 DRAS1 DPCG0 DCL1 DMR9 DMR1 DDPDST DCKSC1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1
Bits24/ 16/8/0 DRAS0 DWR DCL0 DMR8 DMR0 DDBW0 DSZ0 DRAS0 DWR DCL0 DMR8 DMR0 DMRSST DCKSEN DCKSC0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 DMAC Module BSC
SD0MOD
DMR7
SD1ADR

SD1TR

SD1MOD
DMR7
SDSTR

SDCKSCNT
DCKSC7
DMCSADR0
CSA31 CSA23 CSA15 CSA7
DMCDADR0
CDA31 CDA23 CDA15 CDA7
Rev. 2.00 Sep. 07, 2007 Page 1196 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCBCT0
Bits 31/ 23/15/7 CBC23 CBC15 CBC7
Bits30/ 22/14/6 CBC22 CBC14 CBC6 SAMOD2 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6 SAMOD2 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6
Bits 29/ 21/13/5 CBC21 CBC13 CBC5 SAMOD1 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5 SAMOD1 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5
Bits28/ 20/12/4 CBC20 CBC12 CBC4 SAMOD0 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4 SAMOD0 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4
Bits 27/ 19/11/3 CBC19 CBC11 CBC3 OPSEL3 SACT CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3 OPSEL3 SACT CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3
Bits26/ 18/10/2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2
Bits 25/ 17/9/1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1
Bits24/ 16/8/0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 Module DMAC
DMMOD0

DMCSADR1
CSA31 CSA23 CSA15 CSA7
DMCDADR1
CDA31 CDA23 CDA15 CDA7
DMCBCT1
CBC23 CBC15 CBC7
DMMOD1

DMCSADR2
CSA31 CSA23 CSA15 CSA7
DMCDADR2
CDA31 CDA23 CDA15 CDA7
DMCBCT2
CBC23 CBC15 CBC7
Rev. 2.00 Sep. 07, 2007 Page 1197 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMMOD2
Bits 31/ 23/15/7
Bits30/ 22/14/6 SAMOD2 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6 SAMOD2 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6 SAMOD2
Bits 29/ 21/13/5 SAMOD1 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5 SAMOD1 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5 SAMOD1
Bits28/ 20/12/4 SAMOD0 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4 SAMOD0 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4 SAMOD0
Bits 27/ 19/11/3 OPSEL3 SACT CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3 OPSEL3 SACT CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3 OPSEL3 SACT
Bits26/ 18/10/2 OPSEL2 SZSEL2 DAMOD2 DACT CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT
Bits 25/ 17/9/1 OPSEL1 SZSEL1 DAMOD1 DTCM1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1
Bits24/ 16/8/0 OPSEL0 SZSEL0 DAMOD0 DTCM0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 Module DMAC
DMCSADR3
CSA31 CSA23 CSA15 CSA7
DMCDADR3
CDA31 CDA23 CDA15 CDA7
DMCBCT3
CBC23 CBC15 CBC7
DMMOD3

DMCSADR4
CSA31 CSA23 CSA15 CSA7
DMCDADR4
CDA31 CDA23 CDA15 CDA7
DMCBCT4
CBC23 CBC15 CBC7
DMMOD4

Rev. 2.00 Sep. 07, 2007 Page 1198 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCSADR5
Bits 31/ 23/15/7 CSA31 CSA23 CSA15 CSA7
Bits30/ 22/14/6 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6 SAMOD2 CSA30 CSA22 CSA14 CSA6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6 SAMOD2 CSA30 CSA22 CSA14 CSA6
Bits 29/ 21/13/5 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5 SAMOD1 CSA29 CSA21 CSA13 CSA5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5 SAMOD1 CSA29 CSA21 CSA13 CSA5
Bits28/ 20/12/4 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4 SAMOD0 CSA28 CSA20 CSA12 CSA4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4 SAMOD0 CSA28 CSA20 CSA12 CSA4
Bits 27/ 19/11/3 CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3 OPSEL3 SACT CSA27 CSA19 CSA11 CSA3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3 OPSEL3 SACT CSA27 CSA19 CSA11 CSA3
Bits26/ 18/10/2 CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT CSA26 CSA18 CSA10 CSA2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT CSA26 CSA18 CSA10 CSA2
Bits 25/ 17/9/1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1 CSA25 CSA17 CSA9 CSA1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1 CSA25 CSA17 CSA9 CSA1
Bits24/ 16/8/0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 CSA24 CSA16 CSA8 CSA0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 CSA24 CSA16 CSA8 CSA0 Module DMAC
DMCDADR5
CDA31 CDA23 CDA15 CDA7
DMCBCT5
CBC23 CBC15 CBC7
DMMOD5

DMCSADR6
CSA31 CSA23 CSA15 CSA7
DMCDADR6
CDA31 CDA23 CDA15 CDA7
DMCBCT6
CBC23 CBC15 CBC7
DMMOD6

DMCSADR7
CSA31 CSA23 CSA15 CSA7
Rev. 2.00 Sep. 07, 2007 Page 1199 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCDADR7
Bits 31/ 23/15/7 CDA31 CDA23 CDA15 CDA7
Bits30/ 22/14/6 CDA30 CDA22 CDA14 CDA6 CBC22 CBC14 CBC6 SAMOD2 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6
Bits 29/ 21/13/5 CDA29 CDA21 CDA13 CDA5 CBC21 CBC13 CBC5 SAMOD1 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5
Bits28/ 20/12/4 CDA28 CDA20 CDA12 CDA4 CBC20 CBC12 CBC4 SAMOD0 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4
Bits 27/ 19/11/3 CDA27 CDA19 CDA11 CDA3 CBC19 CBC11 CBC3 OPSEL3 SACT RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3
Bits26/ 18/10/2 CDA26 CDA18 CDA10 CDA2 CBC18 CBC10 CBC2 OPSEL2 SZSEL2 DAMOD2 DACT RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2
Bits 25/ 17/9/1 CDA25 CDA17 CDA9 CDA1 CBC25 CBC17 CBC9 CBC1 OPSEL1 SZSEL1 DAMOD1 DTCM1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1
Bits24/ 16/8/0 CDA24 CDA16 CDA8 CDA0 CBC24 CBC16 CBC8 CBC0 OPSEL0 SZSEL0 DAMOD0 DTCM0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 Module DMAC
DMCBCT7
CBC23 CBC15 CBC7
DMMOD7

DMRSADR0
RSA31 RSA23 RSA15 RSA7
DMRDADR0
RDA31 RDA23 RDA15 RDA7
DMRBCT0
RBC23 RBC15 RBC7
DMRSADR1
RSA31 RSA23 RSA15 RSA7
DMRDADR1
RDA31 RDA23 RDA15 RDA7
DMRBCT1
RBC23 RBC15 RBC7
Rev. 2.00 Sep. 07, 2007 Page 1200 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMRSADR2
Bits 31/ 23/15/7 RSA31 RSA23 RSA15 RSA7
Bits30/ 22/14/6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6
Bits 29/ 21/13/5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5
Bits28/ 20/12/4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4
Bits 27/ 19/11/3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3
Bits26/ 18/10/2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2
Bits 25/ 17/9/1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1
Bits24/ 16/8/0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 Module DMAC
DMRDADR2
RDA31 RDA23 RDA15 RDA7
DMRBCT2
RBC23 RBC15 RBC7
DMRSADR3
RSA31 RSA23 RSA15 RSA7
DMRDADR3
RDA31 RDA23 RDA15 RDA7
DMRBCT3
RBC23 RBC15 RBC7
DMRSADR4
RSA31 RSA23 RSA15 RSA7
DMRDADR4
RDA31 RDA23 RDA15 RDA7
DMRBCT4
RBC23 RBC15 RBC7
Rev. 2.00 Sep. 07, 2007 Page 1201 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMRSADR5
Bits 31/ 23/15/7 RSA31 RSA23 RSA15 RSA7
Bits30/ 22/14/6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6 RSA30 RSA22 RSA14 RSA6 RDA30 RDA22 RDA14 RDA6 RBC22 RBC14 RBC6
Bits 29/ 21/13/5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5 RSA29 RSA21 RSA13 RSA5 RDA29 RDA21 RDA13 RDA5 RBC21 RBC13 RBC5
Bits28/ 20/12/4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4 RSA28 RSA20 RSA12 RSA4 RDA28 RDA20 RDA12 RDA4 RBC20 RBC12 RBC4
Bits 27/ 19/11/3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3 RSA27 RSA19 RSA11 RSA3 RDA27 RDA19 RDA11 RDA3 RBC19 RBC11 RBC3
Bits26/ 18/10/2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2 RSA26 RSA18 RSA10 RSA2 RDA26 RDA18 RDA10 RDA2 RBC18 RBC10 RBC2
Bits 25/ 17/9/1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1 RSA25 RSA17 RSA9 RSA1 RDA25 RDA17 RDA9 RDA1 RBC25 RBC17 RBC9 RBC1
Bits24/ 16/8/0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 RSA24 RSA16 RSA8 RSA0 RDA24 RDA16 RDA8 RDA0 RBC24 RBC16 RBC8 RBC0 Module DMAC
DMRDADR5
RDA31 RDA23 RDA15 RDA7
DMRBCT5
RBC23 RBC15 RBC7
DMRSADR6
RSA31 RSA23 RSA15 RSA7
DMRDADR6
RDA31 RDA23 RDA15 RDA7
DMRBCT6
RBC23 RBC15 RBC7
DMRSADR7
RSA31 RSA23 RSA15 RSA7
DMRDADR7
RDA31 RDA23 RDA15 RDA7
DMRBCT7
RBC23 RBC15 RBC7
Rev. 2.00 Sep. 07, 2007 Page 1202 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCNTA0
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5 MDSEL1 DCTG5 MDSEL1 DCTG5 MDSEL1 DCTG5 MDSEL1 DCTG5 MDSEL1 DCTG5
Bits28/ 20/12/4 MDSEL0 DCTG4 MDSEL0 DCTG4 MDSEL0 DCTG4 MDSEL0 DCTG4 MDSEL0 DCTG4
Bits 27/ 19/11/3 DCTG3 DCTG3 DCTG3 DCTG3 DCTG3
Bits26/ 18/10/2 BRLOD DCTG2 BRLOD DCTG2 BRLOD DCTG2 BRLOD DCTG2 BRLOD DCTG2
Bits 25/ 17/9/1 DSEL1 STRG1 SRLOD DCTG1 DSEL1 STRG1 SRLOD DCTG1 DSEL1 STRG1 SRLOD DCTG1 DSEL1 STRG1 SRLOD DCTG1 DSEL1 STRG1 SRLOD DCTG1
Bits24/ 16/8/0 DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 Module DMAC
DMCNTB0

DMCNTA1

DMCNTB1

DMCNTA2

DMCNTB2

DMCNTA3

DMCNTB3

DMCNTA4

Rev. 2.00 Sep. 07, 2007 Page 1203 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCNTB4
Bits 31/ 23/15/7
Bits30/ 22/14/6 DINTM_CH1
Bits 29/ 21/13/5 MDSEL1 DCTG5 MDSEL1 DCTG5 MDSEL1 DCTG5 DINTM_CH2
Bits28/ 20/12/4 MDSEL0 DCTG4 MDSEL0 DCTG4 MDSEL0 DCTG4 DINTM_CH3
Bits 27/ 19/11/3 DCTG3 DCTG3 DCTG3 DINTM_CH4
Bits26/ 18/10/2 BRLOD DCTG2 BRLOD DCTG2 BRLOD DCTG2 DINTM_CH5
Bits 25/ 17/9/1 DSEL1 STRG1 SRLOD DCTG1 DSEL1 STRG1 SRLOD DCTG1 DSEL1 STRG1 SRLOD DCTG1 DINTM_CH6
Bits24/ 16/8/0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DSEL0 STRG0 DRLOD DCTG0 DEN DREQ ECLR DSCLR DMST DINTM_CH7 Module DMAC
DMCNTA5

DMCNTB5

DMCNTA6

DMCNTB6

DMCNTA7

DMCNTB7

DMSCNT

DMICNT
DINTM_CH0
Rev. 2.00 Sep. 07, 2007 Page 1204 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMICNTA
Bits 31/ 23/15/7 DINTA_CH0
Bits30/ 22/14/6 DINTA_CH1 DISTS_CH1 DEDET_CH1 DASTS_CH1 BA0_30 BA0_22 BA0_14 BA0_6 BAM0_30 BAM0_22 BAM0_14 BAM0_6 BD0_30 BD0_22 BD0_14 BD0_6 BDM0_30 BDM0_22 BDM0_14 BDM0_6 BA0_30 BA0_22 BA0_14 BA0_6
Bits 29/ 21/13/5 DINTA_CH2 DISTS_CH2 DEDET_CH2 DASTS_CH2 BA0_29 BA0_21 BA0_13 BA0_5 BAM0_29 BAM0_21 BAM0_13 BAM0_5 BD0_29 BD0_21 BD0_13 BD0_5 BDM0_29 BDM0_21 BDM0_13 BDM0_5 BA0_29 BA0_21 BA0_13 BA0_5
Bits28/ 20/12/4 DINTA_CH3 DISTS_CH3 DEDET_CH3 DASTS_CH3 BA0_28 BA0_20 BA0_12 BA0_4 BAM0_28 BAM0_20 BAM0_12 BAM0_4 BD0_28 BD0_20 BD0_12 BD0_4 BDM0_28 BDM0_20 BDM0_12 BDM0_4 BA0_28 BA0_20 BA0_12 BA0_4
Bits 27/ 19/11/3 DINTA_CH4 DISTS_CH4 DEDET_CH4 DASTS_CH4 BA0_27 BA0_19 BA0_11 BA0_3 BAM0_27 BAM0_19 BAM0_11 BAM0_3 BD0_27 BD0_19 BD0_11 BD0_3 BDM0_27 BDM0_19 BDM0_11 BDM0_3 BA0_27 BA0_19 BA0_11 BA0_3
Bits26/ 18/10/2 DINTA_CH5 DISTS_CH5 DEDET_CH5 DASTS_CH5 BA0_26 BA0_18 BA0_10 BA0_2 BAM0_26 BAM0_18 BAM0_10 BAM0_2 BD0_26 BD0_18 BD0_10 BD0_2 BDM0_26 BDM0_18 BDM0_10 BDM0_2 BA0_26 BA0_18 BA0_10 BA0_2
Bits 25/ 17/9/1 DINTA_CH6 DISTS_CH6 DEDET_CH6 DASTS_CH6 BA0_25 BA0_17 BA0_9 BA0_1 BAM0_25 BAM0_17 BAM0_9 BAM0_1 BD0_25 BD0_17 BD0_9 BD0_1 BDM0_25 BDM0_17 BDM0_9 BDM0_1 BA0_25 BA0_17 BA0_9 BA0_1
Bits24/ 16/8/0 DINTA_CH7 DISTS_CH7 DEDET_CH7 DASTS_CH7 BA0_24 BA0_16 BA0_8 BA0_0 BAM0_24 BAM0_16 BAM0_8 BAM0_0 BD0_24 BD0_16 BD0_8 BD0_0 BDM0_24 BDM0_16 BDM0_8 BDM0_0 BA0_24 BA0_16 BA0_8 BA0_0 UBC Module DMAC
DMISTS
DISTS_CH0
DMEDET
DEDET_CH0
DMASTS
DASTS_CH0
BAR_0
BA0_31 BA0_23 BA0_15 BA0_7
BAMR_0
BAM0_31 BAM0_23 BAM0_15 BAM0_7
BDR_0
BD0_31 BD0_23 BD0_15 BD0_7
BDMR_0
BDM0_31 BDM0_23 BDM0_15 BDM0_7
BAR_1
BA0_31 BA0_23 BA0_15 BA0_7
Rev. 2.00 Sep. 07, 2007 Page 1205 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation BAMR_1
Bits 31/ 23/15/7 BAM0_31 BAM0_23 BAM0_15 BAM0_7
Bits30/ 22/14/6 BAM0_30 BAM0_22 BAM0_14 BAM0_6 BD0_30 BD0_22 BD0_14 BD0_6 BDM0_30 BDM0_22 BDM0_14 BDM0_6 CD0_0 CD1_0 SCMFC1 PCB1 TI6
Bits 29/ 21/13/5 BAM0_29 BAM0_21 BAM0_13 BAM0_5 BD0_29 BD0_21 BD0_13 BD0_5 BDM0_29 BDM0_21 BDM0_13 BDM0_5 UBID0 ID0_1 UBID1 ID1_1 SCMFD0 PCB0 TI5
Bits28/ 20/12/4 BAM0_28 BAM0_20 BAM0_12 BAM0_4 BD0_28 BD0_20 BD0_12 BD0_4 BDM0_28 BDM0_20 BDM0_12 BDM0_4 DBE0 ID0_0 DBE1 ID1_0 SCMFD1 TI4
Bits 27/ 19/11/3 BAM0_27 BAM0_19 BAM0_11 BAM0_3 BD0_27 BD0_19 BD0_11 BD0_3 BDM0_27 BDM0_19 BDM0_11 BDM0_3 RW0_1 RW1_1 ICF OCF ACOSW3 TI3
Bits26/ 18/10/2 BAM0_26 BAM0_18 BAM0_10 BAM0_2 BD0_26 BD0_18 BD0_10 BD0_2 BDM0_26 BDM0_18 BDM0_10 BDM0_2 RW0_0 RW1_0 ACOSW2 TI2
Bits 25/ 17/9/1 BAM0_25 BAM0_17 BAM0_9 BAM0_1 BD0_25 BD0_17 BD0_9 BD0_1 BDM0_25 BDM0_17 BDM0_9 BDM0_1 CP0_1 SZ0_1 CP1_1 SZ1_1 CKS1 WT W3LOAD W2LOAD ACOSW1 TI1
Bits24/ 16/8/0 BAM0_24 BAM0_16 BAM0_8 BAM0_0 BD0_24 BD0_16 BD0_8 BD0_0 BDM0_24 BDM0_16 BDM0_8 BDM0_0 CP0_0 SZ0_0 CP1_0 SZ1_0 CKS2 BDI ICE OCE LE W3LOCK W2LOCK ACOSW0 TI0 NMIE INTC H-UDI BSC Cache Module UBC
BDR_1
BD0_31 BD0_23 BD0_15 BD0_7
BDMR_1
BDM0_31 BDM0_23 BDM0_15 BDM0_7
BBR_0
CD0_1
BBR_1
CD1_1
BRCR
SCMFC0
CCR1

CCR2

ACSWR

SDIR
TI7
ICR0
NMIL
Rev. 2.00 Sep. 07, 2007 Page 1206 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation ICR1
Bits 31/ 23/15/7 IRQ71S IRQ31S
Bits30/ 22/14/6 IRQ70S IRQ30S PINT6S IRQ6F PINT6E PINT6R E14 E6 BE0 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12 IP32 IP12
Bits 29/ 21/13/5 IRQ61S IRQ21S PINT5S IRQ5F PINT5E PINT5R E13 E5 BOVE IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11 IP31 IP11
Bits28/ 20/12/4 IRQ60S IRQ20S PINT4S IRQ4F PINT4E PINT4R E12 E4 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10 IP30 IP10
Bits 27/ 19/11/3 IRQ51S IRQ11S PINT3S IRQ3F PINT3E PINT3R E11 E3 BN3 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03 IP23 IP03
Bits26/ 18/10/2 IRQ50S IRQ10S PINT2S IRQ2F PINT2E PINT2R E10 E2 BN2 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02 IP22 IP02
Bits 25/ 17/9/1 IRQ41S IRQ01S PINT1S IRQ1F PINT1E PINT1R E9 E1 BN1 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01 IP21 IP01
Bits24/ 16/8/0 IRQ40S IRQ00S PINT0S IRQ0F PINT0E PINT0R E8 BN0 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 IP20 IP00 Module INTC
ICR2
PINT7S
IRQRR
IRQ7F
PINTER
PINT7E
PIRR
PINT7R
IBCR
E15 E7
IBNR
BE1
IPR01
IP33 IP13
IPR02
IP33 IP13
IPR05
IP33 IP13
IPR06
IP33 IP13
IPR07
IP33 IP13
IPR08
IP33 IP13
IPR09
IP33 IP13
IPR10
IP33 IP13
IPR11
IP33 IP13
IPR12
IP33 IP13
IPR13
IP33 IP13
Rev. 2.00 Sep. 07, 2007 Page 1207 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation IPR14
Bits 31/ 23/15/7 IP33 IP13
Bits30/ 22/14/6 IP32 IP12 IP32 IP12 IP32 IP12 WTIT TCNT6 RSTE IFC2 DEEP MSTP9 MSTP46 MSTP56 1Hz
Bits 29/ 21/13/5 IP31 IP11 IP31 IP11 IP31 IP11 TME TCNT5 RSTS IFC1 MSTP8 MSTP35 MSTP45 MSTP55 2Hz 10 seconds 10 minutes
Bits28/ 20/12/4 IP30 IP10 IP30 IP10 IP30 IP10 TCNT4 CKOEN IFC0 MSTP7 MSTP44 4Hz
Bits 27/ 19/11/3 IP23 IP03 IP23 IP03 IP23 IP03 TCNT3 RNGS MSTP6 MSTP33 MSTP43 MSTP53 8Hz
Bits26/ 18/10/2 IP22 IP02 IP22 IP02 IP22 IP02 CKS2 TCNT2 STC2 PFC2 MSTP5 MSTP32 MSTP42 MSTP52 16Hz
Bits 25/ 17/9/1 IP21 IP01 IP21 IP01 IP21 IP01 CKS1 TCNT1 STC1 PFC1 MSTP1 MSTP4 RAME1 RAMWE1 MSTP31 MSTP41 32Hz 1second 1 minute 1 hour
Bits24/ 16/8/0 IP20 IP00 IP20 IP00 IP20 IP00 CKS0 TCNT0 STC0 PFC0 MSTP3 RAME0 RAMWE0 MSTP40 CKDV3 64Hz RTC SYSTEM CPG WDT Module INTC
IPR15
IP33 IP13
IPR16
IP33 IP13
WTCSR
IOVF
WTCNT
TCNT7
WRCSR
WOVF
FRQCR

STBCR STBCR2 SYSCR1 SYSCR2 STBCR3 STBCR4 STBCR5 R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT
STBY MSTP10 MSTP47 MSTP57
1000 years 10 years
10 hours 10 days 10 months
Day 1 day 1 month 100 years 1 year 1 second 1 minute 1 hour
RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR
ENB ENB ENB ENB ENB ENB
10 seconds 10 minutes 10 hours 10 days 10 months Day
1 day 1 month
Rev. 2.00 Sep. 07, 2007 Page 1208 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation RCR1 RCR2 RYRAR
Bits 31/ 23/15/7 CF PEF
Bits30/ 22/14/6 PES2
Bits 29/ 21/13/5 PES1 1000 years 10 years
Bits28/ 20/12/4 CIE PES0
Bits 27/ 19/11/3 AIE RTCEN
Bits26/ 18/10/2 ADJ
Bits 25/ 17/9/1 RESET 100 years 1 year
Bits24/ 16/8/0 AF START Module RTC
RCR3 PADRH
ENB PA31DR PA23DR
PA30DR PA22DR PA14DR PA6DR PA30PR PA22PR PA14PR PA6PR PB30DR PB22DR PB14DR PB6DR PB30PR PB22PR PB14PR PB6PR PC14DR PC6DR PC22PR PC14PR PC6PR PD14DR PD6DR PD14PR PD6PR PE6PR
PA29DR PA21DR PA13DR PA5DR PA29PR PA21PR PA13PR PA5PR PB29DR PB21DR PB13DR PB5DR PB29PR PB21PR PB13PR PB5PR PC21DR PC13DR PC5DR PC21PR PC13PR PC5PR PD13DR PD5DR PD13PR PD5PR PE5PR
PA28DR PA20DR PA12DR PA4DR PA28PR PA20PR PA12PR PA4PR PB28DR PB20DR PB12DR PB4DR PB28PR PB20PR PB12PR PB4PR PC20DR PC12DR PC4DR PC20PR PC12PR PC4PR PD12DR PD4DR PD12PR PD4PR PE4PR
PA27DR PA19DR PA11DR PA3DR PA27PR PA19PR PA11PR PA3PR PB27DR PB19DR PB11DR PB3DR PB27PR PB19PR PB11PR PB3PR PC19DR PC11DR PC3DR PC19PR PC11PR PC3PR PD11DR PD3DR PD11PR PD3PR PE3PR
PA26DR PA18DR PA10DR PA2DR PA26PR PA18PR PA10PR PA2PR PB26DR PB18DR PB10DR PB2DR PB26PR PB18PR PB10PR PB2PR PC18DR PC10DR PC2DR PC18PR PC10PR PC2PR PD10DR PD2DR PD10PR PD2PR PE2PR
PA25DR PA17DR PA9DR PA1DR PA25PR PA17PR PA9PR PA1PR PB25DR PB17DR PB9DR PB1DR PB25PR PB17PR PB9PR PB1PR PC17DR PC9DR PC1DR PC25PR PC17PR PC9PR PC1PR PD9DR PD1DR PD9PR PD1PR PE1PR
PA24DR PA16DR PA8DR PA0DR PA24PR PA16PR PA8PR PA0PR PB24DR PB16DR PB8DR PB0DR PB24PR PB16PR PB8PR PB0PR PC16DR PC8DR PC0DR PC24PR PC16PR PC8PR PC0PR PD8DR PD0DR PD16PR PD8PR PD0PR PE0PR I/O Ports
PADRL
PA15DR PA7DR
PAPRH
PA31PR PA23PR
PAPRL
PA15PR PA7PR
PBDRH
PB31DR PB23DR
PBDRL
PB15DR PB7DR
PBPRH
PB31PR PB23PR
PBPRL
PB15PR PB7PR
PCDRH

PCDRL
PC15DR PC7DR
PCPRH
PC23PR
PCPRL
PC15PR PC7PR
PDDR
PD7DR
PDPRH

PDPRL
PD15PR PD7PR
PEPR
PE7PR
Rev. 2.00 Sep. 07, 2007 Page 1209 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation PFDR
Bits 31/ 23/15/7 PF7DR
Bits30/ 22/14/6 PF6DR PF6PR PA30IOR PA22IOR PA14IOR PA6IOR PA27MD2 PA25MD2 PB30IOR PB22IOR PB14IOR PB6IOR PB29MD2 PB25MD2 PB21MD2
Bits 29/ 21/13/5 PF5DR PF5PR PA29IOR PA21IOR PA13IOR PA5IOR PA31MD1 PA29MD1 PA27MD1 PA25MD1 PB29IOR PB21IOR PB13IOR PB5IOR PB31MD1 PB29MD1 PB27MD1 PB25MD1 PB23MD1 PB21MD1
Bits28/ 20/12/4 PF4DR PF4PR PA28IOR PA20IOR PA12IOR PA4IOR PA31MD0 PA29MD0 PA27MD0 PA25MD0 PA23MD0 PA21MD0 PA19MD0 PA17MD0 PA15MD0 PA13MD0 PA11MD0 PA9MD0 PA7MD0 PA5MD0 PA3MD0 PA1MD0 PB28IOR PB20IOR PB12IOR PB4IOR PB31MD0 PB29MD0 PB27MD0 PB25MD0 PB23MD0 PB21MD0
Bits 27/ 19/11/3 PF3DR PF3PR PA27IOR PA19IOR PA11IOR PA3IOR PB27IOR PB19IOR PB11IOR PB3IOR
Bits26/ 18/10/2 PF2DR PF2PR PA26IOR PA18IOR PA10IOR PA2IOR PA26MD2 PB26IOR PB18IOR PB10IOR PB2IOR PB30MD2 PB28MD2 PB26MD2 PB24MD2 PB22MD2 PB20MD2
Bits 25/ 17/9/1 PF1DR PF1PR PA25IOR PA17IOR PA9IOR PA1IOR PA30MD1 PA28MD1 PA26MD1 PA24MD1 PB25IOR PB17IOR PB9IOR PB1IOR PB30MD1 PB28MD1 PB26MD1 PB24MD1 PB22MD1 PB20MD1
Bits24/ 16/8/0 PF0DR PF0PR PA24IOR PA16IOR PA8IOR PA0IOR PA30MD0 PA28MD0 PA26MD0 PA24MD0 PA22MD0 PA20MD0 PA18MD0 PA16MD0 PA14MD0 PA12MD0 PA10MD0 PA8MD0 PA6MD0 PA4MD0 PA2MD0 PA0MD0 PB24IOR PB16IOR PB8IOR PB0IOR PB30MD0 PB28MD0 PB26MD0 PB24MD0 PB22MD0 PB20MD0 PFC Module I/O Ports
PFPR
PF7PR
PAIORH
PA31IOR PA23IOR
PAIORL
PA15IOR PA7IOR
PACR8

PACR7

PACR6

PACR5

PACR4

PACR3

PACR2

PACR1

PBIORH
PB31IOR PB23IOR
PBIORL
PB15IOR PB7IOR
PBCR8

PBCR7

PBCR6

Rev. 2.00 Sep. 07, 2007 Page 1210 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation PBCR5
Bits 31/ 23/15/7
Bits30/ 22/14/6 PC14IOR PC6IOR PD14IOR PD6IOR
Bits 29/ 21/13/5 PB19MD1 PB17MD1 PC21IOR PC13IOR PC5IOR PC25MD1 PC23MD1 PC21MD1 PC11MD1 PC5MD1 PC3MD1 PD13IOR PD5IOR PD15MD1 PD13MD1
Bits28/ 20/12/4 PB19MD0 PB17MD0 PB15MD0 PB13MD0 PB11MD0 PB9MD0 PB7MD0 PB5MD0 PB3MD0 PB1MD0 PC20IOR PC12IOR PC4IOR PC25MD0 PC23MD0 PC21MD0 PC19MD0 PC17MD0 PC15MD0 PC13MD0 PC11MD0 PC9MD0 PC7MD0 PC5MD0 PC3MD0 PC1MD0 PD12IOR PD4IOR PD15MD0 PD13MD0
Bits 27/ 19/11/3 PC19IOR PC11IOR PC3IOR PD11IOR PD3IOR
Bits26/ 18/10/2 PC18IOR PC10IOR PC2IOR PD10IOR PD2IOR
Bits 25/ 17/9/1 PB18MD1 PB16MD1 PC17IOR PC9IOR PC1IOR PC24MD1 PC22MD1 PC20MD1 PC12MD1 PC6MD1 PC4MD1 PC2MD1 PD9IOR PD1IOR PD16MD1 PD14MD1 PD12MD1
Bits24/ 16/8/0 PB18MD0 PB16MD0 PB14MD0 PB12MD0 PB10MD0 PB8MD0 PB6MD0 PB4MD0 PB2MD0 PB0MD0 PC16IOR PC8IOR PC0IOR PC24MD0 PC22MD0 PC20MD0 PC18MD0 PC16MD0 PC14MD0 PC12MD0 PC10MD0 PC8MD0 PC6MD0 PC4MD0 PC2MD0 PC0MD0 PD8IOR PD0IOR PD16MD0 PD14MD0 PD12MD0 Module PFC
PBCR4

PBCR3

PBCR2

PBCR1

PCIORH

PCIORL
PC15IOR PC7IOR
PCCR7

PCCR6

PCCR5

PCCR4

PCCR3

PCCR2

PCCR1

PDIOR
PD7IOR
PDCR5

PDCR4

Rev. 2.00 Sep. 07, 2007 Page 1211 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation PDCR3
Bits 31/ 23/15/7
Bits30/ 22/14/6 PF6IOR CCLR1 CCLR1 BFE BFE IOB2 IOD2 IOB2 IOD2 TTGE2 BDC PSYE BF0
Bits 29/ 21/13/5 PD11MD1 PD9MD1 PD7MD1 PD5MD1 PF5IOR PF5MD1 PF1MD1 CCLR0 CCLR0 BFB BFB IOB1 IOD1 IOB1 IOD1 OE4D N OLS3N
Bits28/ 20/12/4 PD11MD0 PD9MD0 PD7MD0 PD5MD0 PD3MD0 PD1MD0 PE7MD0 PE5MD0 PE3MD0 PE1MD0 PF4IOR PF7MD0 PF5MD0 PF3MD0 PF1MD0 CKEG1 CKEG1 BFA BFA IOB0 IOD0 IOB0 IOD0 TCIEV TCIEV OE4C P OLS3P
Bits 27/ 19/11/3 PF3IOR CKEG0 CKEG0 MD3 MD3 IOA3 IOC3 IOA3 IOC3 TGIED TGIED OE3D FB TOCL OLS2N
Bits26/ 18/10/2 PF2IOR TPSC2 TPSC2 MD2 MD2 IOA2 IOC2 IOA2 IOC2 TGIEC TGIEC OE4B WF TOCS OLS2P
Bits 25/ 17/9/1 PD10MD1 PD8MD1 PD6MD1 PD4MD1 PF1IOR PF6MD1 PF4MD1 PF2MD1 PF0MD1 TPSC1 TPSC1 MD1 MD1 IOA1 IOC1 IOA1 IOC1 TGIEB TGIEB OE4A VF OLSN OLS1N
Bits24/ 16/8/0 PD10MD0 PD8MD0 PD6MD0 PD4MD0 PD2MD0 PD0MD0 PE6MD0 PE4MD0 PE2MD0 PE0MD0 PF0IOR PF6MD0 PF4MD0 PF2MD0 PF0MD0 TPSC0 TPSC0 MD0 MD0 IOA0 IOC0 IOA0 IOC0 TGIEA TGIEA OE3B UF PLSP OLS1P MTU2 Module PFC
PDCR2

PDCR1

PECR2

PECR1

PFIOR
PF7IOR
PFCR2

PFCR1

TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3
CCLR2 CCLR2 IOB3 IOD3 IOB3 IOD3 TTGE TTGE BF1
TCNT_4
TCDR
Rev. 2.00 Sep. 07, 2007 Page 1212 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TDDR
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module MTU2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TCNTS
TCBR
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TSR_3 TSR_4 TITCR TITCNT TBTCR TDER TOLBR TBTM_3 TBTM_4 TADCR
TCFD TCFD T3AEN BF1 UT4AE
3ACOR2 3ACNT2 BF0 DT4AE
3ACOR1 3ACNT1 OLS3N UT4BE
TCFV TCFV 3ACOR0 3ACNT0 OLS3P DT4BE
TGFD TGFD T4VEN OLS2N ITA3AE
TGFC TGFC 4VCOR2 4VCNT2 OLS2P ITA4VE
TGFB TGFB 4VCOR1 4VCNT1 BTE1 OLS1N TTSB TTSB ITB3AE
TGFA TGFA 4VCOR0 4VCNT0 BTE0 TDER OLS1P TTSA TTSA ITB4VE
TADCORA_4
TADCORB_4
Rev. 2.00 Sep. 07, 2007 Page 1213 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TADCOBRA_4
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module MTU2
TADCOBRB_4
TWCR TSTR TSYR TCSYSTR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0
CCE CST4 SYNC4 SCH0 CCLR2 IOB3 IOD3 TTGE TCFD
CST3 SYNC3 SCH1 CCLR1 BFE IOB2 IOD2
SCH2 CCLR0 BFB IOB1 IOD1
SCH3 CKEG1 BFA IOB0 IOD0 TCIEV TCFV
SCH4 CKEG0 MD3 IOA3 IOC3 TGIED TGFD
CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
CST1 SYNC1 SCH3S TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
WRE CST0 SYNC0 SCH4S RWE TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRE_0
TGRF_0
TIER2_0 TSR2_0 TBTM TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1
TTGE2 CCLR2 IOB3 TTGE TCFD
CCLR1 BFE IOB2
CCLR0 BFB IOB1 TCIEU TCFU
CKEG1 BFA IOB0 TCIEV TCFV
CKEG0 MD3 IOA3 TGFD
TTSE TPSC2 MD2 IOA2 TGFC
TGIEF TGFF TTSB TPSC1 MD1 IOA1 TGIEB TGFB
TGIEE TGFE TTSA TPSC0 MD0 IOA0 TGIEA TGFA
Rev. 2.00 Sep. 07, 2007 Page 1214 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TCNT_1
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module MTU2
TGRA_1
TGRB_1
TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2
CCLR2 IOB3 TTGE TCFD
CCLR1 BFE IOB2
CCLR0 BFB IOB1 TCIEU TCFU
CKEG1 BFA IOB0 TCIEV TCFV
I2BE CKEG0 MD3 IOA3 TGFD
I2AE TPSC2 MD2 IOA2 TGFC
I1BE TPSC1 MD1 IOA1 TGIEB TGFB
I1AE TPSC0 MD0 IOA0 TGIEA TGFA
TGRA_2
TGRB_2
TCNTU_5
TGRU_5
TCRU_5 TIORU_5 TCNTV_5

IOC4
IOC3
IOC2
TPSC1 IOC1
TPSC0 IOC0
TGRV_5
TCRV_5 TIORV_5 TCNTW_5

IOC4
IOC3
IOC2
TPSC1 IOC1
TPSC0 IOC0
TGRW_5
TCRW_5 TIORW_5

IOC4
IOC3
IOC2
TPSC1 IOC1
TPSC0 IOC0
Rev. 2.00 Sep. 07, 2007 Page 1215 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TSR_5 TIER_5 TSTR_5 TCNTCMPCLR T8TCR_0 T8TCR_1 T8TCSR_0 T8TCSR_1 T8TCORA_0 T8TCORA_1 T8TCORB_0 T8TCORB_1 T8TCNT_0 T8TCNT_1 T8TCCR_0 T8TCCR_1 ADDRA
Bits 31/ 23/15/7 CMIEB CMIEB CMFB CMFB
Bits30/ 22/14/6 CMIEA CMIEA CMFA CMFA
Bits 29/ 21/13/5 OVIE OVIE OVF OVF
Bits28/ 20/12/4 CCLR1 CCLR1 ADTE ADTE
Bits 27/ 19/11/3 CCLR0 CCLR0 OS3 OS3
Bits26/ 18/10/2 CMFU5 TGIE5U CSTU5 CMPCLR5U CKS2 CKS2 OS2 OS2
Bits 25/ 17/9/1 CMFV5 TGIE5V CSTV5 CMPCLR5V CKS1 CKS1 OS1 OS1
Bits24/ 16/8/0 CMFW5 TGIE5W CSTW5 CMPCLR5W CKS0 CKS0 OS0 OS0 TMR Module MTU2

TMRIS TMRIS

ICKS1 ICKS1
ICKS0 ICKS0 ADC
ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH ADCSR ADF CKS1 DADR0 DADR1 DACR DAOE1 DAOE0 DAE ADIE CKS0 ADST MDS2 MDS1

TRGS1 MDS0
TRGS0 CH2
CH1
CH0 DAC

Rev. 2.00 Sep. 07, 2007 Page 1216 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SCSMR_0
Bits 31/ 23/15/7 C/A
Bits30/ 22/14/6 CHR
Bits 29/ 21/13/5 PE
Bits28/ 20/12/4 O/E
Bits 27/ 19/11/3 STOP
Bits26/ 18/10/2
Bits 25/ 17/9/1 CKS1
Bits24/ 16/8/0 CKS0 Module SCIF
SCBRR_0 SCSCR_0 TIE SCFTDR_0 SCFSR_0 PER3 ER SCFRDR_0 SCFCR_0 RTRG1 SCFDR_0 SCSPTR_0 RTSIO SCLSR_0 SCSMR_1 C/A SCBRR_1 SCSCR_1 TIE SCFTDR_1 SCFSR_1 PER3 ER SCFRDR_1 SCFCR_1 RTRG1 SCFDR_1 SCSPTR_1 RTSIO SCLSR_1 SCSMR_2 C/A RTRG0 RTSDT CHR TTRG1 CTSIO PE TTRG0 T4 R4 CTSDT O/E MCE T3 R3 SCKIO STOP RSTRG2 TFRST T2 R2 SCKDT RSTRG1 RFRST T1 R1 SPB2IO CKS1 RSTRG0 LOOP T0 R0 SPB2DT ORER CKS0 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR RIE TE RE REIE CKE1 CKE0 RTRG0 RTSDT CHR TTRG1 CTSIO PE TTRG0 T4 R4 CTSDT O/E MCE T3 R3 SCKIO STOP RSTRG2 TFRST T2 R2 SCKDT RSTRG1 RFRST T1 R1 SPB2IO CKS1 RSTRG0 LOOP T0 R0 SPB2DT ORER CKS0 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR RIE TE RE REIE CKE1 CKE0
Rev. 2.00 Sep. 07, 2007 Page 1217 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SCBRR_2 SCSCR_2
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module SCIF
TIE
RIE
TE
RE
REIE

CKE1
CKE0
SCFTDR_2 SCFSR_2 PER3 ER SCFRDR_2 SCFCR_2 RTRG1 SCFDR_2 SCSPTR_2 RTSIO SCLSR_2 SCSMR_3 C/A SCBRR_3 SCSCR_3 TIE SCFTDR_3 SCFSR_3 PER3 ER SCFRDR_3 SCFCR_3 RTRG1 SCFDR_3 SCSPTR_3 RTSIO SCLSR_3 SCSMR_4 C/A SCBRR_4 SCSCR_4 TIE RIE TE RE REIE CKE1 CKE0 RTRG0 RTSDT CHR TTRG1 CTSIO PE TTRG0 T4 R4 CTSDT O/E MCE T3 R3 SCKIO STOP RSTRG2 TFRST T2 R2 SCKDT RSTRG1 RFRST T1 R1 SPB2IO CKS1 RSTRG0 LOOP T0 R0 SPB2DT ORER CKS0 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR RIE TE RE REIE CKE1 CKE0 RTRG0 RTSDT CHR TTRG1 CTSIO PE TTRG0 T4 R4 CTSDT O/E MCE T3 R3 SCKIO STOP RSTRG2 TFRST T2 R2 SCKDT RSTRG1 RFRST T1 R1 SPB2IO CKS1 RSTRG0 LOOP T0 R0 SPB2DT ORER CKS0 PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR
Rev. 2.00 Sep. 07, 2007 Page 1218 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SCFTDR_4 SCFSR_4
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module SCIF
PER3 ER
PER2 TEND
PER1 TDFE
PER0 BRK
FER3 FER
FER2 PER
FER1 RDF
FER0 DR
SCFRDR_4 SCFCR_4 RTRG1 SCFDR_4 SCSPTR_4 RTSIO SCLSR_4 SCSMR_5 C/A SCBRR_5 SCSCR_5 TIE SCFTDR_5 SCFSR_5 PER3 ER SCFRDR_5 SCFCR_5 RTRG1 SCFDR_5 SCSPTR_5 RTSDT SCLSR_5 ORER SCSMR_6 C/A SCBRR_6 SCSCR_6 TIE SCFTDR_6 SCFSR_6 PER3 ER PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR RIE TE RE REIE CKE1 CKE0 CHR PE O/E STOP CKS1 CKS0 RTRG0 CTSIO TTRG1 CTSDT TTRG0 T4 R4 SCKIO MCE T3 R3 SCKDT RSTRG2 TFRST T2 R2 SPB2IO RSTRG1 RFRST T1 R1 SPB2DT RSTRG0 LOOP T0 R0 RTSDT PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR RIE TE RE REIE CKE1 CKE0 RTRG0 RTSDT CHR TTRG1 CTSIO PE TTRG0 T4 R4 CTSDT O/E MCE T3 R3 SCKIO STOP RSTRG2 TFRST T2 R2 SCKDT RSTRG1 RFRST T1 R1 SPB2IO CKS1 RSTRG0 LOOP T0 R0 SPB2DT ORER CKS0
Rev. 2.00 Sep. 07, 2007 Page 1219 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SCFRDR_6 SCFCR_6
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module SCIF
RTRG1
RTRG0 RTSDT CHR
TTRG1 CTSIO PE
TTRG0 T4 R4 CTSDT O/E
MCE T3 R3 SCKIO STOP
RSTRG2 TFRST T2 R2 SCKDT
RSTRG1 RFRST T1 R1 SPB2IO CKS1
RSTRG0 LOOP T0 R0 SPB2DT ORER CKS0
SCFDR_6

SCSPTR_6
RTSIO
SCLSR_6

SCSMR_7
C/A
SCBRR_7 SCSCR_7 TIE SCFTDR_7 SCFSR_7 PER3 ER SCFRDR_7 SCFCR_7 RTRG1 SCFDR_7 SCSPTR_7 RTSIO SCLSR_7 SSICR_0 CHNL1 SCKD SSISR_0 RTRG0 RTSDT CHNL0 SWSD CKDV2 TTRG1 CTSIO DWL2 SCKP CKDV1 TTRG0 T4 R4 CTSDT DMEN DWL1 SWSP CKDV0 DMRQ MCE T3 R3 SCKIO UIEN DWL0 SPDP MUEN UIRQ CHNO1 RSTRG2 TFRST T2 R2 SCKDT OIEN SWL2 SDTA OIEN CHNO0 RSTRG1 RFRST T1 R1 SPB2IO IIEN SWL1 PDTA TRMD IIRQ SWNO RSTRG0 LOOP T0 R0 SPB2DT ORER DIEN SWL0 DEL EN DIRQ IDST SSI PER2 TEND PER1 TDFE PER0 BRK FER3 FER FER2 PER FER1 RDF FER0 DR RIE TE RE REIE CKE1 CKE0
Rev. 2.00 Sep. 07, 2007 Page 1220 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SSITDR_0
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module SSI
SSIRDR_0
SSICR_1
CHNL1 SCKD
CHNL0 SWSD CKDV2
DWL2 SCKP CKDV1
DMEN DWL1 SWSP CKDV0 DMRQ
UIEN DWL0 SPDP MUEN UIRQ CHNO1
OIEN SWL2 SDTA OIEN CHNO0
IIEN SWL1 PDTA TRMD IIRQ SWNO
DIEN SWL0 DEL EN DIRQ IDST
SSISR_1

SSITDR_1
SSIRDR_1
ICCR1_0 ICCR2_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 NF2CYC_0 ICCR1_1 ICCR2_1
ICE BBSY MLS TIE TDRE SVA6
RCVD SCP WAIT TEIE TEND SVA5
MST SDAO RIE RDRF SVA4
TRS SDAOP NAKIE NACKF SVA3
CKS3 SCL BCWP STIE STOP SVA2
CKS2 BS2 ACKE AL_OVE SVA1
CKS1 IICRST BC1 ACKBR AAS SVA0
CKS0 BC0 ACKBT ADZ FS
IIC3
ICE BBSY
RCVD SCP
MST SDAO
TRS SDAOP
CKS3 SCL
CKS2
CKS1 IICRST
NF2CYC CKS0
Rev. 2.00 Sep. 07, 2007 Page 1221 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 NF2CYC_1 ICCR1_2 ICCR2_2 ICMR_2 ICIER_2 ICSR_2 SAR_2 ICDRT_2 ICDRR_2 NF2CYC_2 MCR_0
Bits 31/ 23/15/7 MLS TIE TDRE SVA6
Bits30/ 22/14/6 WAIT TEIE TEND SVA5
Bits 29/ 21/13/5 RIE RDRF SVA4
Bits28/ 20/12/4 NAKIE NACKF SVA3
Bits 27/ 19/11/3 BCWP STIE STOP SVA2
Bits26/ 18/10/2 BS2 ACKE AL_OVE SVA1
Bits 25/ 17/9/1 BC1 ACKBR AAS SVA0
Bits24/ 16/8/0 BC0 ACKBT ADZ FS Module IIC3
ICE BBSY MLS TIE TDRE SVA6
RCVD SCP WAIT TEIE TEND SVA5
MST SDAO RIE RDRF SVA4
TRS SDAOP NAKIE NACKF SVA3
CKS3 SCL BCWP STIE STOP SVA2
CKS2 BS2 ACKE AL_OVE SVA1
CKS1 IICRST BC1 ACKBR AAS SVA0
NF2CYC CKS0 BC0 ACKBT ADZ FS
MCR15 MCR7
MCR14 MCR6 TGS1_2 BRP6 IRR6 IMR14 IMR6 TEC6 REC6 TXPR1_14 TXPR1_6 TXPR0_14 TXPR0_6 TXCR0_14 TXCR0_6
MCR5 GSR5 TGS1_1 SJW1 BRP5 IRR13 IRR5 IMR13 IMR5 TEC5 REC5 TXPR1_13 TXPR1_5 TXPR0_13 TXPR0_5 TXCR0_13 TXCR0_5
GSR4 TGS1_0 SJW0 BRP4 IRR12 IRR4 IMR12 IMR4 TEC4 REC4 TXPR1_12 TXPR1_4 TXPR0_12 TXPR0_4 TXCR0_12 TXCR0_4
GSR3 BRP3 IRR3 IMR11 IMR3 TEC3 REC3 TXPR1_11 TXPR1_3 TXPR0_11 TXPR0_3 TXCR0_11 TXCR0_3
TST2 MCR2 GSR2 TGS2_2 BRP2 IRR2 IMR10 IMR2 TEC2 REC2 TXPR1_10 TXPR1_2 TXPR0_10 TXPR0_2 TXCR0_10 TXCR0_2
TST1 MCR1 GSR1 TGS2_1 BRP1 IRR9 IRR1 IMR9 IMR1 TEC1 REC1 TXPR1_9 TXPR1_1 TXPR0_9 TXPR0_1 TXCR0_9 TXCR0_1
NF2CYC TST0 MCR0 GSR0 TGS2_0 BSP BRP0 IRR8 IRR0 IMR8 IMR0 TEC0 REC0 TXPR1_8 TXPR1_0 TXPR0_8 TXCR0_8 RCAN-ET
GSR_0

BCR1_0
TGS1_3
BCR0_0
BRP7
IRR_0
IRR7
IMR_0
IMR15 IMR7
TEC_0/REC_0
TEC7 REC7
TXPR1_0
TXPR1_15 TXPR1_7
TXPR0_0
TXPR0_15 TXPR0_7
TXCR0_0
TXCR0_15 TXCR0_7
Rev. 2.00 Sep. 07, 2007 Page 1222 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TXACK0_0
Bits 31/ 23/15/7 TXACK0_15 TXACK0_7
Bits30/ 22/14/6 TXACK0_14 TXACK0_6 ABACK0_14 ABACK0_6 RXPR0_14 RXPR0_6 RFPR0_14 RFPR0_6 MBIMR0_14 MBIMR0_6 UMSR0_14 UMSR0_6 RTR STDID4
Bits 29/ 21/13/5 TXACK0_13 TXACK0_5 ABACK0_13 ABACK0_5 RXPR0_13 RXPR0_5 RFPR0_13 RFPR0_5 MBIMR0_13 MBIMR0_5 UMSR0_13 UMSR0_5 STDID3
Bits28/ 20/12/4 TXACK0_12 TXACK0_4 ABACK0_12 ABACK0_4 RXPR0_12 RXPR0_4 RFPR0_12 RFPR0_4 MBIMR0_12 MBIMR0_4 UMSR0_12 UMSR0_4 STDID10 STDID2
Bits 27/ 19/11/3 TXACK0_11 TXACK0_3 ABACK0_11 ABACK0_3 RXPR0_11 RXPR0_3 RFPR0_11 RFPR0_3 MBIMR0_11 MBIMR0_3 UMSR0_11 UMSR0_3 STDID9 STDID1
Bits26/ 18/10/2 TXACK0_10 TXACK0_2 ABACK0_10 ABACK0_2 RXPR0_10 RXPR0_2 RFPR0_10 RFPR0_2 MBIMR0_10 MBIMR0_2 UMSR0_10 UMSR0_2 STDID8 STDID0
Bits 25/ 17/9/1 TXACK0_9 TXACK0_1 ABACK0_9 ABACK0_1 RXPR0_9 RXPR0_1 RFPR0_9 RFPR0_1 MBIMR0_9 MBIMR0_1 UMSR0_9 UMSR0_1 STDID7 EXTID17
Bits24/ 16/8/0 TXACK0_8 ABACK0_8 RXPR0_8 RXPR0_0 RFPR0_8 RFPR0_0 MBIMR0_8 MBIMR0_0 UMSR0_8 UMSR0_0 STDID6 EXTID16 Module RCAN-ET
ABACK0_0
ABACK0_15 ABACK0_7
RXPR0_0
RXPR0_15 RXPR0_7
RFPR0_0
RFPR0_15 RFPR0_7
MBIMR0_0
MBIMR0_15 MBIMR0_7
UMSR0_0
UMSR0_15 UMSR0_7
MB[0]. CONTROL0H (MCR15 = 1) MB[0]. CONTROL0H (MCR15 = 0) MB[0]. CONTROL0L MB[0]. LAFMH (MCR15 = 1)
IDE STDID5
STDID3
STDID10 STDID2
STDID9 STDID1
STDID8 STDID0
STDID7 RTR
STDID6 IDE
STDID5 EXTID17
STDID4 EXTID16
EXTID15 EXTID7 IDE_LAFM
EXTID14 EXTID6
EXTID13 EXTID5
EXTID12 EXTID4 STDID_ LAFM10
EXTID11 EXTID3 STDID_ LAFM9 STDID_ LAFM1 STDID_ LAFM7
EXTID10 EXTID2 STDID_ LAFM8 STDID_ LAFM0 STDID_ LAFM6 IDE_ LAFM
EXTID9 EXTID1 STDID_ LAFM7 EXTID_ LAFM17 STDID_ LAFM5 EXTID_ LAFM17 EXTID_ LAFM9 EXTID_ LAFM1
EXTID8 EXTID:0 STDID_ LAFM6 EXTID_ LAFM16 STDID_ LAFM4 EXTID_ LAFM16 EXTID_ LAFM8 EXTID_ LAFM0
STDID_ LAFM5
STDID_ LAFM4 STDID_ LAFM10
STDID_ LAFM3 STDID_ LAFM9 STDID_ LAFM1 EXTID_ LAFM13 EXTID_ LAFM5
STDID_ LAFM2 STDID_ LAFM8 STDID_ LAFM0 EXTID_ LAFM12 EXTID_ LAFM4
MB[0]. LAFMH (MCR15 = 0)
STDID_ LAFM3
STDID_ LAFM2 EXTID_ LAFM14 EXTID_ LAFM6
MB[0]. LAFML
EXTID_ LAFM15 EXTID_ LAFM7
EXTID_ LAFM11 EXTID_ LAFM3 MSG_DATA_0
EXTID_ LAFM10 EXTID_ LAFM2
MB[0]. MSG_DATA[0] MB[0]. MSG_DATA[1] MB[0]. MSG_DATA[2] MB[0]. MSG_DATA[3]
MSG_DATA_1
MSG_DATA_2
MSG_DATA_3
Rev. 2.00 Sep. 07, 2007 Page 1223 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation MB[0]. MSG_DATA[4] MB[0]. MSG_DATA[5] MB[0]. MSG_DATA[6] MB[0]. MSG_DATA[7] MB[0]. CONTROL1H MB[0]. CONTROL1L MB[1 to 15] CONTROL0H (MCR15 = 1) MB[1 to 15]. CONTROL0H (MCR15 = 0) MB[1 to 15]. CONTROL0L MB[1 to 15]. LAFMH (MCR15 = 1)
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3 MSG_DATA_4
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module RCAN-ET
MSG_DATA_5
MSG_DATA_6
MSG_DATA_7
NMC
MBC2
MBC1
MBC0

DLC3
DLC2
DLC1
DLC0
IDE STDID5
RTR STDID4
STDID3
STDID10 STDID2
STDID9 STDID1
STDID8 STDID0
STDID7 EXTID17
STDID6 EXTID16
STDID3
STDID10 STDID2
STDID9 STDID1
STDID8 STDID0
STDID7 RTR
STDID6 IDE
STDID5 EXTID17
STDID4 EXTID16
EXTID15 EXTID7 IDE_LAFM
EXTID14 EXTID6
EXTID13 EXTID5
EXTID12 EXTID4 STDID_ LAFM10
EXTID11 EXTID3 STDID_ LAFM9 STDID_ LAFM1 STDID_ LAFM7
EXTID10 EXTID2 STDID_ LAFM8 STDID_ LAFM0 STDID_ LAFM6 IDE_ LAFM
EXTID9 EXTID1 STDID_ LAFM7 EXTID_ LAFM17 STDID_ LAFM5 EXTID_ LAFM17 EXTID_ LAFM9 EXTID_ LAFM1
EXTID8 EXTID:0 STDID_ LAFM6 EXTID_ LAFM16 STDID_ LAFM4 EXTID_ LAFM16 EXTID_ LAFM8 EXTID_ LAFM0
STDID_ LAFM5
STDID_ LAFM4 STDID_ LAFM10
STDID_ LAFM3 STDID_ LAFM9 STDID_ LAFM1 EXTID_ LAFM13 EXTID_ LAFM5
STDID_ LAFM2 STDID_ LAFM8 STDID_ LAFM0 EXTID_ LAFM12 EXTID_ LAFM4
MB[1 to 15]. LAFMH (MCR15 = 0)
STDID_ LAFM3
STDID_ LAFM2 EXTID_ LAFM14 EXTID_ LAFM6
MB[1 to 15]. LAFML
EXTID_ LAFM15 EXTID_ LAFM7
EXTID_ LAFM11 EXTID_ LAFM3 MSG_DATA_0
EXTID_ LAFM10 EXTID_ LAFM2
MB[1 to 15]. MSG_DATA[0] MB[1 to 15]. MSG_DATA[1] MB[1 to 15]. MSG_DATA[2] MB[1 to 15]. MSG_DATA[3] MB[1 to 15]. MSG_DATA[4]
MSG_DATA_1
MSG_DATA_2
MSG_DATA_3
MSG_DATA_4
Rev. 2.00 Sep. 07, 2007 Page 1224 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation MB[1 to 15]. MSG_DATA[5] MB[1 to 15]. MSG_DATA[6] MB[1 to 15]. MSG_DATA[7] MB[1 to 15]. CONTROL1H MB[1 to 15]. CONTROL1L MCR_1
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3 MSG_DATA_5
Bits26/ 18/10/2
Bits 25/ 17/9/1
Bits24/ 16/8/0 Module RCAN-ET
MSG_DATA_6
MSG_DATA_7
NMC
ATX
DART
MBC2
MBC1
MBC0

DLC3
DLC2
DLC1
DLC0
MCR15 MCR7
MCR14 MCR6 TGS1_2 BRP6 IRR6 IMR14 IMR6 TEC6 REC6 TXPR1_14 TXPR1_6 TXPR0_14 TXPR0_6 TXCR0_14 TXCR0_6 TXACK0_14 TXACK0_6 ABACK0_14 ABACK0_6 RXPR0_14 RXPR0_6 RFPR0_14 RFPR0_6
MCR5 GSR5 TGS1_1 SJW1 BRP5 IRR13 IRR5 IMR13 IMR5 TEC5 REC5 TXPR1_13 TXPR1_5 TXPR0_13 TXPR0_5 TXCR0_13 TXCR0_5 TXACK0_13 TXACK0_5 ABACK0_13 ABACK0_5 RXPR0_13 RXPR0_5 RFPR0_13 RFPR0_5
GSR4 TGS1_0 SJW0 BRP4 IRR12 IRR4 IMR12 IMR4 TEC4 REC4 TXPR1_12 TXPR1_4 TXPR0_12 TXPR0_4 TXCR0_12 TXCR0_4 TXACK0_12 TXACK0_4 ABACK0_12 ABACK0_4 RXPR0_12 RXPR0_4 RFPR0_12 RFPR0_4
GSR3 BRP3 IRR3 IMR11 IMR3 TEC3 REC3 TXPR1_11 TXPR1_3 TXPR0_11 TXPR0_3 TXCR0_11 TXCR0_3 TXACK0_11 TXACK0_3 ABACK0_11 ABACK0_3 RXPR0_11 RXPR0_3 RFPR0_11 RFPR0_3
TST2 MCR2 GSR2 TGS2_2 BRP2 IRR2 IMR10 IMR2 TEC2 REC2 TXPR1_10 TXPR1_2 TXPR0_10 TXPR0_2 TXCR0_10 TXCR0_2 TXACK0_10 TXACK0_2 ABACK0_10 ABACK0_2 RXPR0_10 RXPR0_2 RFPR0_10 RFPR0_2
TST1 MCR1 GSR1 TGS2_1 BRP1 IRR9 IRR1 IMR9 IMR1 TEC1 REC1 TXPR1_9 TXPR1_1 TXPR0_9 TXPR0_1 TXCR0_9 TXCR0_1 TXACK0_9 TXACK0_1 ABACK0_9 ABACK0_1 RXPR0_9 RXPR0_1 RFPR0_9 RFPR0_1
TST0 MCR0 GSR0 TGS2_0 BSP BRP0 IRR8 IRR0 IMR8 IMR0 TEC0 REC0 TXPR1_8 TXPR1_0 TXPR0_8 TXCR0_8 TXACK0_8 ABACK0_8 RXPR0_8 RXPR0_0 RFPR0_8 RFPR0_0
GSR_1

BCR1_1
TGS1_3
BCR0_1
BRP7
IRR_1
IRR7
IMR_1
IMR15 IMR7
TEC_1/REC_1
TEC7 REC7
TXPR1_1
TXPR1_15 TXPR1_7
TXPR0_1
TXPR0_15 TXPR0_7
TXCR0_1
TXCR0_15 TXCR0_7
TXACK0_1
TXACK0_15 TXACK0_7
ABACK0_1
ABACK0_15 ABACK0_7
RXPR0_1
RXPR0_15 RXPR0_7
RFPR0_1
RFPR0_15 RFPR0_7
Rev. 2.00 Sep. 07, 2007 Page 1225 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation MBIMR0_1
Bits 31/ 23/15/7 MBIMR0_15 MBIMR0_7
Bits30/ 22/14/6 MBIMR0_14 MBIMR0_6 UMSR0_14 UMSR0_6 RTR STDID4
Bits 29/ 21/13/5 MBIMR0_13 MBIMR0_5 UMSR0_13 UMSR0_5 STDID3
Bits28/ 20/12/4 MBIMR0_12 MBIMR0_4 UMSR0_12 UMSR0_4 STDID10 STDID2
Bits 27/ 19/11/3 MBIMR0_11 MBIMR0_3 UMSR0_11 UMSR0_3 STDID9 STDID1
Bits26/ 18/10/2 MBIMR0_10 MBIMR0_2 UMSR0_10 UMSR0_2 STDID8 STDID0
Bits 25/ 17/9/1 MBIMR0_9 MBIMR0_1 UMSR0_9 UMSR0_1 STDID7 EXTID17
Bits24/ 16/8/0 MBIMR0_8 MBIMR0_0 UMSR0_8 UMSR0_0 STDID6 EXTID16 Module RCAN-ET
UMSR0_1
UMSR0_15 UMSR0_7
MB[0]. CONTROL0H (MCR15 = 1) MB[0]. CONTROL0H (MCR15 = 0) MB[0]. CONTROL0L MB[0]. LAFMH (MCR15 = 1)
IDE STDID5
STDID3
STDID10 STDID2
STDID9 STDID1
STDID8 STDID0
STDID7 RTR
STDID6 IDE
STDID5 EXTID17
STDID4 EXTID16
EXTID15 EXTID7 IDE_LAFM
EXTID14 EXTID6
EXTID13 EXTID5
EXTID12 EXTID4 STDID_ LAFM10
EXTID11 EXTID3 STDID_ LAFM9 STDID_ LAFM1 STDID_ LAFM7
EXTID10 EXTID2 STDID_ LAFM8 STDID_ LAFM0 STDID_ LAFM6 IDE_ LAFM
EXTID9 EXTID1 STDID_ LAFM7 EXTID_ LAFM17 STDID_ LAFM5 EXTID_ LAFM17 EXTID_ LAFM9 EXTID_ LAFM1
EXTID8 EXTID:0 STDID_ LAFM6 EXTID_ LAFM16 STDID_ LAFM4 EXTID_ LAFM16 EXTID_ LAFM8 EXTID_ LAFM0
STDID_ LAFM5
STDID_ LAFM4 STDID_ LAFM10
STDID_ LAFM3 STDID_ LAFM9 STDID_ LAFM1 EXTID_ LAFM13 EXTID_ LAFM5
STDID_ LAFM2 STDID_ LAFM8 STDID_ LAFM0 EXTID_ LAFM12 EXTID_ LAFM4
MB[0]. LAFMH (MCR15 = 0)
STDID_ LAFM3
STDID_ LAFM2 EXTID_ LAFM14 EXTID_ LAFM6
MB[0]. LAFML
EXTID_ LAFM15 EXTID_ LAFM7
EXTID_ LAFM11 EXTID_ LAFM3 MSG_DATA_0
EXTID_ LAFM10 EXTID_ LAFM2
MB[0]. MSG_DATA[0] MB[0]. MSG_DATA[1] MB[0]. MSG_DATA[2] MB[0]. MSG_DATA[3] MB[0]. MSG_DATA[4] MB[0]. MSG_DATA[5] MB[0]. MSG_DATA[6] MB[0]. MSG_DATA[7] MB[0]. CONTROL1H NMC
MSG_DATA_1
MSG_DATA_2
MSG_DATA_3
MSG_DATA_4
MSG_DATA_5
MSG_DATA_6
MSG_DATA_7
MBC2
MBC1
MBC0
Rev. 2.00 Sep. 07, 2007 Page 1226 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation MB[0]. CONTROL1L MB[1 to 15]. CONTROL0H (MCR15 = 1) MB[1 to 15]. CONTROL0H (MCR15 = 0) MB[1 to 15]. CONTROL0L MB[1 to 15]. LAFMH (MCR15 = 1)
Bits 31/ 23/15/7
Bits30/ 22/14/6
Bits 29/ 21/13/5
Bits28/ 20/12/4
Bits 27/ 19/11/3 DLC3
Bits26/ 18/10/2 DLC2
Bits 25/ 17/9/1 DLC1
Bits24/ 16/8/0 DLC0 Module RCAN-ET
IDE STDID5
RTR STDID4
STDID3
STDID10 STDID2
STDID9 STDID1
STDID8 STDID0
STDID7 EXTID17
STDID6 EXTID16
STDID3
STDID10 STDID2
STDID9 STDID1
STDID8 STDID0
STDID7 RTR
STDID6 IDE
STDID5 EXTID17
STDID4 EXTID16
EXTID15 EXTID7 IDE_LAFM
EXTID14 EXTID6
EXTID13 EXTID5
EXTID12 EXTID4 STDID_ LAFM10
EXTID11 EXTID3 STDID_ LAFM9 STDID_ LAFM1 STDID_ LAFM7
EXTID10 EXTID2 STDID_ LAFM8 STDID_ LAFM0 STDID_ LAFM6 IDE_ LAFM
EXTID9 EXTID1 STDID_ LAFM7 EXTID_ LAFM17 STDID_ LAFM5 EXTID_ LAFM17 EXTID_ LAFM9 EXTID_ LAFM1
EXTID8 EXTID:0 STDID_ LAFM6 EXTID_ LAFM16 STDID_ LAFM4 EXTID_ LAFM16 EXTID_ LAFM8 EXTID_ LAFM0
STDID_ LAFM5
STDID_ LAFM4 STDID_ LAFM10
STDID_ LAFM3 STDID_ LAFM9 STDID_ LAFM1 EXTID_ LAFM13 EXTID_ LAFM5
STDID_ LAFM2 STDID_ LAFM8 STDID_ LAFM0 EXTID_ LAFM12 EXTID_ LAFM4
MB[1 to 15]. LAFMH (MCR15 = 0)
STDID_ LAFM3
STDID_ LAFM2 EXTID_ LAFM14 EXTID_ LAFM6
MB[1 to 15]. LAFML
EXTID_ LAFM15 EXTID_ LAFM7
EXTID_ LAFM11 EXTID_ LAFM3 MSG_DATA_0
EXTID_ LAFM10 EXTID_ LAFM2
MB[1 to 15]. MSG_DATA[0] MB[1 to 15]. MSG_DATA[1] MB[1 to 15]. MSG_DATA[2] MB[1 to 15]. MSG_DATA[3] MB[1 to 15]. MSG_DATA[4] MB[1 to 15]. MSG_DATA[5] MB[1 to 15]. MSG_DATA[6] MB[1 to 15]. MSG_DATA[7] MB[1 to 15]. CONTROL1H MB[1 to 15]. CONTROL1L NMC ATX
MSG_DATA_1
MSG_DATA_2
MSG_DATA_3
MSG_DATA_4
MSG_DATA_5
MSG_DATA_6
MSG_DATA_7
DART
MBC2
MBC1
MBC0
DLC3
DLC2
DLC1
DLC0
Rev. 2.00 Sep. 07, 2007 Page 1227 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation IECTR IECMR IEMCR IEAR1 IEAR2 IESA1 IESA2 IETBFL IEMA1 IEMA2 IERCTL IERBFL IELA1 IELA2 IEFLG IETSR IEIET IERSR IEIER IECKSR IETB001 to IETB128 IERB001 to IERB128 DREQER0 DREQER1 DREQER2 DREQER3 DSFR
Bits 31/ 23/15/7 SS
Bits30/ 22/14/6 IOL RN2
Bits 29/ 21/13/5 DEE RN1 IARL4
Bits28/ 20/12/4 RN0
Bits 27/ 19/11/3 RE CTL3 IMD1 IARU
Bits26/ 18/10/2 CMD2 CTL2 IMD0
Bits 25/ 17/9/1 CMD1 CTL1
Bits24/ 16/8/0 CMD0 CTL0 STE Module IEB
ISAL4
ISAU8 TBFL
IMAL4
IMAU8

RBFL ILAL8
RCTL
CMX RXBSY RXBSYE
MRQ TXS TXSE RXS RXSE
SRQ TXF TXFE RXF RXFE
SRE RXEDE RXEDEE CKS3 LCK TXEAL TXEALE RXEOVE RXEOVEE TB001 to TB128 TXETTME TXETTMEE RXERTME RXERTMEE CKS2
ILAU4 RSS TXERO TXEROE RXEDLE RXEDLEE CKS1 GG TXEACK TXEACKE RXEPE RXEPEE CKS0
RB001 to RB128
SCIF3TX SCIF7TX ADC IOKEEP IRQ7F
SCIF3RX SCIF7RX MTU4 IRQ6F
IIC2TX SCIF2TX SCIF6TX MTU3 IRQ5F
IIC2RX SCIF2RX SCIF6RX MTU2 IRQ4F
IIC1TX SCIF1TX SCIF5TX MTU1 IRQ3F RAMKP3
IIC1RX SCIF1RX SCIF5RX MTU0 IRQ2F CKS2 RAMKP2
IIC0TX SCIF0TX SCIF4TX RCAN1 MRESF IRQ1F CKS1 RAMKP1
IIC0RX SCIF0RX SCIF4RX RCAN0 NMIF IRQ0F CKS0 RAMKP0
INTC
SYSTEM
DSCNT RAMKP

Rev. 2.00 Sep. 07, 2007 Page 1228 of 1312 REJ09B0320-0200
Section 30 List of Registers
30.3
Register States in Each Operating Mode
Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*1 Initialized*1 Initialized*1 Initialized*
1
Register Abbreviation CROMEN CROMSY0 CROMCTL0 CROMCTL1 CROMCTL3 CROMCTL4 CROMCTL5 CROMST0 CROMST1 CROMST3 CROMST4 CROMST5 CROMST6 CBUFST0 CBUFST1 CBUFST2 HEAD00 HEAD01 HEAD02 HEAD03 SHEAD00 SHEAD01 SHEAD02 SHEAD03 SHEAD04 SHEAD05 SHEAD06 SHEAD07 HEAD20 HEAD21 HEAD22 HEAD23 SHEAD20 SHEAD21
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module ROM-DEC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1229 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SHEAD22 SHEAD23 SHEAD24 SHEAD25 SHEAD26 SHEAD27 CBUFCTL0 CBUFCTL1 CBUFCTL2 CBUFCTL3 CROMST0M ROMDECRST RSTSTAT SSI INTHOLD INHINT RINGBUFCTL STRMDIN0 STRMDIN1 STRMDIN2 STRMDIN3 STRMDOUT0 STRMDOUT1 SYCBEEN SYCBESTS1 SYCBESTS2 SYCBESW CS0CNT CS0REC CS1CNT CS1REC CS2CNT CS2REC CS3CNT CS3REC CS4CNT Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module ROM-DEC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Bus Monitor
Initialized*1 Initialized*1 Initialized*
1
BSC
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1230 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation CS4REC CS5CNT CS5REC CS6CNT CS6REC SDC0CNT SDC1CNT CSMOD0 CS1WCNT0 CS2WCNT0 CSMOD1 CS1WCNT1 CS2WCNT1 CSMOD2 CS1WCNT2 CS2WCNT2 CSMOD3 CS1WCNT3 CS2WCNT3 CSMOD4 CS1WCNT4 CS2WCNT4 CSMOD5 CS1WCNT5 CS2WCNT5 CSMOD6 CS1WCNT6 CS2WCNT6 SDRFCNT0 SDRFCNT1 SDIR0 SDIR1 SDPWDCNT SDDPWDCNT SD0ADR SD0TR Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module BSC
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1
Rev. 2.00 Sep. 07, 2007 Page 1231 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SD0MOD SD1ADR SD1TR SD1MOD SDSTR SDCKSCNT DMCSADR0 DMCDADR0 DMCBCT0 DMMOD0 DMCSADR1 DMCDADR1 DMCBCT1 DMMOD1 DMCSADR2 DMCDADR2 DMCBCT2 DMMOD2 DMCSADR3 DMCDADR3 DMCBCT3 DMMOD3 DMCSADR4 DMCDADR4 DMCBCT4 DMMOD4 DMCSADR5 DMCDADR5 DMCBCT5 DMMOD5 DMCSADR6 DMCDADR6 DMCBCT6 DMMOD6 DMCSADR7 DMCDADR7 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module BSC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
DMAC
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1232 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCBCT7 DMMOD7 DMRSADR0 DMRDADR0 DMRBCT0 DMRSADR1 DMRDADR1 DMRBCT1 DMRSADR2 DMRDADR2 DMRBCT2 DMRSADR3 DMRDADR3 DMRBCT3 DMRSADR4 DMRDADR4 DMRBCT4 DMRSADR5 DMRDADR5 DMRBCT5 DMRSADR6 DMRDADR6 DMRBCT6 DMRSADR7 DMRDADR7 DMRBCT7 DMCNTA0 DMCNTB0 DMCNTA1 DMCNTB1 DMCNTA2 DMCNTB2 DMCNTA3 DMCNTB3 DMCNTA4 DMCNTB4 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module DMAC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1233 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation DMCNTA5 DMCNTB5 DMCNTA6 DMCNTB6 DMCNTA7 DMCNTB7 DMSCNT DMICNT DMICNTA DMISTS DMEDET DMASTS BAR0 BAMR0 BDR0 BDMR0 BAR1 BAMR1 BDR1 BDMR1 BBR0 BBR1 BRCR CCR1 CCR2 ACSWR SDIR* ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR
2
Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained*
3
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module DMAC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
UBC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Cache
Initialized*1 Initialized*
1
BSC H-UDI INTC
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1234 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation IPR01 IPR02 IPR05 IPR06 IPR07 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 IPR15 IPR16 WTCSR WTCNT WRCSR FRQCR STBCR STBCR2 SYSCR1 SYSCR2 STBCR3 STBCR4 STBCR5 R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized*4 Initialized* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained*5 Retained*5 Retained*5 Retained*
5 4
Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained*5 Retained*5 Retained*5 Retained*
5
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained*5 Retained*5 Retained*5 Retained*
5
Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained*5 Retained*5 Retained*5 Retained*5 Retained*5 Retained*5 Retained*5 Retained*5 Retained Retained
Module INTC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
WDT
CPG SYSTEM
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Retained*5 Retained*5 Retained*5 Retained*
5
RTC
Retained*5 Retained* Retained*
5
Retained*5 Retained* Retained*
5
Retained*5 Retained* Retained*
5
Retained*5 Retained* Retained*
5
5
5
5
5
Retained*5 Retained Retained
Retained*5 Retained Retained
Retained*5 Retained Retained
Retained*5 Retained Retained
Rev. 2.00 Sep. 07, 2007 Page 1235 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 RYRAR RCR3 PADRH PADRL PAPRH PAPRL PBDRH PBDRL PBPRH PBPRL PCDRH PCDRL PCPRH PCPRL PDDRH PDDRL PDPRH PDPRL PEPRL PFDR PFPR PAIORH PAIORL PACR8 PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 Power-on Reset Retained Retained Retained Retained Initialized Initialized Retained Initialized Initialized Initialized Undefined Undefined Initialized Initialized Undefined Undefined Initialized Initialized Undefined Undefined Initialized Initialized Undefined Undefined Undefined Undefined Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Initialized Initialized* Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
6
Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Deep Standby Retained Retained Retained Retained Retained Retained Retained Retained Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module RTC
I/O ports
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
PFC
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1
Rev. 2.00 Sep. 07, 2007 Page 1236 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation PBIORH PBIORL PBCR8 PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PCIORH PCIORL PCCR7 PCCR6 PCCR5 PCCR4 PCCR3 PCCR2 PCCR1 PDIORH PDIORL PDCR5 PDCR4 PDCR3 PDCR2 PDCR1 PECR2 PECR1 PFIOR PFCR2 PFCR1 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Deep Standby Initialized*
1
Module Standby Initialized Initialized Initialized Initialized Initialized Initialized
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module PFC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
MTU2
Initialized*1 Initialized*1 Initialized*
1
Initialized*1
Rev. 2.00 Sep. 07, 2007 Page 1237 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TITCR TITCNT TBTCR TDER TOLBR TBTM_3 TBTM_4 TADCR TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Deep Standby Initialized*
1
Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module MTU2
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1238 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TSYCR TWCR TSTR TSYR TCSYSTR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Deep Standby Initialized*
1
Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module MTU2
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1239 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 TIORV_5 TCNTW_5 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Deep Standby Initialized*
1
Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module MTU2
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
TCNTCMPCLR Initialized T8TCR_0 T8TCR_1 T8TCSR_0 T8TCSR_1 T8TCORA_0 T8TCORA_1 T8TCORB_0 T8TCORB_1 T8TCNT_0 T8TCNT_1 T8TCCR_0 T8TCCR_1 ADDRA ADDRB ADDRC ADDRD ADDRE Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TMR
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
ADC
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1240 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation ADDRF ADDRG ADDRH ADCSR DADR0 DADR1 DACR SCSMR_0 SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 SCSPTR_1 SCLSR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module ADC
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
DAC
Initialized*1 Initialized*1 Initialized*
1
SCIF
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1241 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SCLSR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 SCFSR_3 SCFRDR_3 SCFCR_3 SCFDR_3 SCSPTR_3 SCLSR_3 SCSMR_4 SCBRR_4 SCSCR_4 SCFTDR_4 SCFSR_4 SCFRDR_4 SCFCR_4 SCFDR_4 SCSPTR_4 SCLSR_4 SCSMR_5 SCBRR_5 SCSCR_5 SCFTDR_5 SCFSR_5 SCFRDR_5 SCFCR_5 SCFDR_5 SCSPTR_5 SCLSR_5 SCSMR_6 SCBRR_6 SCSCR_6 SCFTDR_6 SCFSR_6 Power-on Reset Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module SCIF
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1242 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation SCFRDR_6 SCFCR_6 SCFDR_6 SCSPTR_6 SCLSR_6 SCSMR_7 SCBRR_7 SCSCR_7 SCFTDR_7 SCFSR_7 SCFRDR_7 SCFCR_7 SCFDR_7 SCSPTR_7 SCLSR_7 SSICR_0 SSISR_0 SSITDR_0 SSIRDR_0 SSICR_1 SSISR_1 SSITDR_1 SSIRDR_1 ICCR1_0 ICCR2_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICDRT_0 ICDRR_0 NF2CYC_0 ICCR1_1 ICCR2_1 ICMR_1 Power-on Reset Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained*7 Retained Retained Retained Retained Retained Retained Retained Retained Retained*7 Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained*7 Retained Retained Retained Retained Retained Retained Retained Retained Retained*7
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module SCIF
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
SSI
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
IIC3
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1
Rev. 2.00 Sep. 07, 2007 Page 1243 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 NF2CYC_1 ICCR1_2 ICCR2_2 ICMR_2 ICIER_2 ICSR_2 SAR_2 ICDRT_2 ICDRR_2 NF2CYC_2 MCR_0 GSR_0 BCR1_0 BCR0_0 IRR_0 IMR_0 TEC_0/REC_0 TXPR1_0 TXPR0_0 TXCR0_0 TXACK0_0 ABACK0_0 RXPR0_0 RFPR0_0 MBIMR0_0 UMSR0_0 MB[0 to 15]. CONTROL0H MB[0 to 15]. CONTROL0L Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained* Retained Retained Retained Retained Retained Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
7
Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained* Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
7
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module IIC3
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
RCAN-ET
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*1
Rev. 2.00 Sep. 07, 2007 Page 1244 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation MB[0 to 15]. LAFMH MB[0 to 15]. LAFML MB[0 to 15]. MSG_DATA[0] MB[0 to 15]. MSG_DATA[1] MB[0 to 15]. MSG_DATA[2] MB[0 to 15]. MSG_DATA[3] MB[0 to 15]. MSG_DATA[4] MB[0 to 15]. MSG_DATA[5] MB[0 to 15]. MSG_DATA[6] MB[0 to 15]. MSG_DATA[7] MB[0 to 15]. CONTROL1H MB[0 to 15]. CONTROL1L MCR_1 GSR_1 BCR1_1 BCR0_1 IRR_1 IMR_1 TEC_1/REC_1 TXPR1_1 TXPR0_1 TXCR0_1 TXACK0_1 ABACK0_1 RXPR0_1 RFPR0_1 MBIMR0_1 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module RCAN-ET
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1
Rev. 2.00 Sep. 07, 2007 Page 1245 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation UMSR0_1 MB[0 to 15]. CONTROL0H MB[0 to 15]. CONTROL0L MB[0 to 15]. LAFMH MB[0 to 15]. LAFML MB[0 to 15]. MSG_DATA[0] MB[0 to 15]. MSG_DATA[1] MB[0 to 15]. MSG_DATA[2] MB[0 to 15]. MSG_DATA[3] MB[0 to 15]. MSG_DATA[4] MB[0 to 15]. MSG_DATA[5] MB[0 to 15]. MSG_DATA[6] MB[0 to 15]. MSG_DATA[7] MB[0 to 15]. CONTROL1H MB[0 to 15]. CONTROL1L IECTR IECMR IEMCR IEAR1 IEAR2 IESA1 IESA2 IETBFL IEMA1 IEMA2 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module RCAN-ET
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
IEB
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Rev. 2.00 Sep. 07, 2007 Page 1246 of 1312 REJ09B0320-0200
Section 30 List of Registers
Register Abbreviation IERCTL IERBFL IELA1 IELA2 IEFLG IETSR IEIET IERSR IEIER IECKSR IETB001 to IETB128 IERB001 to IERB128 DREQER0 DREQER1 DREQER2 DREQER3 DSFR DSCNT RAMKP Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Deep Standby Initialized*
1
Module Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module IEB
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*
1
Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*
1
INTC
Initialized*1 Initialized*1 Retained Initialized*1 Initialized*1
SYSTEM
Notes: 1. Not initialized in deep standby mode. But initialized after deep standby mode is released because a power-on reset exception handling is executed. 2. Initialized by UDTRST assertion or in the Test-Logic-Reset state of the TAP controller. 3. Bits BN[3:0] are initialized. 4. Retains the previous value after an internal power-on reset by means of the WDT. 5. Counting up continues. 6. Bits RTCEN and START are retained. 7. Bits BC[3:0] are initialized.
Rev. 2.00 Sep. 07, 2007 Page 1247 of 1312 REJ09B0320-0200
Section 30 List of Registers
Rev. 2.00 Sep. 07, 2007 Page 1248 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Section 31 Electrical Characteristics
31.1 Absolute Maximum Ratings
Table 31.1 lists the absolute maximum ratings. Table 31.1 Absolute Maximum Ratings
Item Power supply voltage (I/O) Power supply voltage (Internal) Power supply voltage (PLL) Analog power supply voltage Analog reference voltage Input voltage Analog input pin PC22 to PC25, PD15, PD16 Other pins Operating temperature Symbol Value PVCC VCCR PLLVCC AVCC AVref VAN Vin Vin Topr -0.3 to 4.6 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to 5.5 -0.3 to PVCC +0.3 -20 to +70 (Regular specifications) -40 to +85 (Wide-range specifications) Storage temperature Caution: Tstg -55 to +125 C V V V V V C -0.3 to 4.6 Unit V
Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Rev. 2.00 Sep. 07, 2007 Page 1249 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.2
DC Characteristics
Tables 31.2 and 31.3 list DC characteristics. Table 31.2 DC Characteristics (1) [Common Items] [Regular Specifications] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Supply current* Normal operation Symbol ICC Min. Typ. 120 100 80 60 50 45 5 1.5 80 300 500 750 1000 50 70 80 90 100 Max. 180 160 140 140 130 125 30 20 100 750 1500 2250 3000 75 300 500 750 1000 Unit mA mA mA mA mA mA mA mA A A A A A A A A A A Test Conditions I = 120 MHz I = 100 MHz I = 80 MHz I = 120 MHz I = 100 MHz I = 80 MHz Ta > 50C Ta 50C Ta > 50C RAM: 0 Kbyte retained Ta > 50C RAM: 8 Kbytes retained Ta > 50C RAM: 16 Kbytes retained Ta > 50C RAM: 24 Kbytes retained Ta > 50C RAM: 32 Kbytes retained Ta 50C RAM: 0 Kbyte retained Ta 50C RAM: 8 Kbytes retained Ta 50C RAM: 16 Kbytes retained Ta 50C RAM: 24 Kbytes retained Ta 50C RAM: 32 Kbytes retained

Sleep mode
Isleep
Software standby mode Deep standby mode
Istby Idstby
Rev. 2.00 Sep. 07, 2007 Page 1250 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics Item Input leakage current Symbol |Iin | All input pins (except PC22 to PC25, PD15, PD16, PE0 to PE7, EXTAL, AUDIO_X1, and RTC_X1) PC22 to PC25, PD15, PD16 Three-state leakage current Input pull-up MOS current Input capacitance All input/output pins, |ITSI | output pins (off state) UDTRST, UDTMS, UDTDI, UDTCK,
ASEBRK/ASEBRKAK
Min.
Typ.
Max. 1.0
Unit A
Test Conditions Vin = 0.5 to PVCC - 0.5 V

20 1.0
A A Vin = 0.5 to PVCC - 0.5 V
-lp
10
--
150
A
Vin = 0 V
All pins
Cin AICC

1 1 2
20 2 2 3
pF mA A mA
Analog power During A/D or D/A supply current conversion Waiting for A/D or D/A conversion Analog reference voltage current
Alref
Caution: Note: *
When the A/D converter or D/A converter is not in use, the AVCC and AVSS pins should not be open. Supply current values are values when all of the output pins and pins with the pull-up function (UDTRST, UDTMS, UDTDI, UDTCK, ASEBRK/ASEBRKAK) are unloaded and represent the total current supplied to the PVCC, VCCR, and PLLVCC systems. Reference values are given under "Typ."
Rev. 2.00 Sep. 07, 2007 Page 1251 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Table 31.2 DC Characteristics (2) [Common Items] [Wide-Range Specifications] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Supply current* Normal operation Symbol ICC Min. Typ. 100 80 50 45 5 1.5 80 300 500 750 1000 50 70 80 90 100 Max. 160 140 130 125 40 20 100 1000 2000 3000 4000 75 300 500 750 1000 Unit mA mA mA mA mA mA A A A A A A A A A A Test Conditions I = 100 MHz I = 80 MHz I = 100 MHz I = 80 MHz Ta > 50C Ta 50C Ta > 50C RAM: 0 Kbyte retained Ta > 50C RAM: 8 Kbytes retained Ta > 50C RAM: 16 Kbytes retained Ta > 50C RAM: 24 Kbytes retained Ta > 50C RAM: 32 Kbytes retained Ta 50C RAM: 0 Kbyte retained Ta 50C RAM: 8 Kbytes retained Ta 50C RAM: 16 Kbytes retained Ta 50C RAM: 24 Kbytes retained Ta 50C RAM: 32 Kbytes retained

Sleep mode
Isleep
Software standby mode Deep standby mode
Istby
Idstby
Rev. 2.00 Sep. 07, 2007 Page 1252 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics Item Input leakage current Symbol |Iin | All input pins (except PC22 to PC25, PD15, PD16, PE0 to PE7, EXTAL, AUDIO_X1, and RTC_X1) PC22 to PC25, PD15, PD16 Three-state leakage current Input pull-up MOS current Input capacitance All input/output pins, |ITSI | output pins (off state) UDTRST, UDTMS, -lp UDTDI, UDTCK, and
ASEBRK/ASEBRKAK
Min.
Typ.
Max. 1.0
Unit A
Test Conditions Vin = 0.5 to PVCC - 0.5 V

1 1 2
20 1.0
A A Vin = 0.5 to PVCC - 0.5 V
10
150
A
Vin = 0 V
All pins
Cin AICC

20 2 2 3
pF mA A mA
Analog power During A/D or D/A supply current conversion Waiting for A/D or D/A conversion Analog reference voltage current
Alref
Caution: Note: *
When the A/D converter or D/A converter is not in use, the AVCC and AVSS pins should not be open. Supply current values are values when all of the output pins and pins with the pull-up function (UDTRST, UDTMS, UDTDI, UDTCK, ASEBRK/ASEBRKAK) are unloaded and represent the total current supplied to the PVCC, VCCR, and PLLVCC systems. Reference values are given under "Typ."
Rev. 2.00 Sep. 07, 2007 Page 1253 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Table 31.2 DC Characteristics (3) [Except for I2C-Related Pins*1] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Input high voltage
RES, MRES, NMI, MD1, MD0, MD_CLK1, MD_CLK0, ASEMD, UDTRST, ASEBRK/ASEBRKAK, EXTAL, CKIO, AUDIO_X1, RTC_X1
Symbol VIH
Min.
Typ.
Max.
Unit
Test Conditions
PVCC - 0.5
PVCC + 0.3 V
PF7 to PF0 Input pins other than above (excluding Schmitt pins) Input low voltage
RES, MRES, NMI, MD1, MD0, MD_CLK1, MD_CLK0, ASEMD, UDTRST, ASEBRK/ASEBRKAK, EXTAL, CKIO, AUDIO_X1, RTC_X1
2.2 2.2

AVCC + 0.3 PVCC + 0.3
VIL
-0.3
0.5
V
Input pins other than above (excluding Schmitt pins)
-0.3
0.8
Rev. 2.00 Sep. 07, 2007 Page 1254 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Item
Symbol
+
Min. PVCC - 0.5 -- 0.2
Typ.
Max.
Unit V V V
Test Conditions
Schmitt trigger TIOC0A to TIOC0D, VT (VIH) input TIOC1A, TIOC1B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TIC5U to TIC5W, TCLKA to TCLKD, SCK7 to SCK0, RxD7 to RxD0, IRQ7 to IRQ0* , PINT7 to PINT0 Output high voltage Output low voltage RAM standby voltage Power-supply start voltage Power-supply rising gradient SVCC VCCSTART VRAM All output pins VOL All output pins VOH
2

0.5
VT (VIL) V T - V T-
+
-
characteristics TIOC2A, TIOC2B,
PVCC - 0.5

0
--
V
IOH = -200 A
3.0
0.4
V
IOL = 1.6 mA
0.8
V

V
20
ms/V
Notes: 1. Pins (open-drain pins): PC22/IRQ0/SCL0/DREQ2, PC23/IRQ1/SDA0, PC24/IRQ2/SCL1, PC25/IRQ3/SDA1, PD15/SDA2, and PD16/SCL2 2. Except (PC22/)IRQ0, (PC23/)IRQ1, (PC24/)IRQ2, and (PC25/)IRQ3
Rev. 2.00 Sep. 07, 2007 Page 1255 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Table 31.2 DC Characteristics (4) [I2C-Related Pins*] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Input high voltage PC22/DREQ2, PC23, PC24, Input low voltage PC25, PD15, PD16 Schmitt trigger input IRQ0/SCL0, characteristics IRQ1/SDA0, IRQ2/SCL1, IRQ3/SDA1, SDA2, ASCL2 Output low voltage SCL0 to SCL2, SDA0 to SDA2 VOL VT (VIH) VT- (VIL) V T - V T-
+ +
Symbol VIH
Min. 2.2
Typ.
Max.
Unit
Test Conditions

PVCC + 0.3 V
VIL
-0.3 PVCC x 0.7 -0.3
0.8 5.5
V V
PVCC x 0.3 V -- V
PVCC x 0.05
0.4
V
IOL = 3.0 mA
Note:
*
Pins (open-drain pins): PC22/IRQ0/SCL0/DREQ2, PC23/IRQ1/SDA0, PC24/IRQ2/SCL1, PC25/IRQ3/SDA1, PD15/SDA2, and PD16/SCL2
Table 31.3 Permissible Output Currents (1) [Common Items] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Permissible output low current (per pin) SCL0 to SCL2, SDA0 to SDA2 Other than above Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: IOL -IOH -IOH Symbol IOL Min. Typ. Max. 10 2 150 2 50 mA mA mA Unit mA
To protect the LSI's reliability, do not exceed the output current values in the table above.
Rev. 2.00 Sep. 07, 2007 Page 1256 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Table 31.3 Permissible Output Currents (2) [Wide-Range Specifications] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V, I 80 MHz
Item Permissible output low current (per pin) SCL0 to SCL2, SDA0 to SDA2 Other than above Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: IOL -IOH -IOH Symbol IOL Min. Typ. Max. 10 2 150 2 50 mA mA mA Unit mA
To protect the LSI's reliability, do not exceed the output current values in the table above.
Table 31.3 Permissible Output Currents (3) [Wide-Range Specifications] Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V, 80 MHz < I 100 MHz
Item Permissible output low current (per pin) SCL0 to SCL2, SDA0 to SDA2 Other than above Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: IOL -IOH -IOH Symbol IOL Min. Typ. Max. 10 2 50 2 50 mA mA mA Unit mA
To protect the LSI's reliability, do not exceed the output current values in the table above.
Rev. 2.00 Sep. 07, 2007 Page 1257 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3
AC Characteristics
Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 31.4 Maximum Operating Frequency Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Operating frequency CPU (I) Symbol f Min. 20 Typ. Max. 120 100 Internal bus, external bus (B) Peripheral module (P) 20 5 60 40 Unit MHz Remarks Regular specifications Wide-range specifications
31.3.1
Clock Timing
Table 31.5 Clock Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item EXTAL, XTAL crystal oscillator frequency (clock mode 0) EXTAL, XTAL crystal oscillator frequency (clock mode 2) AUDIO_X1, AUDIO_X2 crystal oscillator frequency EXTAL clock input frequency (clock mode 0) EXTAL clock input frequency (clock mode 2) Symbol Min. fEX fEX 10 10 10 10 10 Max. 15 20 25 15 30 Unit MHz MHz MHz MHz MHz Figure 31.1 Figure
Rev. 2.00 Sep. 07, 2007 Page 1258 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Item EXTAL clock input cycle time (clock mode 0) EXTAL clock input cycle time (clock mode 2) AUDIO_X1, AUDIO_CLK clock input frequency AUDIO_X1, AUDIO_CLK clock input cycle time EXTAL, AUDIO_X1, AUDIO_CLK clock input pulse low width EXTAL, AUDIO_X1, AUDIO_CLK clock input pulse high width EXTAL, AUDIO_X1, AUDIO_CLK clock input rise time EXTAL, AUDIO_X1, AUDIO_CLK clock input fall time CKIO clock input frequency CKIO clock input cycle time CKIO clock input pulse low width CKIO clock input pulse high width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output pulse low width CKIO clock output pulse high width CKIO clock output rise time CKIO clock output fall time Power-on oscillation settling time Oscillation settling time on return from standby 1 Oscillation settling time on return from standby 2 RTC clock oscillation settling time
Symbol Min. fEXcyc fEXcyc fEX tEXcyc tEXL tEXH tEXr tEXf fCK tCKIcyc tCKIL tCKIH tCKIr tCKIf fOP tcyc tCKOL tCKOH tCKOr tCKOf tOSC1 tOSC2 tOSC3 tROSC 66.67 33.33 1 25 0.4 0.4 20 16.67 0.4 0.4 20 16.67 0.4 0.4 10 10 10 3
Max. 100 100 40 1000 0.6 0.6 4 4 60 50 0.6 0.6 3 3 60 50 0.6 0.6 3 3
Unit ns ns MHz ns tcyc tcyc ns ns MHz ns tcyc tcyc ns ns MHz ns tcyc tcyc ns ns ms ms ms s
Figure Figure 31.1
Figure 31.2
Figure 31.3
Figure 31.4 Figure 31.5 Figure 31.6 Figure 31.7
Rev. 2.00 Sep. 07, 2007 Page 1259 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
tEXcyc EXTAL, AUDIO_X1, AUDIO_CLK* 1/2 PVcc (input) tEXH VIH VIH VIL tEXf VIL tEXL VIH 1/2 PVcc tEXr
Note: * When the clock is input on the EXTAL, AUDIO_X1, or AUDIO_CLK pin.
Figure 31.1 EXTAL, AUDIO_X1, and AUDIO_CLK Clock Input Timing
tCKIcyc CKIO (input) 1/2 PVcc tCKIH tCKIL VIH 1/2 PVcc tCKIr
VIH
VIH VIL tCKIf VIL
Figure 31.2 CKIO Clock Input Timing
tcyc tCKOH CKIO (output) VOH VOH VOL tCKOf tCKOL VOH VOL
1/2 PVcc
1/2 PVcc tCKOr
Figure 31.3 CKIO Clock Output Timing
Oscillation settling time CKIO, Internal clock
Vcc
Vcc Min.
tRESW/tMRESW
tOSC1 RES MRES
Note: Oscillation settling time when the internal oscillator is used.
Figure 31.4 Power-On Oscillation Settling Time
Rev. 2.00 Sep. 07, 2007 Page 1260 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Standby period CKIO, Internal clock
Oscillation settling time
tOSC2 RES MRES
Note: Oscillation settling time when the internal oscillator is used.
tRESW/tMRESW
Figure 31.5 Oscillation Settling Time on Return from Standby (Return by Reset)
Oscillation settling time Standby period CKIO, Internal clock
tOSC3
NMI, IRQ
Note: Oscillation settling time when the internal oscillator is used.
Figure 31.6 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ)
Oscillation settling time RTC clock (internal)
PVCC
PVCCmin
tROSC
Figure 31.7 RTC Clock Oscillation Settling Time
Rev. 2.00 Sep. 07, 2007 Page 1261 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.2
Control Signal Timing
Table 31.6 Control Signal Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
B = 60 MHz Item RES pulse width RES setup time*
1
Symbol tRESW tRESS tMRESW
1
Min. 20*
2
Max.
Unit tcyc ns tcyc ns tcyc ns ns tcyc ns ns ns
Figure Figures 31.4, 31.5, and 31.8
200 20*
3
MRES pulse width MRES setup time* NMI pulse width NMI setup time*1 NMI hold time IRQ7 to IRQ0 pulse width IRQ7 to IRQ0 setup time* IRQ7 to IRQ0 hold time PINT7 to PINT0 setup time*
1 1
tMRESS tNMIW tNMIS tNMIH tIRQW tIRQS tIRQH tPINTS
200 20*
4
150 10 20*
4
Figures 31.6 and 31.9
150 10 150
Notes: 1. The RES, MRES, NMI, IRQ7 to IRQ0 and PINT7 to PINT0 signals are asynchronous signals. When the setup time is satisfied, change of signal level is detected at the rising edge of the clock. If not, the detection can be delayed until the rising edge of the next clock. 2. In software standby mode, deep standby mode or when the clock multiplication ratio is changed, tRESW = tOSC2 (min). 3. In software standby mode or deep standby mode, tMRESW = tOSC2 (min). 4. In software standby mode or deep standby mode, tNMIW/tIRQW = tOSC3 (min).
Rev. 2.00 Sep. 07, 2007 Page 1262 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
CKIO
tRESS/tMRESS tRESW/tMRESW
RES MRES
tRESS/tMRESS
Figure 31.8 Reset Input Timing
CKIO
tNMIS NMI tNMIW
tNMIH
IRQ7 to IRQ0 tIRQW tIRQS IRQ7 to IRQ0 edge input tIRQH
tIRQS
IRQ level input
tPINTS PINT7 to PINT0
Figure 31.9 Interrupt Signal Input Timing
Rev. 2.00 Sep. 07, 2007 Page 1263 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.3
Bus Timing
Table 31.7 Bus Timing*1 Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
B = 60 MHz*2 Item Address delay time 1 (external space) Address delay time 2 (SDRAM space) Byte control delay time Chip select delay time 1 (external space) Chip select delay time 2 (SDRAM space) Read strobe delay time Read data setup time 1 (external space) Read data setup time 2 (SDRAM space) Read data hold time 1 (external space) Read data hold time 2 (SDRAM space) Write enable delay time 1 (external space) Write enable delay time 2 (SDRAM space) Write data delay time 1 (external space) Write data delay time 2 (SDRAM space) Write data hold time 1 (external space) Write data hold time 2 (SDRAM space) Symbol tAD1 tAD2 tBCD tCSD1 tCSD2 tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED1 tWED2 tWDD1 tWDD2 tWDH1 tWDH2 Min. 1 1 13 8 0 2 1 1 1 Max. 13 13 13 13 13 13 13 13 13 13 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure Figures 31.10 to 31.14 Figures 31.15 to 31.21 Figures 31.10 to 31.14 Figures 31.10 to 31.14 Figures 31.15 to 31.21 Figures 31.10 to 31.14 Figures 31.10 to 31.14 Figures 31.15 to 31.21 Figures 31.10 to 31.14 Figures 31.15 to 31.21 Figures 31.10 to 31.14 Figures 31.15 to 31.21 Figures 31.10 to 31.14 Figures 31.15 to 31.21 Figures 31.10 to 31.14 Figures 31.15 to 31.21
Rev. 2.00 Sep. 07, 2007 Page 1264 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
B = 60 MHz*2 Item External wait setup time External wait hold time SDRAS delay time SDCAS delay time DQM delay time CKE delay time Symbol tWTS tWTH tRASD tCASD tDQMD tCKED Min. 8 5 1 1 1 1 Max. 13 13 13 13 Unit ns ns ns ns ns ns Figure Figure 31.14 Figure 31.14 Figures 31.15 to 31.21 Figures 31.15 to 31.21 Figures 31.15 to 31.21 Figure 31.21
Notes: 1. When writing to the external address space or making SDRAM settings in power-on reset exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in ACSWR to B'0011 beforehand. 2. The maximum value (fmax) of B (external bus clock) depends on the number of wait cycles and the system configuration of your board.
Tw1 CKIO tAD1 A27 to A0 tBCD BC3 to BC0
Tw2
Tw2
Tend (Trd)
Tn1
Ts
tAD1
tBCD
tCSD1 CSn tRSD RD Read D31 to D0 tWED1 WR3 to WR0 Write D31 to D0 tWDD1 tWDH1 tWED1 tRDS1 tRDH1 tRSD
tCSD1
Figure 31.10 Basic Bus Timing for External Address Space (Normal Access, Cycle Wait Control, CS Extended Cycle)
Rev. 2.00 Sep. 07, 2007 Page 1265 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Tw1
Tw2
Tend (Trd)
Tpw1
Tpw2 Tend (Trd)
Tpw1
Tpw2
Tend (Trd)
Tpw1
Tpw2
Tend (Trd)
Tn1
Ts
CKIO
tAD1
A27 to A0
tAD1
tAD1
tAD1
tAD1
tBCD
BC3 to BC0
tBCD
tBCD
tBCD
tBCD
tCSD1
CSn
tCSD1
tRSD
RD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRSD
tRDS1
D31 to D0
tRDH1
tRDS1
tRDH1
tRDS1
tRDH1
tRDS1
tRDH1
Figure 31.11 Basic Bus Timing for External Address Space (Page Read Access, Normal Access Compatible Mode)
Tw1 Tw2 Tend (Trd) Tpw1 Tend (Trd) Tpw1 Tend (Trd) Tpw1 Tend (Trd) Tn1
CKIO
tAD1
A27 to A0
tAD1
tAD1
tAD1
tAD1
tAD1
tRDH1 tBCD
BC3 to BC0
tBCD
tBCD
tRDH1 tBCD
tRDH1 tBCD
tRDH1 tBCD
tCSD1
CSn
tCSD1
tRSD
RD
tRSD
tRDS1
D31 to D0
tRDS1
tRDS1
tRDS1
Figure 31.12 Basic Bus Timing for External Address Space (Page Read Access, External Read Data Sequential Assert Mode)
Rev. 2.00 Sep. 07, 2007 Page 1266 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
Tw1
Tw2
Tend
Tdw1
Tpw1
Tend
Tdw1
Tpw1
Tend
Tdw1
Tpw1
Tend Tpw1 (Tn1)
Ts
CKIO
tAD1
A27 to A0
tAD1
tAD1
tAD1
tAD1
tBCD
BC3 to BC0
tBCD
tBCD
tBCD
tBCD
tCSD1
CSn
tCSD1
tWED1
WR3 to WR0
tWED1
tWED1 tWED1
tWED1 tWED1
tWED1
tWED1
tWDD1
D31 to D0
tWDH1
tWDH1
tWDH1
tWDH1
tWDD1
tWDD1
tWDD1
Figure 31.13 Basic Bus Timing for External Address Space (Page Write Access)
Tw1 Tw2 Tw3 (Tend) Tend Tpw1 Tpw2 Tpw3 (Tend) Tend
CKIO
tAD1
A27 to A0
tAD1
tAD1
tRDH1 tBCD
BC3 to BC0
tBCD
tBCD
tWTS
WAIT
tWTH
tWTS
tWTH
tCSD1
CSn
tCSD1
tRSD
RD
tRSD
tRDS1
D31 to D0
tRDS1
tRDH1
Figure 31.14 External Wait Timing for External Address Space (Page Read Access for 16-Bit Channel Width, External Read Data Sequential Assert Mode)
Rev. 2.00 Sep. 07, 2007 Page 1267 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
T1 CKIO
tAD2
T2
T3
(RD command)
T4
T5
T6
(PRA command)
(ACT command)
tAD2
tAD2
tAD2
tAD2
A16 to A2
Row Address
tAD2 tAD2
Column Address
tAD2 tAD2 tAD2
A12*
tCSD2 tCSD2 tCSD2 tCSD2
PRA command
tCSD2 tCSD2 tCSD2
SDCSn
tRASD tRASD tRASD tRASD tRASD
SDRAS SDCAS SDWE SDCKE
tDQMD
tCASD
tCASD
tWED2
tWED2
(High)
tDQMD
DQMn
tRDS2 tRDH2
D31 to D0
Note: * Address pin connected to A10 in SDRAM.
Figure 31.15 Single Read Bus Timing for SDRAM Space (DLC = 2 (Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1268 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
T1 CKIO
T2
T3
(WR command)
T4
T5
T6
(PRA command)
(ACT command)
tAD2
A16 to A2
Row Address
tAD2
Column Address
tAD2
tAD2
tAD2
tAD2
Row Address
tAD2
A12*
tAD2
tAD2
tAD2
tAD2
tAD2
PRA command
tCSD2
SDCSn
tCSD2
tCSD2
tCSD2
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
SDRAS
tRASD
tRASD
tRASD
tRASD
tRASD
tCASD
SDCAS
tCASD
tWED2
SDWE
tWED2
tWED2
tWED2
SDCKE
(High)
tDQMD
tDQMD
DQMn
tWDD2
D31 to D0 Note: * Address pin connected to A10 in SDRAM.
tWDH2
Figure 31.16 Single Write Bus Timing for SDRAM Space (DLC = 2 (Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1269 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
T1 (ACT) CKIO
T2
T3 (RD)
T4 (RD)
T5 (RD)
T6 (RD)
T7 (PRA)
tAD2
A16 to A2
Row Address
tAD2
C0 (Column Address 0)
tAD2
C1
tAD2
C2
tAD2
C3
tAD2
tAD2
tAD2
tAD2
A12*
tAD2
tAD2
tAD2
tAD2
PRA command
tCSD2
SDCSn
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
SDRAS
tRASD
tRASD
tRASD
tRASD
tCASD
SDCAS
tCASD
tCASD
tWED2
SDWE
tWED2
SDCKE
(High)
tDQMD
DQMn
tDQMD
tRDS2 tRDH2
D31 to D0 Note: * Address pin connected to A10 in SDRAM.
tRDS2 tRDH2
Figure 31.17 Multiple Read Bus Timing for SDRAM Space (Four Data Access, DLC = 2 (Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1270 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
T1 (ACT)
T2
T3 (WR)
T4 (WR)
T5 (WR)
T6 (WR)
T7 (PRA)
CKIO
tAD2
A16 to A2
Row Address
tAD2
C0 (Column Address 0)
tAD2
C1
tAD2
C2
tAD2
C3
tAD2
tAD2
tAD2
tAD2
A12*
tAD2
tAD2
PRA command
tAD2
tAD2
tCSD2
SDCSn
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
SDRAS
tRASD
tRASD
tRASD
tRASD
tCASD
SDCAS
tCASD
tCASD
tWED2
SDWE
tWED2
SDCKE
(High)
tDQMD
DQMn
tDQMD
tWDD2
D31 to D0
tWDH2
tWDH2
tWDD2
tWDH2
tWDD2
Note: * Address pin connected to A10 in SDRAM.
tWDD2
tWDD2
Figure 31.18 Multiple Write Bus Timing for SDRAM Space (Four Data Access, DLC = 2 (Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1271 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
T1 (ACT)
T2
T3 (RD)
T4 (RD)
T5 (RD)
T6 T7 (RD) (PRA)
T8
T9 (ACT)
T10
T11 (RD)
T12 (RD)
T13 (RD)
T14 T15 (RD) (PRA)
CKIO
tAD2
A16 to A2
tAD2
C0 (Column Address 0)
tAD2
C1
tAD2
C2
tAD2
C3
tAD2
tAD2
R1
tAD2
C4 C5
tAD2
C6
tAD2
C7
tAD2
tAD2
Row Address
tAD2
A12*
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
tAD2
PRA command
PRA command
tCSD2 tCSD2 tCSD2
SDCSn
tCSD2 tCSD2 tCSD2 tCSD2
tCSD2
tRASD tRASD
SDRAS
tRASD tRASD tRASD tRASD
tRASD tRASD
tCASD
SDCAS
tCASD
tCASD
tCASD
tWED2 tWED2
SDWE SDCKE (High)
tWED2 tWED2
tDQMD
DQMn
tRDS2 tRDH2
D31 to D0
tRDS2 tRDH2
tRDS2 tRDH2
tRDS2 tRDH2
Note: * Address pin connected to A10 in SDRAM.
Figure 31.19 Multiple Read Row Span Bus Timing for SDRAM Space (Eight Data Access, DLC = 2 (Two Cycles), DRCD = 1 (Two Cycles), DPCG = 1 (Two Cycles))
Rev. 2.00 Sep. 07, 2007 Page 1272 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
T1 (MRS command)
CKIO
tAD2
A16 to A2
tAD2
tAD2
A12*
tAD2
tCSD2
SDCSn
tCSD2
tRASD
SDRAS
tRASD
tCASD
SDCAS
tCASD
tWED2
SDWE
tWED2
SDCKE DQMn
(High)
D31 to D0
(Hi-Z)
Note: * Address pin connected to A10 in SDRAM.
Figure 31.20 Bus Timing for SDRAM Space Mode Register Setting
Rev. 2.00 Sep. 07, 2007 Page 1273 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
(RFA) CKIO
(RFS)
(RFX)
(RFA)
tAD2
A16 to A2
tAD2
tAD2
A12*
tAD2
tCSD2
SDCSn
tCSD2
tCSD2
tCSD2
tCSD2
tCSD2
tCSD2
tRASD
tRASD
tRASD
tRASD
tRASD
tRASD
tRASD
SDRAS
tCASD
tCASD
tCASD
tCASD
tCASD
tCASD
tCASD
SDCAS
SDWE
(High)
tCKED tDQMD
tCKED tDQMD
SDCKE DQMn
(Hi-Z) D31 to D0
Note: * Address pin connected to A10 in SDRAM.
Figure 31.21 Bus Timing for SDRAM Space Self Refresh
Rev. 2.00 Sep. 07, 2007 Page 1274 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.4
DMAC Module Timing
Table 31.8 DMAC Module Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item DREQ setup time DREQ hold time DACK, DACT, DTEND delay time Symbol tDRQS tDRQH tDACD Min. 15 15 Max. 15 Figure 31.23 Unit ns Figure Figure 31.22
CKIO tDRQS tDRQH DREQn
Note: n = 0 to 3
Figure 31.22 DREQ Input Timing
CKIO t DACKn DACTn DTENDn Note: n = 0 to 3
DACD
t
DACD
Figure 31.23 DACK, DACT, DTEND Output Timing
Rev. 2.00 Sep. 07, 2007 Page 1275 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.5
UBC Trigger Timing
Table 31.9 UBC Trigger Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item UBCTRG delay time Symbol tUBCTGD Min. Max. 14 Unit ns Figure Figure 31.24
CKIO tUBCTGD UBCTRG
Figure 31.24 UBC Trigger Timing
Rev. 2.00 Sep. 07, 2007 Page 1276 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.6
MTU2 Module Timing
Table 31.10 MTU2 Module Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Output compare output delay time Input capture input setup time Timer input setup time Symbol Min. tTOCD tTICS tTCKS (n - 1) x tcyc + 20 1.5 2.5 2.5 Max. 100 Unit ns ns ns tpcyc tpcyc tpcyc Figure 31.26 Figure Figure 31.25
(n - 1) x tcyc/2 + 20
Timer clock pulse width (single edge) tTCKWH/L Timer clock pulse width (both edges) tTCKWH/L Timer clock pulse width (phase counting mode) Note: tTCKWH/L
Above is the case in which the clock ratio B:P = n:1 (n = 1, 2, 3, 4, 6, 8, or 12) tpcyc indicates peripheral clock (P) cycle.
CKIO
tTOCD
Output compare output
tTICS
Input capture input
Figure 31.25 MTU2 Input/Output Timing
CKIO tTCKS tTCKS
TCLKA to TCLKD tTCKWL tTCKWH
Figure 31.26 MTU2 Clock Input Timing
Rev. 2.00 Sep. 07, 2007 Page 1277 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.7
8-Bit Timer Timing
Table 31.11 8-Bit Timer Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Note: Symbol Min. tTMOD tTMRS tTMCS tTMCWH tTMCWL (n - 1) x tcyc + 25 (n - 1) x tcyc + 25 1.5 2.5 Max. 40 Unit ns ns ns tpcyc tpcyc Figure Figure 31.27 Figure 31.28 Figure 31.29
Above is the case in which the clock ratio B:P = n:1 (n = 1, 2, 3, 4, 6, 8, or 12) tpcyc indicates peripheral clock (P) cycle.
CKIO tTMOD
TMO0, TMO1
Figure 31.27 8-Bit Timer Output Timing
CKIO tTMRS
TMRI0, TMRI1
Figure 31.28 8-Bit Timer Reset Input Timing
Rev. 2.00 Sep. 07, 2007 Page 1278 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
CKIO tTMCS TMCI0, TMCI1 tTMCS
tTMCWL
tTMCWH
Figure 31.29 8-Bit Timer Clock Input Timing 31.3.8 Watchdog Timer Timing
Table 31.12 shows the timing of the watchdog timer. Table 31.12 Watchdog Timer Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item WDTOVF delay time Symbol tWOVD Min. Max. 100 Unit ns Figure Figure 31.30
CKIO tWOVD tWOVD
WDTOVF
Figure 31.30 Watchdog Timer Timing
Rev. 2.00 Sep. 07, 2007 Page 1279 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.9
SCIF Module Timing
Table 31.13 SCIF Module Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Symbol Min. 12 4 tSCKr tSCKf tSCKW tTXD tRXS tRXH -- -- 0.4 -- Max. 1.5 1.5 0.6 Unit tpcyc tpcyc tpcyc tpcyc tScyc Figure 31.32 Figure Figure 31.31
Input clock cycle (Clocked synchronous) tScyc (Asynchronous) Input clock rise time Input clock fall time Input clock width Transmit data delay time (Clocked synchronous) Receive data setup time (Clocked synchronous) Receive data hold time (Clocked synchronous)
3 tpcyc + 15 ns ns ns
4 tpcyc + 15 1 tpcyc + 15
Note: tpcyc indicates a peripheral clock (P) cycle.
tSCKW SCK
tSCKr
tSCKf
tScyc
Figure 31.31 SCK Input Clock Timing
tScyc SCK tTXD TxD (data transmit) tRXS tRXH RxD (data receive)
Figure 31.32 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 2.00 Sep. 07, 2007 Page 1280 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.10 IIC3 Module Timing Table 31.14 I2C Bus Interface 3 Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Specifications Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse removal time*2 SDA input bus free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA output fall time*3 tSTOS tSDAS tSDAH Cb tof 3 1 tpcyc* + 20 0 0 PVCC = 3.0 to 3.6 V --
1
Symbol tSCL tSCLH tSCLL tSr tSf tSP
Test Conditions
Min. 12 tpcyc* + 600 3 tpcyc*1 + 300 5 tpcyc*1 + 300
1
Typ.
Max.
Unit ns ns ns ns ns tpcyc*1 tpcyc*1 tpcyc*1 tpcyc*1 tpcyc*1 ns ns pF ns
Figure Figure 31.33

300 300 1.2

5 3 3
tBUF tSTAH tSTAS

400 250
Notes: 1. tpcyc indicates the peripheral clock (P) cycle. 2. Depends on the value of NF2CYC. 3. Indicates the I/O buffer characteristics.
Rev. 2.00 Sep. 07, 2007 Page 1281 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
SDA tBUF
VIH VIL tSTAH tSCLH tSTAS tSP tSTOS
SCL P* S* tSf tSCLL tSCL [Legend] S: Start condition P: Stop condition Sr: Start condition for retransmission Sr* tSr tSDAH tSDAS P*
Figure 31.33 I2C Bus Interface 3 Input/Output Timing 31.3.11 SSI Module Timing Table 31.15 SSI Module Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Output clock cycle Input clock cycle Clock high Clock low Clock rise time Delay Setup time Hold time AUDIO_CLK input frequency Symbol Min. tO tI tHC tLC tRC tDTR tSR tHTR fAUDIO 80 80 32 32 15 5 1 Typ. Max. Unit Remarks Output Input Bidirectional Figure Figure 31.34
64000 ns 64000 ns 20 50 40 ns ns ns ns ns ns MHz
Output (100 pF) Transmit Receive Receive Figures 31.35 and 31.36 Figures 31.37 and 31.38 Figures 31.37 and 31.38 Figure 31.39
Rev. 2.00 Sep. 07, 2007 Page 1282 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
tHC
tRC
SSISCKn
tLC
tI ,tO
Figure 31.34 Clock Input/Output Timing
SSISCKn
tDTR SSIWSn, SSIDATAn
Figure 31.35 SSI Transmit Timing (1)
SSISCKn
tDTR SSIWSn, SSIDATAn
Figure 31.36 SSI Transmit Timing (2)
SSISCKn
tSR SSIWSn, SSIDATAn
tHTR
Figure 31.37 SSI Receive Timing (1)
Rev. 2.00 Sep. 07, 2007 Page 1283 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
SSISCKn
tSR SSIWSn, SSIDATAn
tHTR
Figure 31.38 SSI Receive Timing (2)
fAUDIO
AUDIO_CLK
Figure 31.39 AUDIO_CLK Input Timing 31.3.12 RCAN-ET Module Timing [R5S72611] [R5S72613] Table 31.16 RCAN-ET Module Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Transmit data delay time Receive data setup time Receive data hold time Symbol tCTXD tCRXS tCRXH Min. 100 100 Max. 100 Unit ns Figure Figure 31.40
CKIO tCRXS CRx (receive data) tCTXD CTx (transmit data) tCRXH
Figure 31.40 RCAN-ET Input/Output Timing
Rev. 2.00 Sep. 07, 2007 Page 1284 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.13 A/D Trigger Input Timing Table 31.17 A/D Trigger Input Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Module A/D converter Item Symbol Min. (n - 1) x tcyc + 17 Max. Unit ns Figure Figure 31.41
Trigger input setup tTRGS time
Note: Above is the case in which the clock ratio B:P = n:1 (n = 1, 2, 3, 4, 6, 8, or 12)
CKIO
tTRGS
ADTRG
Figure 31.41 A/D Converter External Trigger Input Timing 31.3.14 I/O Port Timing Table 31.18 I/O Port Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Output data delay time Input data setup time Input data hold time Symbol tPORTD tPORTS tPORTH Min. 100 100 Max. 100 Unit ns Figure Figure 31.42
Rev. 2.00 Sep. 07, 2007 Page 1285 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
CKIO tPORTS Port (read) tPORTD Port (write) tPORTH
Figure 31.42 I/O Port Timing 31.3.15 H-UDI-Related Pin Timing Table 31.19 H-UDI-Related Pin Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item UDTCK cycle time UDTCK high pulse width UDTCK low pulse width UDTRST pulse width UDTRST setup time UDTDI setup time UDTDI hold time UDTMS setup time UDTMS hold time UDTDO delay time Note: * Symbol tTCKcyc tTCKH tTCKL tTRSW tTRSS tTDIS tTDIH tTMSS tTMSH tTDOD Min. 50* 0.4 0.4 20 200 10 10 10 10 Max. 0.6 0.6 16 Unit ns tTCKcyc tTCKcyc tTCKcyc ns ns ns ns ns ns Figure 31.45 Figure 31.44 Figure Figure 31.43
Should be greater than the peripheral clock (P) cycle time.
Rev. 2.00 Sep. 07, 2007 Page 1286 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
tTCKcyc tTCKH tTCKL VIH UDTCK (input) VIH 1/2 PVcc VIL VIL VIH 1/2 PVcc
Figure 31.43 UDTCK Input Timing
UDTCK (input)
tTRSS tTRSW UDTRST
tTRSS
Figure 31.44 UDTRST Input Timing
tTCKcyc UDTCK (input) tTDIS UDTDI tTMSS UDTMS tTDOD UDTDO change timing after switching command setting UDTDO tTDOD Initial value tTMSH tTDIH
Figure 31.45 H-UDI Data Transfer Timing
Rev. 2.00 Sep. 07, 2007 Page 1287 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.3.16 AUD-II Timing Table 31.20 AUD-II Timing Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item AUDRST pulse width AUDMD setup time RAM monitor clock cycle RAM monitor clock low pulse width RAM monitor clock high pulse width RAM monitor output data delay time RAM monitor input data setup time RAM monitor input data hold time RAM monitor SYNC setup time RAM monitor SYNC hold time Symbol tAUDRSTW tAUDMDS tRMCYC tRMCKWL tRMCKWH tRMDD tRMDS tRMDH tRMSS tRMSH Min. 5 5 33.33 0.4 0.4 2 15 5 15 5 Max. 0.6 0.6 14 Unit tRMCYC tRMCYC ns tRMCYC tRMCYC ns ns ns ns ns Figure 31.47 Figure Figure 31.46
tRMCYC
AUDCK (input)
tAUDRSTW AUDRST tAUDMDS
AUDMD
Figure 31.46 AUD Reset Timing
Rev. 2.00 Sep. 07, 2007 Page 1288 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
tRMCYC tRMCKWH tRMCKWL
VIHVIH VIL VIL
AUDCK (input)
1/2 PVCC
tRMDD
AUDATA3 to AUDATA0 (output)
tRMDS
tRMDH
AUDATA3 to AUDATA0 (input)
tRMSS
tRMSH
AUDSYNC (input)
Figure 31.47 RAM Monitor Timing 31.3.17 AC Characteristics Measurement Conditions * Input signal reference levels: high level = VIH min, low level = VIL max * Output signal reference level: PVCC/2 (PVCC = 3.0 to 3.6 V) * Input pulse level: PVSS to 3.0 V (where RES, MRES, NMI, MD1, MD0, MD_CLK1, MD_CLK0, ASEMD, UDTRST, and Schmitt trigger input pins are within PVSS to PVCC) * Input rise and fall times: 1 ns
LSI output pin Measurement point
CL
CMOS output
Note: CL is the total value that includes the capacitance of measurement tools. Each pin is set as follows: 30 pF: CKIO, SDRAS, SDCAS, CS0 to CS6, SDCS0, SDCS1, SDCKE, SDWE, DQM0 to DQM3 50 pF: All other pins
Figure 31.48 Measurement Circuit
Rev. 2.00 Sep. 07, 2007 Page 1289 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.4
A/D Converter Characteristics
Table 31.21 lists the A/D converter characteristics. Table 31.21 A/D Converter Characteristics Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min. 10 3.9*
2
Typ. 10
Max. 10
Unit bits s pF k LSB LSB LSB LSB LSB
1

20 5 3.0*1 2.0* 2.0* 0.5* 4.0
1

1
Notes: 1. Reference values 2. To satisfy the absolute accuracy, the conversion time should be 3.9 s or longer.
Rev. 2.00 Sep. 07, 2007 Page 1290 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.5
D/A Converter Characteristics
Table 31.22 lists the D/A converter characteristics. Table 31.22 D/A Converter Characteristics Conditions: PVCC = VCCR = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, PVCC - 0.3 V AVCC PVCC, AVref = 3.0 V to AVCC, PVSS = VSSR = PLLVSS = AVSS = 0 V
Item Resolution Conversion time Absolute accuracy Note: * Min. 8 Typ. 8 Max. 8 10 3.0 2.5 Unit bits s LSB LSB Load capacitance 20 pF Load resistance 2 M Load resistance 4 M Test Conditions
2.0*

Reference values
Rev. 2.00 Sep. 07, 2007 Page 1291 of 1312 REJ09B0320-0200
Section 31 Electrical Characteristics
31.6
Usage Note
Mount a multilayer ceramic capacitor between a pair of pins PVcc and PVss, VccR and VssR, or PLLVcc and PLLVss as a bypass capacitor. These capacitors must be placed as close as the power supply pins of the LSI. Also, a capacitor must be connected between the VCL and VSS pins to stabilize the power supply voltage that is internally lowered. Figure 31.49 is an example of externally allocated capacitors.
PVCC power supply PVCC power supply
PVCC power supply
PVCC power supply
PVCC power supply
PVCC power supply
1 VSSR 2 RES 3 PLLVCC 4 NMI 5 PLLVSS 6 RTC_X1 7 RTC_X2 8 PVSS 9 XTAL 10 EXTAL 11 PVSS 12 CKIO/SDCLK 13 PVCC 14 MD_CLK0 15 MD_CLK1 16 PVSS 17 PA0/A0 18 PVCC 19 PA1/A1 20 PA2/A2 21 PA3/A3 22 PA4/A4 23 PA5/A5 24 PA6/A6 25 PA7/A7 26 PA8/A8 27 PA9/A9 28 PA10/A10 29 PA11/A11 30 PA12/A12 31 PA13/A13 32 PA14/A14 33 PA15/A15 34 PA16/A16 35 PA17/A17 36 PA18/A18 37 PA19/A19 38 PVSS 39 PA20/A20 40 PVCC 41 PA21/A21 42 PA22/A22 43 PA23/A23 44 VCL
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
ASEMD MD1 MD0 WDTOVF PVSS PB0/D0 PVCC PB1/D1 PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 PB8/D8 PB9/D9 PB10/D10 PB11/D11 PB12/D12 PB13/D13 PB14/D14 PB15/D15 PVSS PB16/D16/IRQ0/TIOC3A PVCC PB17/D17/IRQ1/TIOC3B PB18/D18/IRQ2/TIOC3C PB19/D19/IRQ3/TIOC3D PB20/D20/IRQ4/TIOC4A/TxD2 PB21/D21/IRQ5/TIOC4B/RxD2 PB22/D22/IRQ6/TIOC4C/SCK2 PB23/D23/IRQ7/TIOC4D PB24/D24/PINT0/TIC5U/TxD6 PB25/D25/PINT1/TIC5V/RxD6 PVCC PB26/D26/PINT2/TIC5W/SCK6 PVSS PB27/D27/PINT3 PB28/D28/PINT4/TMO0/TxD3 PB29/D29/PINT5/TMRI0/RxD3 PB30/D30/PINT6/TMCI0/SCK3 PB31/D31/PINT7 VCCR MRES
ASEBRK/ASEBRKAK 132 UDTCK 131 UDTDI 130 UDTDO 129 UDTMS 128 PVCC 127 UDTRST 126 PVSS 125 AUDIO_X1 124 AUDIO_X2 123 PVSS 122 PD0/AUDIO_CLK 121 PD1/SSIDATA0 120 PD2/SSISCK0 119 PD3/SSIWS0 118 PD4/TxD4/SSIDATA1 117 PD5/RxD4/SSISCK1 116 PD6/SCK4/SSIWS1 115 PD7/TIOC0A/TxD0/DACT1 114 PD8/TIOC0B/RxD0/DTEND1 113 PD9/TIOC0C/SCK0 112 PD10/TMO1/TIOC0D/TxD1 111 PD11/TMRI1/RxD1 110 PD12/TMCI1/SCK1 109 PD13/DREQ1 108 PD14/DACK1 107 PD15/SDA2 106 PD16/SCL2 105 PF7/AUDATA3 104 PVSS 103 PF6/AUDATA2 102 PVCC 101 PF5/AUDATA1 100 PF4/AUDATA0 99 PF3/AUDSYNC 98 PF2/TCLKD/SCK7/AUDCK 97 PF1/RxD7/AUDMD 96 PF0/TxD7/AUDRST 95 AVSS 94 PE7/IRQ7/AN7/DA1 93 PE6/IRQ6/AN6/DA0 92 PE5/IRQ5/AN5 91 PE4/IRQ4/AN4 90 PE3/PINT7/AN3 89
LQFP2424-176Cu (FP-176EV) Top view
PE2/PINT6/AN2 88 PE1/PINT5/AN1 87 PE0/PINT4/AN0 86 AVREF 85 AVCC 84 PC0/CS0 83 PC1/CS1 82 PC2/CS2/SDCS1/ADTRG 81 PC3/CS3/UBCTRG 80 PC4/CS4/TIOC1A/TxD5 79 PC5/CS5/TIOC1B/RxD5 78 PC6/CS6/TCLKA/SCK5 77 PVCC 76 PC7/SDCS0 75 PVSS 74 PC8/RD 73 PC9/WR0 72 PC10/WR1 71 PC11/WR2/TIOC2A/DACT2 70 PC12/WR3/TIOC2B/DTEND2 69 PC13/WAIT 68 PC14/SDCKE 67 PC15/SDRAS 66 PC16/SDCAS 65 PC17/SDWE 64 PC18/BC0/DQM0 63 PC19/BC1/DQM1 62 PC20/BC2/DQM2/TCLKB 61 PC21/BC3/DQM3/TCLKC/DACK2 60 PC22/IRQ0/SCL0/DREQ2 59 PC23/IRQ1/SDA0 58 PC24/IRQ2/SCL1 57 PC25/IRQ3/SDA1 56 PVSS 55 PA31/CRx1/DTEND0 54 PVCC 53 PA30/CTx1/DACT0 52 PA29/CRx0/DACK0 51 PA28/CTx0/DREQ0 50 PA27/A27/PINT3/DTEND3 49 PA26/A26/PINT2/DACT3 48 PA25/A25/PINT1/DACK3 47 PA24/A24/PINT0/DREQ3 46 VSS 45
PVCC power supply
PVCC power supply
PVCC power supply
PVCC power supply
PVCC power supply
Cin, Cout
CL1, CL2
Figure 31.49 Example of Externally Allocated Capacitors
Rev. 2.00 Sep. 07, 2007 Page 1292 of 1312 REJ09B0320-0200
PVCC power supply
0.1 F
Appendix
Appendix
A. Pin States
Pin States
Pin Function Reset State Power-On*
2
Table A.1
Pin State Power-Down State
Area 0 Data Bus Width Type Clock Pin Name CKIO (clock modes 0 and 2) CKIO (clock mode 3) XTAL (clock modes 0 and 2) XTAL 1 (clock mode 3)* EXTAL (clock modes 0 and 2) EXTAL 1 (clock mode 3)* System control RES MRES WDTOVF ASEBRK/ASEBRKAK Mode MD1, MD0 MD_CLK1, MD_CLK0 ASEMD Interrupt NMI IRQ7 to IRQ0 PINT7 to PINT0 8 Bits O I O O I Z I -- O H I I I I -- -- 16 Bits O I O O I Z I -- O H I I I I -- -- 32 Bits O I O O I Z I -- O H I I I I -- -- Manual O I O O I Z I I O O I I I I I I O I O O I Z I I O O I I I I I I Sleep
Software Standby L/Z* I L L I Z I I K I I I I I I I
5
Deep Standby L/Z* I L L I Z I I K K I I I I I*
3 5
--
Rev. 2.00 Sep. 07, 2007 Page 1293 of 1312 REJ09B0320-0200
Appendix
Pin Function Reset State Power-On*
2
Pin State Power-Down State
Area 0 Data Bus Width Type Address data Pin Name A27 to A24 A23 to A0 D31 to D16 D15 to D8 D7 to D0 Bus control WAIT CS0 CS6 to CS1 RD WR3 WR2 WR1 WR0 BC3 to BC0 SDCS1, SDCS0 SDRAS SDCAS SDWE DQM3 to DQM0 SDCKE DMAC DREQ3 to DREQ0 DACK3 to DACK0 DACT3 to DACT0 DTEND3 to DTEND0 8 Bits Z L -- -- Z -- H -- H -- -- -- H -- -- -- -- -- -- -- -- -- -- -- 16 Bits Z L -- Z Z -- H -- H -- -- H H -- -- -- -- -- -- -- -- -- -- -- 32 Bits Z L Z Z Z -- H -- H H H H H -- -- -- -- -- -- -- -- -- -- -- Manual O O I/O I/O I/O I O O O O O O O O O O O O O O I O O O O O I/O I/O I/O I O O O O O O O O O O O O O O I O O O Sleep
Software Standby K K Z Z Z Z K K K K K K K K K K K K K K Z K K K
Deep Standby K K K K K Z K K K K K K K K K K K K K K Z K K K
Rev. 2.00 Sep. 07, 2007 Page 1294 of 1312 REJ09B0320-0200
Appendix
Pin Function Reset State Power-On*
2
Pin State Power-Down State
Area 0 Data Bus Width Type MTU2 Pin Name TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A to TIOC3D TIOC4A to TIOC4D TIC5U, TIC5V, TIC5W TMR TMO1, TMO0 TMCI1, TMCI0 TMRI1, TMRI0 SCIF SCK7 to SCK0 RxD7 to RxD0 TxD7 to TxD0 IIC3 SCL2 to SCL0 SDA2 to SDA0 SSI 8 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I O -- -- -- -- 32 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I O -- -- -- -- Manual I I/O I/O I/O I/O I/O I O I I I/O I O I/O I/O I/O I/O I/O I I O I O I O I I/O I/O I/O I/O I/O I O I I I/O I O I/O I/O I/O I/O I/O I I O I O I O Sleep
Software Standby Z K K K K K Z K Z Z K Z K Z Z K K K Z I O Z K Z K
Deep Standby Z K K K K K Z K Z Z K Z K Z Z K K K Z I O Z K Z K
SSIDATA1, SSIDATA0 -- SSISCK1, SSISCK0 SSIWS1, SSIWS0 AUDIO_CLK AUDIO_X1* AUDIO_X2*
1
-- -- -- I O -- -- -- --
1
RCAN_ET CRx1, CRx0 CTx1, CTx0 IEB IERxD IETxD
Rev. 2.00 Sep. 07, 2007 Page 1295 of 1312 REJ09B0320-0200
Appendix
Pin Function Reset State Power-On*
2
Pin State Power-Down State
Area 0 Data Bus Width Type A/D converter D/A converter RTC Pin Name AN7 to AN0 ADTRG DA1, DA0 RTC_X1* RTC_X2* AUD-II AUDRST AUDMD AUDSYNC AUDCK
1
8 Bits -- -- -- I O -- -- -- --
16 Bits -- -- -- I O -- -- -- -- -- I I I
32 Bits -- -- -- I O -- -- -- -- -- I I I
Manual I I O I O I I I/O I/O I/O I I I I I O I O I I
Sleep
Software Standby Z Z O I O I I I/O I/O I/O I I I
Deep Standby Z Z Z I O Z Z K K K I I I
1
I/O I/O I/O I I I
4
AUDATA3 to AUDATA0 -- H-UDI UDTCK UDTMS UDTDI UDTDO UDTRST UBC I/O ports UBCTRG PA31 to PA28 PA27 to PA0 PB31 to PB16 PB15 to PB8 PB7 to PB0 I I I O/Z* I -- I L I I Z
4
O/Z* I -- I L I Z Z
4
O/Z* I -- I L Z Z Z
4
O/Z* I O I/O I/O I/O I/O I/O
O/Z* I O I/O I/O I/O I/O I/O
4
O/Z* I O K K K K K
4
K I K K K K K K
Rev. 2.00 Sep. 07, 2007 Page 1296 of 1312 REJ09B0320-0200
Appendix
Pin Function Reset State Power-On*
2
Pin State Power-Down State
Area 0 Data Bus Width Type I/O ports Pin Name PC25 to PC22 PC21 to PC13 PC12, PC11 PC10 PC9 PC8 PC7 to PC1 PC0 PD16, PD15 PD14 to PD0 PE7 to PE0 PF7 to PF0 I I I I H H I H I I I I 8 Bits I I I H H H I H I I I I 16 Bits I I H H H H I H I I I I 32 Bits Manual I I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I/O I/O I/O I/O I/O I/O I I/O I I/O Sleep
Software Standby Z K K K K K K K Z K Z K
Deep Standby Z K K K K K K K Z K Z K
[Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. When pins for the connection with a crystal resonator are not used, the EXTAL and AUDIO_X1 pins must be pulled up and the XTAL and AUDIO_X2 pins must be open. The RTC_X1 pin must be connected to GND and the RTC_X2 must be open. 2. Power-on reset by low-level input to the RES pin. The pin states after a power-on reset by the H-UDI reset assert command or WDT overflow are the same as the initial pin states at normal operation (see section 25, Pin Function Controller (PFC)). 3. IRQ pins that can release deep standby mode are limited to PE7 to PE4 and PC25 to PC22. 4. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state. 5. L when the CKIO output is specified and Z when the CKIO output is stopped with the setting of CKIOCR.
Rev. 2.00 Sep. 07, 2007 Page 1297 of 1312 REJ09B0320-0200
B.
JEITA Package Code PLQP0176KB-A 176P6Q-A / FP-176E / FP-176EV 1.8g
RENESAS Code
Previous Code
MASS[Typ.]
Appendix
E
*2
HE
c1
c
ZE
A
ZD
F
A2
Index mark
c
A1
REJ09B0320-0200
HD *1 D 89
P-LQFP176-24x24-0.50
132
Package Dimensions
Rev. 2.00 Sep. 07, 2007 Page 1298 of 1312
88 bp b1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Terminal cross section
Reference Symbol
133
Dimension in Millimeters Min D 23.9 E A2 HD HE A A1 L L1 bp b1 0.05 0.15 0.1 0.20 0.18 25.8 25.8 23.9 Nom 24.0 24.0 1.4 26.0 26.0 26.2 26.2 1.7 0.15 0.25 Max 24.1 24.1
Figure B.1 Package Dimensions
45 44 e
p
176
1
y
*3 b
x Detail F
c c1
0.09
0.145 0.125 0 e x y ZD ZE L L1 0.35 1.25 1.25 0.5 1.0 0.5
0.20
8
0.08 0.10
0.65
Main Revisions and Additions in this Edition
Main Revisions and Additions in this Edition
Item Table 1.2 Product Lineup Page Revision (See Manual for Details) 10 Modified
Abbreviation R5S72611 Product Code R5S72611RB120FP R5S72611RP100FP R5S72611RP80FP R5S72612 R5S72612RB120FP R5S72612RP100FP R5S72612RP80FP R5S72613 R5S72613RB120FP R5S72613RP100FP R5S72613RP80FP
4.4.2 CKIO Control Register (CKIOCR)
90
Modified
When this LSI is started in clock operating mode 3, CKIOCR is initialized to H'00 by a power-on reset caused by the RES pin or in deep standby mode. When this LSI is started in clock operating mode 0 or 2, CKIOCR is initialized to H'01 by a power-on reset caused by the RES pin or in deep standby mode. This register is not initialized by an internal reset triggered by an overflow of the WDT, a manual reset, in sleep mode, or in software standby mode.
9.5.2 SDRAM Interface (9) Read/Write Access (c) Byte Access Control by DQM Figure 9.26 SDRAMC Setting Procedure 9.6.2 Write Buffer 9.6.3 Note on Transition to Software Standby Mode or Deep Standby Mode
264
Added
268 288, 289
Figure modified Added
Rev. 2.00 Sep. 07, 2007 Page 1299 of 1312 REJ09B0320-0200
Main Revisions and Additions in this Edition
Item 11.1 Features
Page Revision (See Manual for Details) 306 Modified
1. Single data transfer: Transfer in one read cycle and one write cycle by the DMAC (in the case of dual address transfer), and one read cycle or one write cycle transfer by the DMAC (at single address transfer) 2. Single operand transfer: Continuous data transfer by the DMAC on one channel (amount of data to be transferred is set in a register) : 6. BIU: Bus Interface Unit (peripheral module). One of the following four kinds according to the source or destination of transfer. BIU_E: BIU_P: External space (normal space and SDRAM space) Peripheral bus (1) (see figure 1.1)
BIU_SH: Peripheral bus (2) (see figure 1.1), on-chip RAM space BIU_C: Peripheral bus (3) (see figure 1.1)
15.5.1 Register Writing during RTC Count
665
Modified Do not write to the count registers (RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, and RYRCNT) during the RTC counting (while the START bit in RCR2 is 1). If any of the count registers is written to during the RTC counting, the count register may not be read correctly immediately after the execution of a write instruction. The RTC counting must be stopped before writing to any of the count registers.
Figure 16.11 Sample Flowchart for Transmitting Serial Data
720
Modified
Yes Write transmit data to SCFTDR and read 1 from TDFE and TEND flags in SCFSR, then clear these flags to 0 All data transmitted? [1] [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear these flags to 0
No
Rev. 2.00 Sep. 07, 2007 Page 1300 of 1312 REJ09B0320-0200
Main Revisions and Additions in this Edition
Item Figure 16.16 Sample Flowchart for Transmitting/Receiving Serial Data
Page Revision (See Manual for Details) 724 Modified
[1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear these flags to 0. The transition of the TDFE flag from
Yes Write transmit data to SCFTDR, and read 1 from TDFE and TEND flags in SCFTDR, then clear these flags to 0
[1]
Figure 17.22 Bit Synchronous Circuit Timing Table 17.5 Time for Monitoring SCL
768 769
Figure modified Modified
CKS3 1 CKS2 0 1 Time for Monitoring SCL 33 tpcyc 81 tpcyc
17.7.1 Issuance of Stop Condition 770 and Start Condition (Retransmission) 17.7.2 Settings for Multi-Master Operation 17.7.3 Reading ICDRR in Master Receive Mode 18.3.1 Control Register (SSICR) 778 770
Title added
Added
Added
Bit 11 Bit Name SPDP Description Serial Padding Polarity 0: Padding bits are low. 1: Padding bits are high. Note: When MUEN = 1, padding bits are low. (The MUTE function is given priority.)
Rev. 2.00 Sep. 07, 2007 Page 1301 of 1312 REJ09B0320-0200
Main Revisions and Additions in this Edition
Item 18.3.2 Status Register (SSISR)
Page Revision (See Manual for Details) 785 Modified
Bit 0 Bit Name IDST Description : * SSI = Master transmitter (SWSD = 1 and TRMD = 1) This bit is set to 1 if the EN bit is cleared and the data written to SSITDR is completely output from the serial data input/output pin (SSIDATA), that is, the output of the system word length is completed.
18.4.1 Bus Format
787
Modified The bus format can be selected from one of the four major modes shown in table 18.3.
18.4.2 Non-Compressed Modes (6) Multi-channel Formats
793
Modified The SSI module supports the transfer of 2, 3 and 4 channels by using the CHNL, SWL and DWL bits only when the system word length (SWL) is greater than or equal to the data word length (DWL) multiplied by channels (CHNL).
18.4.2 Non-Compressed Modes (6) Multi-channel Formats Figure 18.7 Multichannel Format (2 Channels Without Padding)
793
Modified Figures 18.7 to 18.9 show how 2, 3 and 4 channels are transferred to ...
793
Modified SCKP = 0, SWSP = 0, DEL = 1, CHNL = 01, SPDP = don't care, SDTA = don't care System word length = data word length x 2
Figure 18.8 Multichannel Format (3 Channels with High Padding)
793
Modified SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = 1, SDTA = 0 System word length = data word length x 3
Figure 18.9 Multichannel Format (4 Channels; Transmitting and Receiving in the order of Padding Bits and Serial Data; with Padding)
794
Modified SCKP = 0, SWSP = 0, DEL = 1, CHNL = 11, SPDP = 0, SDTA = 1 System word length = data word length x 4
Rev. 2.00 Sep. 07, 2007 Page 1302 of 1312 REJ09B0320-0200
Main Revisions and Additions in this Edition
Item
Page Revision (See Manual for Details) Modified
* Don't set MCR5 (Sleep Mode) without entering Halt
19.6.1 Configuration of RCAN-ET 860 (4) CAN sleep mode
Mode.
* After setting MCR1, make sure that GSR4 is set and
the RCAN-ET has entered Halt Mode before clearing MCR1. 20.8 Usage Notes 22.7.7 Usage Note when Shifting to Single Mode during A/D Conversion 27.2.9 Deep Standby Oscillation Settling Clock Select Register (DSCNT) 941, 942 Added
1036 Added
1139 Notes added
Bit Bit Name Description 2 to 0 CKS[2:0]
Clock Select
: Setting value
000: 001: 010: 011: 100:
Clock select
1 x P*1 1/64 x P*1 1/128 x P*1 1/256 x P*2 1/512 x P*2
Notes: 1. Do not use this setting. 2. Set the clock so that it is equal to or longer than the oscillation settling time 2 on return from standby (tOSC3).
27.2.10 Deep Standby Cancel Source Flag Register (DSFR)
1140, Added 1141 Note: * Only 0 can be written after reading 1 to clear the flag. Even when IRQ is input after a manual reset has been accepted as a source canceling deep standby, the IRQ flag is not set. 1151 Title added
27.4.1 Note on Setting Registers
27.4.2 Note on Canceling Standby 1151 Added Mode when an External Clock is being Input
Rev. 2.00 Sep. 07, 2007 Page 1303 of 1312 REJ09B0320-0200
Main Revisions and Additions in this Edition
Item Table A.1 Pin States
Page Revision (See Manual for Details) 1294 Modified
Pin State Power-Down State Type Bus control CS0 CS6 to CS1 RD WR3 WR2 WR1 WR0 BC3 to BC0 SDCS1, SDCS0 SDRAS SDCAS SDWE DQM3 to DQM0 Pin Name Software Standby K K K K K K K K K K K K K
Rev. 2.00 Sep. 07, 2007 Page 1304 of 1312 REJ09B0320-0200
Index
Numerics
16-bit counter mode................................ 618 16-bit/32-bit displacement ........................ 33 8-bit timers (TMR) ................................. 601
B
Bit manipulation instructions .................... 63 Bit synchronous circuit ........................... 767 Block diagram........................................... 11 Branch instructions ................................... 57 Break detection and processing............... 727 Break on data access cycle...................... 179 Break on instruction fetch cycle.............. 178 Bus monitor............................................. 291 Bus state controller (BSC) ...................... 205 Bus timing............................................. 1264
A
A/D conversion time (multi mode and scan mode)............................................ 1030 A/D conversion time (single mode)...... 1029 A/D conversion timing ......................... 1029 A/D converter (ADC) ........................... 1011 A/D converter activation......................... 539 A/D converter characteristics................ 1290 A/D converter start request delaying function................................................... 529 A/D trigger input timing ....................... 1285 Absolute address....................................... 33 Absolute address accessing....................... 33 Absolute maximum ratings................... 1249 AC characteristics................................. 1258 AC characteristics measurement conditions ............................................. 1289 Address array.................................. 188, 200 Address array read .................................. 200 Address errors......................................... 105 Address map ........................................... 209 Address-array write (associative operation) ............................ 201 Address-array write (non-associative operation)................................................ 201 Addressing modes..................................... 34 Advanced user debugger II (AUD-II)............................................... 1161 Analog input pin ratings ....................... 1035 Arithmetic operation instructions ............. 52
C
Cache ...................................................... 187 Calculating exception handling vector table addresses ........................................ 100 CAN interface ......................................... 813 CAN sleep mode ..................................... 859 Canceling software standby mode .......... 633 Cascaded connection............................... 618 CD-ROM decoder (ROM-DEC) ............. 943 Changing the division ratio ....................... 92 Changing the frequency .................... 91, 633 Changing the multiplication rate............... 91 Clock frequency control circuit................. 79 Clock operating modes ............................. 81 Clock pulse generator (CPG) .................... 77 Clock timing ......................................... 1258 Clocked synchronous serial format......... 757 Coherency of cache and external memory ................................................... 200 Compare match count mode ................... 619 Compare match signal............................. 616 Complementary PWM mode .................. 493 Control signal timing ............................ 1262 Controller area network (RCAN-ET)...... 809
Rev. 2.00 Sep. 07, 2007 Page 1305 of 1312 REJ09B0320-0200
CPU .......................................................... 23 Crystal oscillator....................................... 79 CSC interface.......................................... 242
F
Floating point operation instructions ........ 60 Floating-point ranges ................................ 69 Floating-point registers ............................. 71 Floating-point unit (FPU) ......................... 67 Format of double-precision floating-point number ............................... 68 Format of single-precision floating-point number ............................... 67 FPU exception........................................... 75 FPU-related CPU instructions................... 62 Full-scale error...................................... 1032
D
D/A converter (DAC) ........................... 1037 D/A converter characteristics ............... 1291 D/A output hold function in software standby mode........................................ 1042 Data array ....................................... 188, 201 Data array read ....................................... 202 Data array write ...................................... 202 Data format in registers ............................ 28 Data formats in memory ........................... 28 Data transfer instructions.......................... 48 DC characteristics................................. 1250 Dead time compensation ........................ 534 Definitions of A/D conversion accuracy................................................ 1031 Delayed branch instructions ..................... 31 Denormalized numbers............................. 70 Direct memory access controller (DMAC) ................................................. 305 Displacement accessing............................ 33 Divider...................................................... 79
G
General illegal instructions ..................... 112 General registers ....................................... 23 Global base register (GBR)....................... 26
H
Halt mode................................................ 858 H-UDI commands................................. 1156 H-UDI interrupt ............................ 137, 1159 H-UDI reset .......................................... 1159 H-UDI-related pin timing ..................... 1286
E
Effective address calculation .................... 34 Equation for getting SCBRR value......... 692 Exception handling ................................... 95 Exception handling state........................... 65 Exception handling vector table ............... 99 Exception source generation immediately after delayed branch instruction.............. 114 Exceptions triggered by instructions ...... 111 External pulse width measurement......... 533 External trigger input timing ................ 1030
I
I/O port timing ...................................... 1285 I/O ports ................................................ 1043 I2C bus format......................................... 748 I2C bus interface 3 (IIC3)........................ 729 ID Reorder .............................................. 824 IEBus controller (IEB) ........................ 875 IIC3 module timing............................... 1281 Immediate data.......................................... 32 Immediate data accessing ......................... 32 Immediate data format .............................. 29 Initial values of general registers .............. 27
Rev. 2.00 Sep. 07, 2007 Page 1306 of 1312 REJ09B0320-0200
Instruction features ................................... 30 Instruction format ..................................... 38 Instruction set ........................................... 42 Integer division instructions ................... 113 Interrupt controller (INTC)..................... 119 Interrupt exception handling................... 110 Interrupt exception handling vectors and priorities ........................................... 141 Interrupt priority level............................. 109 Interrupt response time ........................... 153 IRQ interrupts ......................................... 138
J
Jump table base register (TBR) ................ 26
L
List of registers ..................................... 1167 Load-store architecture ............................. 31 Local acceptance filter mask (LAFM).... 821 Logic operation instructions ..................... 55 LRU ........................................................ 189
MTU2 functions...................................... 374 MTU2 interrupts ..................................... 537 MTU2 module timing ........................... 1277 MTU2 output pin initialization ............... 568 Multi mode............................................ 1023 Multi-function timer pulse unit 2 (MTU2)................................................... 373 Multiplexed pin table (Port A) .............. 1061 Multiplexed pin table (Port B) .............. 1063 Multiplexed pin table (Port C) .............. 1065 Multiplexed pin table (Port D) .............. 1067 Multiplexed pin table (Port E) .............. 1068 Multiplexed pin table (Port F)............... 1068 Multiply and accumulate register high (MACH)............................................ 26 Multiply and accumulate register low (MACL) .................................................... 26 Multiply/Multiply-and-accumulate operations.................................................. 31
N
NaN........................................................... 70 NMI interrupt.......................................... 137 Noise filter .............................................. 761 Nonlinearity error.................................. 1032 Non-numbers (NaN) ................................. 69 Note on making a transition to deep standby mode ........................................ 1150 Note on using a PLL oscillation circuit..... 94 Note on using crystal resonator................. 93
M
Mailbox................................................... 812 Mailbox control ...................................... 813 Mailbox structure.................................... 816 Manual reset ........................................... 104 Master receive operation......................... 751 Master transmit operation ....................... 749 Measurement circuit ............................. 1289 Memory-mapped cache .......................... 200 Message control field.............................. 817 Message data fields................................. 822 Message receive sequence ...................... 865 Message transmission sequence.............. 863 Micro processor interface (MPI)............. 812 Module standby function ...................... 1151
O
Offset error............................................ 1032 On-chip peripheral module interrupts ........... 139 On-chip RAM ....................................... 1123 Operation in asynchronous mode............ 708 Operation in clocked synchronous mode ....................................................... 717
Rev. 2.00 Sep. 07, 2007 Page 1307 of 1312 REJ09B0320-0200
P
Package dimensions.............................. 1298 Page conflict ......................................... 1124 Permissible signal source impedance ... 1035 Pin assignments ........................................ 12 Pin function controller (PFC) ............... 1061 PINT interrupts....................................... 139 PLL circuit................................................ 79 Power-down modes .............................. 1125 Power-down state ..................................... 65 Power-on reset ........................................ 102 Prefetch operation (only for operand cache)......................... 197 Procedure register (PR) ............................ 27 Processing of analog input pins ............ 1034 Program counter (PC)............................... 27 Program execution state............................ 65
Q
Quantization error................................. 1032
R
RCAN-ET bit rate calculation ................ 835 RCAN-ET interrupt sources ................... 869 RCAN-ET memory map......................... 814 Realtime clock (RTC)............................. 639 Receive data sampling timing and receive margin (asynchronous mode) ..... 728 Reconfiguration of mailbox.................... 867 Register bank error exception handling .......................................... 107, 162 Register bank errors................................ 107 Register bank exception.......................... 162 Register banks .................................. 27, 158 Register banks and bank control registers .................................................. 159
Registers ABACK0 ............................................ 851 ACSWR .............................................. 241 ADCSR ............................................. 1016 ADDR ............................................... 1014 BAMR................................................. 169 BAR .................................................... 168 BBR .................................................... 172 BCR .................................................... 832 BDMR................................................. 171 BDR .................................................... 170 BRCR.................................................. 174 CBUFCTL .......................................... 980 CBUFST ............................................. 966 CCR .................................................... 190 CKIOCR ............................................... 90 CROMCTL ......................................... 954 CROMEN ........................................... 952 CROMST............................................ 960 CROMST0M ...................................... 983 CROMSY0 ......................................... 953 CS1WCNTn........................................ 221 CS2WCNTn........................................ 223 CSMODn ............................................ 218 CSnCNT ............................................. 213 CSnREC.............................................. 215 DACR ............................................... 1039 DADR0 ............................................. 1039 DADR1 ............................................. 1039 DMASTS ............................................ 344 DMCBCT ........................................... 314 DMCDADR........................................ 313 DMCNTA ........................................... 324 DMCNTB ........................................... 332 DMCSADR......................................... 312 DMEDET............................................ 342 DMICNT............................................. 339 DMICNTA.......................................... 340 DMISTS.............................................. 341 DMMOD............................................. 318
Rev. 2.00 Sep. 07, 2007 Page 1308 of 1312 REJ09B0320-0200
DMRBCT ........................................... 317 DMRDADR........................................ 316 DMRSADR ........................................ 315 DMSCNT............................................ 338 DREQER ............................................ 133 DSCNT ............................................. 1139 DSFR ................................................ 1140 FPSCR .................................................. 72 FPUL .................................................... 73 FRQCR ................................................. 87 GSR .................................................... 829 HEAD ................................................. 968 IBCR................................................... 131 IBNR................................................... 132 ICCR................................................... 733 ICDRR................................................ 746 ICDRS ................................................ 746 ICDRT ................................................ 746 ICIER.................................................. 740 ICMR.................................................. 738 ICR ..................................................... 125 ICSR ................................................... 742 IEAR................................................... 901 IECKSR.............................................. 924 IECMR ............................................... 897 IECTR................................................. 896 IEFLG................................................. 910 IEIER.................................................. 923 IEIET .................................................. 917 IELA ................................................... 908 IEMA.................................................. 905 IEMCR ............................................... 899 IERB ................................................... 927 IERBFL .............................................. 908 IERCTL .............................................. 907 IERSR................................................. 919 IESA ................................................... 903 IETB ................................................... 926 IETBFL............................................... 904 IETSR ................................................. 913
IMR..................................................... 843 INHINT............................................... 989 INTHOLD........................................... 988 IPR ...................................................... 123 IRQRR ................................................ 127 IRR...................................................... 837 MBIMR0............................................. 854 MCR.................................................... 823 NF2CYC ............................................. 747 PACR ................................................ 1072 PADR................................................ 1044 PAIOR .............................................. 1071 PAPR ................................................ 1046 PBCR ................................................ 1083 PBDR ................................................ 1048 PBIOR............................................... 1082 PBPR................................................. 1050 PCCR ................................................ 1097 PCDR ................................................ 1052 PCIOR............................................... 1096 PCPR................................................. 1053 PDCR ................................................ 1108 PDDR................................................ 1055 PDIOR .............................................. 1107 PDPR ................................................ 1056 PECR ................................................ 1115 PEPR................................................. 1057 PFCR................................................. 1119 PFDR ................................................ 1059 PFIOR ............................................... 1118 PFPR ................................................. 1060 PINTER .............................................. 129 PIRR.................................................... 130 R64CNT.............................................. 642 RAMKP ............................................ 1138 RCR .................................................... 657 RDAYAR............................................ 654 RDAYCNT ......................................... 647 REC..................................................... 844 RFPR0................................................. 853
Rev. 2.00 Sep. 07, 2007 Page 1309 of 1312 REJ09B0320-0200
RHRAR .............................................. 652 RHRCNT............................................ 645 RINGBUFCTL ................................... 990 RMINAR ............................................ 651 RMINCNT.......................................... 644 RMONAR........................................... 655 RMONCNT ........................................ 648 RSECAR............................................. 650 RSECCNT .......................................... 643 RSTSTAT........................................... 985 RWKAR ............................................. 653 RWKCNT........................................... 646 RXPR0................................................ 852 RYRAR .............................................. 656 RYRCNT............................................ 649 SAR (IIC3) ......................................... 745 SCBRR ............................................... 692 SCFCR................................................ 700 SCFDR ............................................... 702 SCFRDR............................................. 675 SCFSR ................................................ 684 SCFTDR............................................. 676 SCLSR................................................ 705 SCRSR................................................ 675 SCSCR................................................ 680 SCSMR............................................... 677 SCSPTR.............................................. 703 SCTSR................................................ 676 SDBPR ............................................. 1155 SDCKSCNT ....................................... 240 SDCmCNT ......................................... 217 SDDPWDCNT ................................... 233 SDIR......................................... 229, 1156 SDmADR ........................................... 234 SDmMOD........................................... 237 SDmTR............................................... 235 SDPWDCNT ...................................... 232 SDRFCNT0 ........................................ 226 SDRFCNT1 ........................................ 227 SDSTR................................................ 238
Rev. 2.00 Sep. 07, 2007 Page 1310 of 1312 REJ09B0320-0200
SHEAD ............................................... 970 SSI ...................................................... 985 SSICR ................................................. 775 SSIRDR .............................................. 786 SSISR.................................................. 781 SSITDR............................................... 786 STBCR.............................................. 1128 STRMDIN .......................................... 991 STRMDOUT ...................................... 993 SYCBEEN .......................................... 292 SYCBESTS1....................................... 293 SYCBESTS2....................................... 295 SYCBESW ......................................... 298 SYSCR.............................................. 1136 TADCOBRA_4 .................................. 431 TADCOBRB_4................................... 431 TADCORA_4 ..................................... 430 TADCORB_4 ..................................... 430 TADCR............................................... 427 TBTER................................................ 455 TBTM ................................................. 425 TCBR.................................................. 452 TCCR.................................................. 607 TCDR.................................................. 451 TCNT.......................................... 431, 604 TCNTCMPCLR.................................. 412 TCNTS................................................ 450 TCORA............................................... 604 TCORB ............................................... 605 TCR............................................. 386, 605 TCSR .................................................. 609 TCSYSTR........................................... 437 TDDR ................................................. 451 TDER.................................................. 457 TEC..................................................... 844 TGCR.................................................. 448 TGR .................................................... 432 TICCR................................................. 426 TIER ................................................... 413 TIOR ................................................... 393
TITCNT .............................................. 454 TITCR................................................. 452 TMDR................................................. 390 TOCR ................................................. 441 TOER.................................................. 440 TOLBR ............................................... 447 TRWER .............................................. 439 TSR..................................................... 418 TSTR .................................................. 433 TSYR.................................................. 435 TWCR................................................. 458 TXACK0 ............................................ 850 TXCR0 ............................................... 849 TXPR0................................................ 846 TXPR1................................................ 846 UMSR................................................. 855 WRCSR .............................................. 630 WTCNT .............................................. 627 WTCSR .............................................. 628 Relationship between clock operating mode and frequency range........................ 82 Reset state ................................................. 65 Reset-synchronized PWM mode ............ 490 Restoration from bank ............................ 160 Restoration from stack............................ 161 Restriction on DMAC usage................... 727 RISC-type instruction set.......................... 30 Rounding .................................................. 74 RTC crystal oscillator circuit.................. 666
Serial communication interface with FIFO (SCIF)............................................ 669 Serial Sound Interface (SSI) ................... 771 Setting analog input voltage........ 1033, 1042 Shift instructions ....................................... 56 Sign extension of word data...................... 30 Single mode .......................................... 1020 Slave receive operation ........................... 756 Slave transmit operation.......................... 753 Sleep mode............................................ 1142 Slot illegal instructions ........................... 112 Software standby mode......................... 1143 Stack after interrupt exception handling .................................................. 152 Stack status after exception handling ends ......................................................... 115 Standby control circuit.............................. 79 Status register (SR) ................................... 24 System control instructions....................... 58
T
T bit........................................................... 32 TAP controller ...................................... 1157 Test mode settings................................... 861 The address map for each mailbox.......... 815 Time quanta is defined............................ 832 Timing to clear an interrupt source ......... 164 Transfer rate............................................ 735 Trap instructions ..................................... 112 Types of exception handling and priority order ............................................. 95
S
Saving to bank ........................................ 159 Saving to stack........................................ 161 Scan mode ............................................ 1025 SCIF interrupt sources ............................ 725 SCIF module timing ............................. 1280 Searching cache ...................................... 195 Sending a break signal ............................ 727
U
UBC trigger timing ............................... 1276 UDTDO output timing .......................... 1158 Unconditional branch instructions with no delay slot .............................................. 31 Usage Note.............................................. 770
Rev. 2.00 Sep. 07, 2007 Page 1311 of 1312 REJ09B0320-0200
User break controller (UBC) .................. 165 User break interrupt ................................ 137 User debugging interface (H-UDI)....... 1153 Using interval timer mode ...................... 635 Using watchdog timer mode................... 634
W
Watchdog timer (WDT).......................... 625 Watchdog timer timing ......................... 1279 Write-back buffer (only for operand cache) ......................... 198
V
Vector base register (VBR) ...................... 26
Rev. 2.00 Sep. 07, 2007 Page 1312 of 1312 REJ09B0320-0200
Renesas 32-Bit RISC Microcomputer Hardware Manual SH7261 Group
Publication Date: Rev.1.00, Jul. 31, 2006 Rev.2.00, Sep. 07, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
SH7261 Group Hardware Manual

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